SN54HC166, SN74HC166
SCLS117E – DECEMBER 1982 – REVISED FEBRUARY 2022
SNx4HC166 8-Bit Parallel-Load Shift Registers
1 Features
2 Description
•
•
•
•
•
•
•
•
•
The SNx4HC166 device contains an 8-bit shift
register with one serial input and eight parallel-load
inputs.
Wide operating voltage range of 2 V to 6 V
Outputs can drive up to 10 LSTTL loads
Low power consumption, 80-μA max ICC
Typical tpd = 13 ns
±4-mA output drive at 5 V
Low input current of 1 μA max
Synchronous load
Direct overriding clear
Parallel-to-serial conversion
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HC166D
SOIC (16)
9.90 mm × 3.90 mm
SN74HC166DB
SSOP (16)
6.20 mm × 5.30 mm
SN74HC166N
PDIP (16)
19.31 mm × 6.35 mm
SN74HC166NS
SO (16)
6.20 mm × 5.30 mm
SN74HC166PW
TSSOP (16)
5.00 mm × 4.40 mm
SN54HC166J
CDIP (16)
24.38 mm × 6.92 mm
SNJ54HC166FK
LCCC (20)
8.89 mm × 8.45 mm
SNJ54HC166J
CFP (16)
10.16 mm × 6.73 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC166, SN74HC166
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SCLS117E – DECEMBER 1982 – REVISED FEBRUARY 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions(1) .................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Timing Requirements ................................................. 6
5.6 Switching Characteristics ...........................................7
5.7 Operating Characteristics........................................... 7
6 Parameter Measurement Information............................ 8
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Device Functional Modes............................................9
8 Power Supply Recommendations................................10
9 Layout.............................................................................10
9.1 Layout Guidelines..................................................... 10
10 Device and Documentation Support..........................11
10.1 Receiving Notification of Documentation Updates.. 11
10.2 Support Resources................................................. 11
10.3 Trademarks............................................................. 11
10.4 Electrostatic Discharge Caution.............................. 11
10.5 Glossary.................................................................. 11
11 Mechanical, Packaging, and Orderable
Information.................................................................... 11
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 1982) to Revision E (February 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references thorughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCLS117E – DECEMBER 1982 – REVISED FEBRUARY 2022
4 Pin Configuration and Functions
J, D, DB, N, NS, or PW Package
16-Pin CDIP, SOIC, SSOP, PDIP, SO, TSSOP
Top View
FK Package
20-Pin LCCC
Top View
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SCLS117E – DECEMBER 1982 – REVISED FEBRUARY 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
current(2)
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Section 5.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions(1)
SN54HC166
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 4.5 V
VCC = 6 V
SN74HC166
MIN
NOM
MAX
2
5
6
Low-level input voltage
VI
Input voltage
VO
Output voltage
(2)
5
6
3.15
4.2
4.2
VCC = 4.5 V
0
Input transition rise/fall time VCC = 4.5 V
Operating free-air temperature
−55
0.5
0.5
1.35
1.35
V
V
1.8
VCC
0
VCC
0
VCC
V
VCC
V
1000
1000
500
500
400
400
125
UNIT
V
1.8
0
VCC = 6 V
(1)
2
3.15
VCC = 2 V
TA
MAX
1.5
VCC = 6 V
Δt/Δv(2)
NOM
1.5
VCC = 2 V
VIL
MIN
−40
85
ns
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state
from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
5.3 Thermal Information
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal
(1)
resistance
D (SOIC)
DB (SSOP)
N (PDIP)
NS (SO)
PW (TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
73
82
67
64
108
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCLS117E – DECEMBER 1982 – REVISED FEBRUARY 2022
5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST
(1)
CONDITIONS
VCC (V)
IOH = −20 μA
VOH
IOH = −4 mA
IOH = −5.2 mA
ICC
Ci
(1)
SN54HC166
MAX
MIN
SN74HC166
MIN
TYP
MAX
MIN
2
1.9
1.998
1.9
1.9
4.5
4.4
4.499
4.4
4.4
6
5.9
5.999
5.9
5.9
4.5
3.98
4.3
3.7
3.84
6
5.48
5.8
5.2
5.34
MAX
UNIT
V
2
0.002
0.1
0.1
0.1
IOL = 20 μA
4.5
0.001
0.1
0.1
0.1
6
0.001
0.1
0.1
0.1
IOL = 4 mA
4.5
0.17
0.26
0.4
0.33
IOL = 5.2 mA
6
0.15
0.26
0.4
0.33
VI = VCC or 0
6
±0.1
±100
±1000
±1000
nA
VI = VCC or 0, IO
=0
6
8
160
80
μA
10
10
10
pF
VOL
II
TA = 25°C
2 to 6
3
V
VI = VIH or VIL, unless otherwise noted.
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SCLS117E – DECEMBER 1982 – REVISED FEBRUARY 2022
5.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
VCC(V)
fclock
Clock frequency
CLR low
tw
Pulse duration
CLK high or low
SH/LD high before CLK↑
SER before CLK↑
tsu
Setup time
CLK INH low before CLK↑
Data before CLK↑
CLR inactive before CLK↑
SH/LD high after CLK↑
SER after CLK↑
th
Hold time
CLK INH high after CLK↑
Data after CLK↑
6
TA = 25°C
MIN
SN54HC166
MAX
MIN
SN74HC166
MAX
MIN
MAX
2
6
4.2
5
4.5
31
21
25
6
36
25
29
2
100
150
125
4.5
20
30
25
6
17
26
21
2
80
120
100
4.5
16
24
20
6
14
20
17
2
145
220
180
4.5
29
44
36
6
25
38
31
2
80
120
100
4.5
16
24
20
6
14
20
17
2
100
150
125
4.5
20
30
25
6
17
26
21
2
80
120
100
4.5
16
24
20
6
14
20
17
2
40
60
50
4.5
8
12
10
6
7
10
9
2
0
0
0
4.5
0
0
0
6
0
0
0
2
5
5
5
4.5
5
5
5
6
5
5
5
2
0
0
0
4.5
0
0
0
6
0
0
0
2
5
5
5
4.5
5
5
5
6
5
5
5
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UNIT
MHz
ns
ns
ns
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SCLS117E – DECEMBER 1982 – REVISED FEBRUARY 2022
Figure 5-1. Typical Clear, Shift, Load, Inhibit, and Shift Sequence
5.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 6)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPHL
tpd
tt
CLR
CLK
QH
QH
Any
VCC (V)
TA = 25°C
MIN
TYP
SN54HC166
MAX
MIN
SN74HC166
MAX
MIN
2
6
11
4.2
5
4.5
31
36
21
25
6
36
45
25
MAX
UNIT
MHz
29
2
62
120
180
150
4.5
18
24
36
30
6
13
20
31
26
2
75
150
225
190
4.5
15
30
45
38
6
13
26
38
32
2
38
75
110
95
4.5
8
15
22
19
6
6
13
19
16
ns
ns
ns
5.7 Operating Characteristics
TA = 25℃
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load
TYP
50
UNIT
pF
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SCLS117E – DECEMBER 1982 – REVISED FEBRUARY 2022
6 Parameter Measurement Information
tpd is the maximum between tPLH and tPHL
Figure 6-1. Load Circuit
Figure 6-2. Voltage Waveforms
Pulse Durations
Figure 6-3. Voltage Waveforms
Setup and Hold and Input Rise and Fall Times
Figure 6-4. Voltage Waveforms
Propagation Delay and Output Transition Times
A. CL includes probe and jig capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following charactersitics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%
D. The outputs are measured one at a time with one input transition per measurement.
8
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7 Detailed Description
7.1 Overview
These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding
clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When
high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each
clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs
on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on
the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
7.2 Functional Block Diagram
7.3 Device Functional Modes
Table 7-1. Function Table
OUTPUTS
INPUTS
INTERNAL
QH
CLR
SH/LD
CLK INH
CLK
SER
PARALLEL
A...H
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
QA0
QB0
QH0
H
L
L
↑
X
a...h
a
b
h
H
H
L
↑
H
X
H
QAn
QGn
H
H
L
↑
L
X
L
QAn
QGn
H
X
H
↑
X
X
QA0
QB0
QH0
QA
QB
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
10
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SCLS117E – DECEMBER 1982 – REVISED FEBRUARY 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9050101Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629050101Q2A
SNJ54HC
166FK
5962-9050101QEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9050101QE
A
SNJ54HC166J
5962-9050101VEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9050101VE
A
SNV54HC166J
SN54HC166J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HC166J
Samples
SN74HC166D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC166
Samples
SN74HC166DBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC166
Samples
SN74HC166DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HC166
Samples
SN74HC166DRE4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC166
Samples
SN74HC166DRG4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC166
Samples
SN74HC166N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC166N
Samples
SN74HC166NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC166
Samples
SN74HC166PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC166
Samples
SN74HC166PWG4
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC166
Samples
SN74HC166PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HC166
Samples
SN74HC166PWT
ACTIVE
TSSOP
PW
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC166
Samples
SNJ54HC166FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629050101Q2A
SNJ54HC
166FK
Addendum-Page 1
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
4-Nov-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
SNJ54HC166J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9050101QE
A
SNJ54HC166J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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