SN54HCT541, SN74HCT541
SCLS306E – JANUARY 1996 – REVISED MAY 2022
SNx4HCT541 Octal Buffers and Line Drivers With 3-State Outputs
1 Features
2 Description
•
•
These octal buffers and line drivers are designed to
have the performance of the popular ’HC240 series
devices and to offer a pinout with inputs and outputs
on opposite sides of the package. This arrangement
greatly facilitates printed circuit board layout.
•
•
•
•
•
•
Operating voltage range of 4.5 V to 5.5 V
High-current 3-state outputs interface
directly with system bus or can drive up
to 15 LSTTL loads
Low power consumption, 80-µA max ICC
Typical tpd = 12 ns
±6-mA output drive at 5 V
Low input current of 1 µA max
Inputs are TTL-voltage compatible
Data flow-through pinout (all inputs on opposite
side from outputs)
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HCT541DW
SOIC (20)
12.80 mm × 7.50 mm
SN74HCT541DB
SSOP (20)
7.20 mm × 5.30 mm
SN74HCT541N
PDIP (20)
25.40 mm × 6.35 mm
SN74HCT541NS
SO (20)
15.00 mm × 5.30 mm
SN74HCT541PW
TSSOP (20)
6.50 mm × 4.40 mm
SN54HCT541J
CDIP (20)
26.92 mm × 6.92 mm
SNJ54HCT541FK
LCCC (20)
8.89 mm × 8.45 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HCT541, SN74HCT541
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SCLS306E – JANUARY 1996 – REVISED MAY 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions(1) .................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Switching Characteristics............................................5
5.6 Switching Characteristics............................................5
5.7 Operating Characteristics........................................... 5
6 Parameter Measurement Information............................ 6
7 Detailed Description........................................................7
7.1 Overview..................................................................... 7
7.2 Functional Block Diagram........................................... 7
7.3 Device Functional Modes............................................7
8 Power Supply Recommendations..................................8
9 Layout...............................................................................8
9.1 Layout Guidelines....................................................... 8
10 Device and Documentation Support............................9
10.1 Receiving Notification of Documentation Updates....9
10.2 Support Resources................................................... 9
10.3 Trademarks............................................................... 9
10.4 Electrostatic Discharge Caution................................9
10.5 Glossary....................................................................9
11 Mechanical, Packaging, and Orderable
Information.................................................................... 10
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2022) to Revision E (May 2022)
Page
• Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, DB was 70 is now 122.7,
N was 69 is now 84.6, NS was 60 is now 113.4, PW was 83 is now 131.8........................................................ 4
Changes from Revision C (August 2003) to Revision D (February 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCLS306E – JANUARY 1996 – REVISED MAY 2022
4 Pin Configuration and Functions
OE1
1
20
VCC
A1
2
19
OE2
A2
3
18
Y1
A3
4
17
Y2
A4
5
16
Y3
A5
6
15
Y4
A6
7
14
Y5
A7
8
13
Y6
A8
9
12
Y7
10
11
Y8
GND
J, DB, DW, N, NS, or PW Package
20-Pin CDIP, SSOP, SOIC, PDIP, SO, or TSSOP
Top View
FK Package
20-Pin LCCC
Top View
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SCLS306E – JANUARY 1996 – REVISED MAY 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
current(2)
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature range
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions(1)
SN54HCT541
SN74HCT541
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
∆t/∆v
Input transition rise and fall time
500
ns
TA
Operating free-air temperature
85
°C
(1)
2
2
V
0.8
500
–55
125
V
–40
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5.3 Thermal Information
THERMAL METRIC
4
DW (SOIC)
DB (SSOP)
N (PDIP)
NS (SO)
PW (TSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
UNIT
109.1
122.7
84.6
113.4
131.8
°C/W
76
81.6
72.5
78.6
72.2
°C/W
RθJA
Junction-to-ambient thermal
resistance
RθJC (top)
Junction-to-case (top) thermal
resistance
RθJB
Junction-to-board thermal
resistance
77.6
77.5
65.3
78.4
82.8
°C/W
ΨJT
Junction-to-top characterization
parameter
51.5
46.1
55.3
47.1
21.5
°C/W
ΨJB
Junction-to-board
characterization parameter
77.1
77.1
65.2
78.1
82.4
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
N/A
°C/W
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5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VI = VIH or VIL
VOL
VI = VIH or VIL
II
VI = VCC or 0
VCC
IOH = −20 µA
IOH = −6 mA
IOL = 20 µA
IOL = 6 mA
TYP
MAX
MIN
4.4
4.499
4.4
4.4
3.98
4.3
3.7
3.84
MAX
UNIT
V
0.1
0.1
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
nA
±0.01
±0.5
±10
±5
µA
8
160
80
µA
1.4
2.4
3
2.9
mA
3
10
10
10
pF
5.5 V
VI = VCC or 0,
5.5 V
5.5 V
Ci
MIN
0.1
VO = VCC or 0, VI = VIH or VIL
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
MAX
SN74HCT541
0.001
IOZ
IO = 0
SN54HCT541
MIN
4.5 V
ICC
∆ICC (1)
(1)
4.5 V
TA = 25°C
4.5 V to 5.5 V
V
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
5.5 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 6-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
tt
Y
VCC
TA = 25°C
MIN
SN54HCT541
MIN
MAX
SN74HCT541
TYP
MAX
MIN
MAX
4.5 V
13
23
34
29
5.5 V
12
21
31
26
4.5 V
21
30
45
38
5.5 V
19
27
41
34
4.5 V
19
30
45
38
5.5 V
18
27
41
34
4.5 V
8
12
18
15
5.5 V
7
11
16
14
UNIT
ns
ns
ns
ns
5.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 6-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tt
Y
VCC
TA = 25°C
MIN
SN54HCT541
MIN
MAX
SN74HCT541
TYP
MAX
MIN
MAX
4.5 V
20
33
49
42
5.5 V
19
30
45
38
4.5 V
26
40
60
50
5.5 V
25
36
54
45
4.5 V
17
42
63
53
5.5 V
14
38
57
48
UNIT
ns
ns
ns
5.7 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per buffer/driver
No load
TYP
35
UNIT
pF
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SCLS306E – JANUARY 1996 – REVISED MAY 2022
6 Parameter Measurement Information
VCC
From Output
Under Test
CL
(see Note A)
PARAMETER
tPZH
S1
Test
Point
RL
1 kΩ
ten
RL
tPZL
tPHZ
tdis
S2
tPLZ
1 kΩ
tpd or tt
−−
LOAD CIRCUIT
2.7 V
Input 1.3 V
0.3 V
2.7 V
CL
S1
S2
50 pF
or
150 pF
Open
Closed
Closed
Open
50 pF
50 pF
or
150 pF
Open
Closed
Closed
Open
Open
Open
3V
1.3 V
0.3 V 0 V
tr
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
3V
Input
1.3 V
1.3 V
0V
tPLH
In-Phase
Output
1.3 V
10%
tPHL
90%
90%
tr
Out-ofPhase
Output
tPHL
90%
VOH
1.3 V
10% V
OL
tf
tPLH
1.3 V
10%
tf
1.3 V
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
Output
Control
(Low-Level
Enabling)
3V
1.3 V
1.3 V
0V
tPZL
tPLZ
Output
Waveform 1
(See Note B)
≈VCC
1.3 V
10%
tPZH
VOL
tPHZ
Output
Waveform 2
(See Note B)
1.3 V
90%
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 6-1. Load Circuit and Voltage Waveforms
6
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SCLS306E – JANUARY 1996 – REVISED MAY 2022
7 Detailed Description
7.1 Overview
These octal buffers and line drivers are designed to have the performance of the popular ’HC240 series devices
and to offer a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly
facilitates printed circuit board layout.
The 3-state control gate is a 2-input NOR. If either output-enable (OE1 or OE2) input is high, all eight outputs are
in the high-impedance state. The ’HCT541 devices provide true data at the outputs.
7.2 Functional Block Diagram
7.3 Device Functional Modes
Table 7-1. Function Table
(Each Buffer/Driver)
INPUTS
OE1
OE2
A
OUTPUT
Y
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
8
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
JM38510/65761BRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65761BRA
Samples
M38510/65761BRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65761BRA
Samples
SN54HCT541J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HCT541J
Samples
SN74HCT541DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT541
Samples
SN74HCT541DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT541
Samples
SN74HCT541DWE4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT541
Samples
SN74HCT541DWG4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT541
Samples
SN74HCT541DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT541
Samples
SN74HCT541DWRE4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT541
Samples
SN74HCT541DWRG4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT541
Samples
SN74HCT541N
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT541N
Samples
SN74HCT541NSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT541
Samples
SN74HCT541NSRE4
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT541
Samples
SN74HCT541NSRG4
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT541
Samples
SN74HCT541PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT541
Samples
SN74HCT541PWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT541
Samples
SN74HCT541PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT541
Samples
SN74HCT541PWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT541
Samples
SN74HCT541PWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT541
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SNJ54HCT541FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SNJ54HCT
541FK
Samples
SNJ54HCT541J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SNJ54HCT541J
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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