Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
SN74LV244A
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
SN74LV244A Octal Buffers and Drivers With 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 6.5 ns at 5 V
Typical VOLP (Output Ground Bounce)
2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250-mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Servers and Network Switches
LED Displays
Telecom Infrastructure
Motor-Drive Control Boards
3 Description
The SN74LV244A octal buffers and line drivers are
designed for 2-V to 5.5-V VCC operation.
The SN74LV244A devices are designed specifically
to improve both performance and density of the 3state memory address drivers, clock drivers, and busoriented receivers and transmitters. These devices
are organized as two 4-bit line drivers with separate
output-enable (OE) inputs.
Device Information
PART NUMBER
PACKAGE (PIN)
BODY SIZE
SN74LV244ADGV
TVSOP (20)
5.00 mm × 4.40 mm
SN74LV244ADW
SOIC (20)
12.80 mm × 7.50 mm
SN74LV244ANS
SOP (20)
12.60 mm × 5.30 mm
SN74LV244APW
TSSOP (20)
6.50 mm × 4.40 mm
SN74LV244ARGY
VQFN (20)
4.50 mm × 3.50 mm
Logic Diagram (Positive Logic)
1OE
1A1
1A2
1A3
1A4
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV244A
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
4
4
5
5
6
6
6
6
7
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Noise Characteristics ................................................
Operating Characteristics..........................................
Switching Characteristics: VCC = 2.5 V ± 0.2 V ........
Switching Characteristics: VCC = 3.3 V ± 0.3 V ........
Switching Characteristics: VCC = 5 V ± 0.5 V .........
Typical Characteristics ............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (June 2013) to Revision N
Page
•
Added Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Detailed
Description section, Applications and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...... 1
•
Deleted SN54LV244A part number from the data sheet........................................................................................................ 1
•
Removed the TA = –40°C to 85°C test conditions with the same values as the TA = –40°C to 125°C Recommended
test conditions in the Electrical Characteristics and Switching Characteristics tables .......................................................... 6
•
Removed the word 'Recommended' in the TA = –40°C to 125°C Recommended test conditions in the Electrical
Characteristics and Switching Characteristics tables ............................................................................................................ 6
Changes from Revision L (August 2010) to Revision M
Page
•
Changed document format from Quicksilver to DocZone ..................................................................................................... 1
•
Changed Extended operating temperature range to 125°C ................................................................................................... 1
2
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
SN74LV244A
www.ti.com
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
DB, DGV, DW, NS, PW Package
20-Pin SSOP, TVSOP, SOIC, SO, TSSOP
Top View
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
VCC
19
1
20
19 2OE
18 1Y1
2
3
17 2A4
16 1Y2
4
5
15 2A3
14 1Y3
6
7
13 2A2
12 1Y4
8
9
10
11
2A1
20
2
1OE
1
GND
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
RGY Package
20-Pin VQFN With Exposed Thermal Pad
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1A1
2
I
Input
1A2
4
I
Input
1A3
6
I
Input
1A4
8
I
Input
1OE
1
I
Output enable
1Y1
18
O
Output
1Y2
16
O
Output
1Y3
14
O
Output
1Y4
12
O
Output
2A1
11
I
Input
2A2
13
I
Input
2A3
15
I
Input
2A4
17
I
Input
2OE
19
I
Output enable
2Y1
9
O
Output
2Y2
7
O
Output
2Y3
5
O
Output
2Y4
3
O
Output
GND
10
—
Ground
VCC
20
—
Power pin
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
3
SN74LV244A
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
VI
Input voltage
–0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
Tj
Continuous current through VCC or GND
Junction temperature
–65
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5-V maximum.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
4
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±2000
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
SN74LV244A
www.ti.com
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
High-level input voltage
Low-level input voltage
VI
Input voltage
VO
Output voltage
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
High-level output current
5.5
High or low state
0
VCC
3-state
0
5.5
Δt/Δv
Input transition rise or fall rate
VCC = 3 V to 3.6 V
(1)
µA
–8
mA
–16
50
VCC = 2.3 V to 2.7 V
µA
2
VCC = 3 V to 3.6 V
8
VCC = 4.5 V to 5.5 V
16
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
V
–2
VCC = 2 V
Low-level output current
V
–50
VCC = 2.3 V to 2.7 V
VCC = 4.5 V to 5.5 V
IOL
V
VCC × 0.3
0
VCC = 2 V
IOH
V
1.5
VCC = 2 V
VIL
UNIT
mA
ns/V
20
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LV244A
THERMAL METRIC (1)
DB
(SSOP)
DGV
(TVSOP)
DW
(SOIC)
NS
(SO)
PW
(TSSOP)
RGY
(VQFN)
UNIT
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
RθJA
Junction-to-ambient thermal
resistance
94.7
115.9
79.4
76.9
102.6
34.9
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
56.7
31.1
43.8
43.4
36.7
43.1
°C/W
RθJB
Junction-to-board thermal resistance
49.9
57.4
47.2
44.5
53.6
12.7
°C/W
ψJT
Junction-to-top characterization
parameter
18.7
1.0
18.8
17.0
2.4
0.9
°C/W
ψJB
Junction-to-board characterization
parameter
49.5
56.7
46.7
44.1
53.1
12.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
n/a
n/a
n/a
n/a
n/a
7.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
5
SN74LV244A
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
www.ti.com
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VCC
MIN
TYP
MAX
IOH = –50 µA
TA = –40°C to 125°C
2 V to
5.5 V
IOH = –2 mA
TA = –40°C to 125°C
2.3 V
IOH = –8 mA
TA = –40°C to 125°C
3V
2.48
IOH = 16 mA
TA = –40°C to 125°C
4.5 V
3.8
IOL = 50 µA
TA = –40°C to 125°C
2 V to
5.5 V
IOL = 2 mA
TA = –40°C to 125°C
2.3 V
0.4
IOL = 8 mA
TA = –40°C to 125°C
3V
0.44
0.55
UNIT
VCC – 0.1
2
V
0.1
V
IOL = 16 mA
TA = –40°C to 125°C
4.5 V
II
VI = 5.5 V or GND
TA = –40°C to 125°C
0 to 5.5 V
±1
µA
IOZ
VO = VCC or GND
TA = –40°C to 125°C
5.5 V
±5
µA
ICC
VI = VCC or GND, IO =
0
TA = –40°C to 125°C
5.5 V
20
µA
Ioff
VI or VO = 0 to 5.5 V
TA = –40°C to 125°C
0
5
µA
Ci
VI = VCC or GND
TA = –40°C to 125°C
3.3 V
2.3
pF
6.6 Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C (1)
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic
0.55
V
VOL(V)
Quiet output, minimum dynamic
–0.5
V
VOH(V)
Quiet output, minimum dynamic
2.9
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
6.7 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
VCC
CL = 50 pF, f = 10 MHz
TYP
3.3 V
14
5V
16
UNIT
pF
6.8 Switching Characteristics: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tpd
A
Y
CL = 15 pF
ten
OE
Y
CL = 15 pF
tdis
OE
Y
CL = 15 pF
tpd
A
Y
CL = 50 pF
ten
OE
Y
CL = 50 pF
(1)
6
TEST CONDITIONS
MIN
TA = 25°C
TA = –40°C to 125°C
1
TA = –40°C to 125°C
9.1
14.1
9.5 (1)
15.3
18
10.8
UNIT
ns
ns
(1)
16
1
1
14.6 (1)
17
(1)
1
TA = 25°C
12.5
15
8.9 (1)
TA = 25°C
TA = –40°C to 125°C
(1)
7.5
TA = 25°C
TA = –40°C to 125°C
MAX
(1)
1
TA = 25°C
TA = –40°C to 125°C
TYP
17.8
21
ns
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
SN74LV244A
www.ti.com
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
Switching Characteristics: VCC = 2.5 V ± 0.2 V (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
OE
Y
CL = 50 pF
tdis
tsk(o)
CL = 50 pF
TEST CONDITIONS
MIN
TA = 25°C
TA = –40°C to 125°C
TYP
MAX
13.4
19.2
1
UNIT
ns
21
TA = 25°C
2
TA = –40°C to 125°C
2
ns
6.9 Switching Characteristics: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tpd
A
Y
CL = 15 pF
ten
OE
Y
CL = 15 pF
tdis
OE
Y
CL = 15 pF
tpd
A
Y
CL = 50 pF
ten
OE
Y
CL = 50 pF
tdis
OE
Y
CL = 50 pF
tsk(o)
(1)
CL = 50 pF
TEST CONDITIONS
MIN
TA = 25°C
TA = –40°C to 125°C
(1)
(1)
5.4
6.3 (1)
7.6 (1)
ns
11.7 (1)
ns
13
6.8
1
11.9
ns
13.5
7.8
14.1
1
ns
16
TA = 25°C
TA = –40°C to 125°C
10.6 (1)
1
TA = 25°C
TA = –40°C to 125°C
ns
12.5
TA = 25°C
TA = –40°C to 125°C
8.4
UNIT
10
1
TA = 25°C
TA = –40°C to 125°C
MAX
1
TA = 25°C
TA = –40°C to 125°C
TYP
11
16
1
ns
18
TA = 25°C
1.5
TA = –40°C to 125°C
1.5
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.10 Switching Characteristics: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tpd
A
Y
CL = 15 pF
ten
OE
Y
CL = 15 pF
tdis
OE
Y
CL = 15 pF
tpd
A
Y
CL = 50 pF
ten
OE
Y
CL = 50 pF
tdis
OE
Y
CL = 50 pF
tsk(o)
(1)
TEST CONDITIONS
MIN
TA = 25°C
TA = –40°C to 125°C
1
TA = –40°C to 125°C
1
TA = –40°C to 125°C
4.9
7.5
8.5
5.6
1
9.3
10.5
8.8
1
12.2 (1)
13.5
1
TA = 25°C
7.3 (1)
8.5
6.5 (1)
TA = 25°C
5.5
UNIT
6.5
4.5 (1)
TA = 25°C
TA = –40°C to 125°C
(1)
3.9
TA = 25°C
TA = –40°C to 125°C
MAX
(1)
1
TA = 25°C
TA = –40°C to 125°C
TYP
14.2
15.5
TA = 25°C
1
TA = –40°C to 85°C
1
ns
ns
ns
ns
ns
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
7
SN74LV244A
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
www.ti.com
Input Voltage
Output Voltage
6.11 Typical Characteristics
Output Current
Input Current
Figure 1. Input Voltage vs Input Current
8
Figure 2. Output Voltage vs Output Current
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
SN74LV244A
www.ti.com
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
7 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
CC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
tPLZ
≈VCC
50% VCC
tPZH
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
VOH
50% VCC
VOL
50% VCC
tPZL
tPHL
tPHL
Out-of-Phase
Output
0V
VCC
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns,
tf ≤ 3 ns.
D.
The outputs are measured one at a time, with one input transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPZL and tPZH are the same as ten.
G.
tPHL and tPLH are the same as tpd.
H.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
9
SN74LV244A
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
www.ti.com
8 Detailed Description
8.1 Overview
The SN74LV244 devices are octal buffers grouped in fours, with each group having its own enable pin. The LV
family supports high current drive of about 16 mA, thus making it suitable for driving digital signals over longer
board lengths. This device is generally used to buffer or incorporate delays between the signals between two
microcontroller or peripheral devices.
8.2 Functional Block Diagram
1OE
1A1
1A2
1A3
1A4
1
19
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
8.3 Feature Description
The SN74LV244A, a part of LV family, can work over a wide voltage range from 2 V to 5.5 V. The device
features a very low propagation delay of about 6.5 ns when enabled for 5-V VCC, which allows the device to be
used for high-speed applications. The device supports a partial-power-down mode for low quiescent current
application, thus making it the buffer of choice in power-efficient circuits. The Ioff circuitry also disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
8.4 Device Functional Modes
The SN74LV244A devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When
OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state. To ensure the high-impedance state during power up or power down, OE must be tied to
VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
Table 1. Function Table
INPUTS
10
OUTPUTS
OE
A
Y
L
L
L
L
H
H
H
X
Z
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
SN74LV244A
www.ti.com
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LV244A device can be used as an 8-channel buffer to drive signals from one controller to another
device. Buffers are typically used for signals running on long traces on printed circuit boards or going through
connectors linking two printed circuit boards together. Buffers are also used to create delay between the lines to
match the edges of two clock or data signals. The high-current capability of the SN74LV244A device also allows
a controller to drive LEDs up to 16 mA.
9.2 Typical Application
1OE
1
1A1
2
1A2
1A3
1A4
16
Controller
1B1
18
1B2
1B3
8
1B4
12
16
2OE
19
2A1
11
2A4
2B1
9
2A2
2A3
Controller
Device
/('¶V
2B2
2B3
17
2B4
3
Gnd
VCC
10
20
0.1uF
Figure 4. Typical Application Diagram
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
11
SN74LV244A
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
www.ti.com
Typical Application (continued)
9.2.1 Design Requirements
A 0.1-µF bypass capacitor must be placed between each VCC pin and GND. For best results, each capacitor
must be placed as close as possible to the SN74LV244A device.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions
– Inputs and outputs are overvoltage tolerant, which allows them to go as high as 5.5 V at any valid VCC
2. Recommended output conditions:
– Load currents must not exceed limits as mentioned in Recommended Operating Conditions
3. Frequency selection criterion:
– Added trace resistance or capacitance can reduce maximum frequency capability; use layout practices as
directed in Layout Guidelines
Voltage
9.2.3 Application Curve
Time
Figure 5. SN74LV244A Transient response
12
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
SN74LV244A
www.ti.com
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply-voltage rating listed in the
Absolute Maximum Ratings table.
Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dualsupply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. For best results, the bypass capacitor must be
installed as close as possible to the power terminal.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self-inductance of the trace, which results in the reflection. Not all PCB traces can be straight;
therefore, some traces must turn corners. Figure 6 shows progressively better techniques of rounding corners.
Only the last example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 6. Trace Example
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
13
SN74LV244A
SCLS383N – SEPTEMBER 1997 – REVISED OCTOBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN74LV244A
PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LV244ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244ADBRE4
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244ADBRG4
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244ADGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244ADW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244ADWE4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244ADWG4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244ADWRG4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244ANSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV244A
SN74LV244APW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244APWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244APWRE4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244APWRG3
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244APWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV244A
SN74LV244ARGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV244A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2022
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
