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SN74LVC07A
SCAS595W – OCTOBER 1997 – REVISED OCTOBER 2016
SN74LVC07A Hex Buffer and Driver With Open-Drain Outputs
1 Features
3 Description
•
•
The SN74LVC07A device is a hex buffer and driver
that is designed for 1.65-V to 5.5-V VCC operation.
1
•
•
•
Operates From 1.65 V to 5 V
Inputs and Open-Drain Outputs Accept Voltages
Up to 5.5 V
Max tpd of 2.6 ns at 5 V
Latch-Up Performance Exceeds 250 mA
Per JESD 17
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
2 Applications
•
•
•
•
•
•
•
•
•
•
•
Device Information(1)
PART NUMBER
PACKAGE
SOIC (14)
8.65 mm × 3.91 mm
SN74LVC07ADB
SSOP (14)
6.20 mm × 5.30 mm
SN74LVC07ADGV TVSOP (14)
3.60 mm × 4.40 mm
SN74LVC07APW
TSSOP (14)
5.00 mm × 4.40 mm
SN74LVC07ANS
SO (14)
10.30 mm × 5.30 mm
SN74LVC07ARGY VQFN (14)
AV Receiver
Audio Dock: Portable
Blu-ray Player and Home Theater
MP3 Player or Recorder
Personal Digital Assistant (PDA)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid State Drive (SSD): Client and Enterprise
TV: LCD, Digital, and High-Definition (HDTV)
Tablet: Enterprise
Video Analytics: Server
Wireless Headset, Keyboard, and Mouse
BODY SIZE (NOM)
SN74LVC07AD
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
A
Y
Copyright © 2016 Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC07A
SCAS595W – OCTOBER 1997 – REVISED OCTOBER 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
6
6
6
7
7
Parameter Measurement Information .................. 8
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics—DC Limit Changes..........
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
VCC = 1.8 V ± 0.15 V................................................. 8
VCC = 2.5 V ± 0.2 V................................................... 9
VCC = 2.7 and 3.3 V ± 0.3 V ................................... 10
VCC = 5 V ± 0.5 V.................................................... 11
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision V (May 2015) to Revision W
Page
•
Changed Pin Functions table ................................................................................................................................................ 4
•
Added Junction temperature to the Absolute Maximum Ratings table .................................................................................. 5
•
Reformatted the Electrical Characteristics and the Switching Characteristics tables ........................................................... 6
•
Changed Typical Application Diagram ................................................................................................................................ 13
•
Added Receiving Notification of Documentation Updates section ...................................................................................... 16
Changes from Revision U (June 2014) to Revision V
Page
•
Changed Handling Ratings table to ESD Ratings table ........................................................................................................ 5
•
Added industry standard terms to package designators in the Thermal Information table .................................................... 6
•
Changed from "High" to "High-Z" in the Function Table ..................................................................................................... 12
Changes from Revision T (February 2011) to Revision U
Page
•
Updated document to new TI data sheet format .................................................................................................................... 1
•
Removed Ordering Information table ..................................................................................................................................... 1
•
Added Applications ................................................................................................................................................................. 1
•
Added Ioff Features bullet........................................................................................................................................................ 1
•
Added Device Information table ............................................................................................................................................. 1
•
Added Handling Ratings table. ............................................................................................................................................... 5
•
Changed MAX operating free-air temperature from 85°C to 125°C....................................................................................... 5
•
Updated Thermal Information table. ...................................................................................................................................... 6
•
Added –40°C TO +125°C temperature range to Electrical Characteristics table................................................................... 6
•
Added Switching Characteristics table for –40°C TO 125°C temperature range................................................................... 6
2
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•
SCAS595W – OCTOBER 1997 – REVISED OCTOBER 2016
Added Typical Characteristics ................................................................................................................................................ 7
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5 Pin Configuration and Functions
D, DB, DGV, NS, PW Package
14-Pin SOIC, SSOP, TVSOP, SO, TSSOP
Top View
RGY Package
14-Pin VQFN
Top View
Pin Functions
PIN
NO.
4
NAME
I/O
DESCRIPTION
1
1A
I
Input 1
2
1Y
O
Output 1
3
2A
I
Input 2
4
2Y
O
Output 2
5
3A
I
Input 3
6
3Y
O
Output 3
7
GND
—
Ground pin
8
4Y
O
Output 4
9
4A
I
Input 4
10
5Y
O
Output 5
11
5A
I
Input 5
12
6Y
O
Output 6
13
6A
I
Input 6
14
VCC
—
Power pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
–0.5
6.5
V
–0.5
6.5
V
VI
Input voltage
VO
Output voltage
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
150
°C
150
°C
Tj
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
5.5
Low-level input voltage
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
5.5
V
IOL
Low-level output current
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
VCC = 4.5 V
TA
(1)
Operating free-air temperature
mA
24
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74LVC07A
THERMAL METRIC (1)
D
(SOIC)
DB
(SSOP)
DGV
(TVSOP)
NS
(SO)
PW
(TSSOP)
RGY
(VQFN)
UNIT
160.3
80.6
°C/W
14 PINS
RθJA
Junction-to-ambient thermal resistance
177.4
135.1
157.7
120.3
RθJC(top)
Junction-to-case (top) thermal resistance
75.4
86.7
78.3
76.3
84.4
97.0
°C/W
RθJB
Junction-to-board thermal resistance
70.6
82.4
90.8
79.0
102.1
56.7
°C/W
ψJT
Junction-to-top characterization parameter
34.7
43.7
21.0
36.2
24.3
16.7
°C/W
ψJB
Junction-to-board characterization parameter
70.4
81.9
90.1
78.7
101.4
56.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
n/a
n/a
35.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics—DC Limit Changes
TA = –40°C to +125°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
IOL = 100 µA
IOL = 4 mA
VOL
IOL = 12 mA
IOL = 24 mA
II
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = VCC or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
(1)
IO = 0
VCC
MIN
TYP (1)
MAX
1.65 V to 5.5 V
0.2
1.65 V
0.45
2.3 V
0.7
2.7 V
0.4
3V
0.55
UNIT
V
3.6 V
±5
µA
0V
±10
µA
3.6 V
10
µA
2.7 V to 3.6 V
500
µA
3.3 V
5.0
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 through Figure 6)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
–40°C to 85°C
tpd
A
Y
–40°C to 125°C
6
MIN
MAX
VCC = 1.8 V ± 0.15 V
1
5.6
VCC = 2.5 V ± 0.2 V
1
3.4
VCC = 2.7 V
1
3.3
VCC = 3.3 V ± 0.3 V
1
3.6
VCC = 5 V ± 0.5 V
1
2.6
VCC = 1.8 V ± 0.15 V
1
6.1
VCC = 2.5 V ± 0.2 V
1
3.9
VCC = 2.7 V
1
3.8
VCC = 3.3 V ± 0.3 V
1
4.1
VCC = 5 V ± 0.5 V
1
3.1
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UNIT
ns
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6.7 Operating Characteristics
TA = 25°C
Cpd
PARAMETER
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
Power dissipation capacitance
per buffer and driver
f = 10 MHz
1.8
2
2.5
3.78
UNIT
pF
2.5
2.5
2
2
1.5
1.5
TPD - ns
TPD - ns
6.8 Typical Characteristics
1
1
0.5
0.5
TPD in ns
TPD in ns
0
0
1
2
3
VCC - V
4
5
6
0
-100
D001
Figure 1. TPD vs VCC
-50
0
50
Temperature (qC)
100
150
D002
Figure 2. TPD vs Temperature
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7 Parameter Measurement Information
7.1 VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tPZL (see Note F)
2 × VCC
tPLZ (see Note G)
2 × VCC
tPHZ/tPZH
2 × VCC
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VCC
VCC/2
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at 2 × VCC
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.15 V
VOL
tPHZ
tPZH
tPHL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VCC
VCC − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.15 V.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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7.2 VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tPZL (see Note F)
2 × VCC
tPLZ (see Note G)
2 × VCC
tPHZ/tPZH
2 × VCC
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC
VCC/2
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at 2 × VCC
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.15 V
VOL
tPHZ
tPZH
tPHL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VCC
VCC − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.15 V.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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7.3 VCC = 2.7 and 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPZL (see Note F)
6V
tPLZ (see Note G)
6V
tPHZ/tPZH
6V
LOAD CIRCUIT
tw
2.7 V
2.7 V
Timing
Input
0V
0V
2.7 V
1.5 V
1.5 V
0V
1.5 V
1.5 V
0V
tPLH
2.7 V
1.5 V
tPLZ
3V
1.5 V
VOL
Output
Waveform 2
S1 at 6 V
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
3V
1.5 V
Output
Control
(low-level
enabling)
tPZL
2.7 V
Output
VOLTAGE WAVEFORMS
PULSE DURATION
th
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.5 V
1.5 V
tsu
Data
Input
1.5 V
Input
3V
1.5 V
2.7 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at 1.5 V.
G. tPLZ is measured at VOL + 0.3 V.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
10
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7.4 VCC = 5 V ± 0.5 V
2 x VCC
500 Ω
2 x VCC
2 x VCC
500 Ω
2 x VCC
Output
Waveform 1
S1 at 2 x VCC
(see Note B)
Output
Waveform 2
S1 at 2 x VCC
(see Note B)
0.3 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal connections such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal connections such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.3 V.
H. All parameters and waveforms are not applicable to all devices.
Figure 6. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The outputs of the SN74LVC07A device are open drain and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA.
Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of
this device as translators in a mixed-system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
A
Y
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8.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 5.5 V
Allows up or down voltage translation
– Inputs and outputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC07A.
Table 1. Function Table
12
INPUT
A
OUTPUT
Y
H
Hi-Z
L
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC07A device is a high-drive, open-drain CMOS device that can be used for a multitude of buffertype functions. It can produce 24 mA of drive current at 3.3 V. Therefore, this device is ideal for driving multiple
inputs and for high-speed applications up to 100 MHz. The inputs and outputs are 5.5-V tolerant allowing the
device to translate up to 5.5 V or down to VCC.
9.2 Typical Application
Basic LED Driver
Buffer Function
VPU
VPU
Wired OR
µC or Logic µC or Logic
µC or Logic
LVC07A
LVC07A
µC or Logic
LVC07A
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Figure 7. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads;
therefore, routing and load conditions must be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions
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Typical Application (continued)
– Load currents must not exceed 25 mA per output and 50 mA total for the part.
– Outputs must not be pulled above 5.5 V.
9.2.3 Application Curve
1600
ICC 1.8 V
ICC 2.5 V
ICC 3.3 V
ICC 5 V
1400
TPD - ns
1200
1000
800
600
400
200
0
0
20
40
VCC - V
60
80
D003
Figure 8. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
0.1 µf is recommended; if there are multiple VCC pins, then 0.01 µf or 0.022 µf is recommended for each power
pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 µf and a 1 µf
are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for
best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs must never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 9 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the
part is a transceiver.
14
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SN74LVC07A
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SCAS595W – OCTOBER 1997 – REVISED OCTOBER 2016
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 9. Layout Diagram
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004.
• Semiconductor and IC Package Thermal Metrics, SPRA953.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC07AD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC07A
Samples
SN74LVC07ADBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC07A
Samples
SN74LVC07ADE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC07A
Samples
SN74LVC07ADGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC07A
Samples
SN74LVC07ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LVC07A
Samples
SN74LVC07ADRG3
ACTIVE
SOIC
D
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LVC07A
Samples
SN74LVC07ADRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC07A
Samples
SN74LVC07ADT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC07A
Samples
SN74LVC07ANSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC07A
Samples
SN74LVC07APW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC07A
Samples
SN74LVC07APWE4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC07A
Samples
SN74LVC07APWG4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC07A
Samples
SN74LVC07APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LC07A
Samples
SN74LVC07APWRE4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC07A
Samples
SN74LVC07APWRG3
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LC07A
Samples
SN74LVC07APWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC07A
Samples
SN74LVC07APWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC07A
Samples
SN74LVC07APWTG4
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC07A
Samples
SN74LVC07ARGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC07A
Samples
SN74LVC07ARGYRG4
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC07A
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2022
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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