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SN74LVC1404
SCES469F – AUGUST 2003 – REVISED MARCH 2020
SN74LVC1404 Oscillator Driver for Crystal Oscillator or Ceramic Resonator
1 Features
2 Applications
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Available in the Texas Instruments
NanoFree™ package
Supports 5-V VCC operation
Inputs accept voltages to 5.5 V
One buffered inverter with Schmitt-trigger input
and two unbuffered inverters
Integrated solution for oscillator applications
Suitable for commonly used clock frequencies:
– 15 kHz, 3.58 MHz, 4.43 MHz, 13 MHz,
25 MHz, 26 MHz, 27 MHz, 28 MHz
Control input to disable the oscillator circuit
Low power consumption (10-µA Max ICC) in
standby state
±24-mA Output Drive at 3.3 V
Ioff supports live insertion, partial-power-down
mode, and back-drive protection
Latch-up performance exceeds 100 mA
Per JESD 78, Class II
ESD protection exceeds JESD 22
– 2000-V Human-body model (A114-A)
– 200-V Machine model (A115-A)
– 1000-V Charged-device model (C101)
Servers
PCs and notebooks
Network switches
Wearable health and fitness devices
Telecom infrastructures
Electronic points-of-sale
3 Description
The SN74LVC1404 device consists of one inverter
with a Schmitt-trigger input and two unbuffered
inverters. It is designed for 1.65-V to 5.5-V VCC
operation.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1404DCT
SM8 (8)
2.95 mm × 2.80 mm
SN74LVC1404DCU
VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC1404YZP
DSBGA (8)
1.88 mm × 0.88 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
CTRL
XIN
XOUT
1
3
OSCOUT
2
6
A
7
5
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1404
SCES469F – AUGUST 2003 – REVISED MARCH 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
4
4
5
5
6
7
7
7
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, CL = 15 pF ......................
Switching Characteristics, CL = 30 pF or 50 pF........
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
9
Detailed Description ............................................ 10
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 17
12 Layout................................................................... 17
12.1 Layout Guidelines ................................................. 17
12.2 Layout Example .................................................... 17
13 Device and Documentation Support ................. 18
13.1 Trademarks ........................................................... 18
13.2 Electrostatic Discharge Caution ............................ 18
13.3 Glossary ................................................................ 18
14 Mechanical, Packaging, and Orderable
Information ........................................................... 18
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2014) to Revision F
Page
•
Formatted pinout figures for search capability ....................................................................................................................... 3
•
Corrected pin numbering for the DSBGA package to match the mechanical drawing ......................................................... 3
•
Changed ESD Ratings table format to comply with JEDEC standards ................................................................................ 4
•
Added YZP TA MIN /MAX specs and package thermal information ...................................................................................... 5
Changes from Revision D (January 2007) to Revision E
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. ................................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added Handling Ratings table. .............................................................................................................................................. 4
•
Changed MAX ambient temperature to 125°C....................................................................................................................... 5
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added Typical Characteristics. .............................................................................................................................................. 7
2
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SCES469F – AUGUST 2003 – REVISED MARCH 2020
6 Pin Configuration and Functions
DCT Package
8-Pin SSOP
Top View
DCU Package
8-Pin VSSOP
Top View
YZP Package
8-Ball DSBGA
Bottom View
D
C
B
A
1
2
Drawings not to scale
Pin Functions
PIN NO.
NAME
I/O
DESCRIPTION
DCT/DCU
YZP
1
A1
CTRL
I
OSC Control
2
B1
XOUT
O
Crystal Connection Out
3
C1
XIN
I
Crystal Connection In
4
D1
GND
—
Ground
5
D2
Y
O
Schmitt Trigger Output
6
C2
A
I
Schmitt Trigger Input
7
B2
OSCOUT
O
Oscillator Output
8
A2
VCC
—
Power Supply
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SCES469F – AUGUST 2003 – REVISED MARCH 2020
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
(2)
MIN
MAX
–0.5
6.5
UNIT
V
VI
Input voltage range
XIN, A, CTRL inputs
–0.5
6.5
V
VO
Voltage range applied to any output
in the high-impedance or power-off state (2)
Y output
–0.5
6.5
V
VO
Voltage range applied to any output
in the high or low state (2) (3)
XOUT, OSCOUT
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
Continuous current through VCC or GND
Tstg
Storage Temperature Range
TJ
Junction Temperature
(1)
(2)
(3)
-65
±50
mA
±100
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 ESD Ratings
MAX
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
Operating
MIN
MAX
1.65
5.5
UNIT
VCC
Supply voltage
VI
Input voltage (XIN, CTRL, A inputs)
0
5.5
V
VO
Output voltage (XOUT, OSCOUT, Y outputs)
0
VCC
V
Data retention only
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current (OSCOUT, XOUT, Y outputs)
–8
–16
VCC = 3 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
Low-level output current (OSCOUT, XOUT, Y outputs)
8
16
VCC = 3 V
IOL
Δt/Δv
Low-level output current (XOUT)
32
VCC = 1.65 V
Input transition rise and fall time (CTRL input)
2
VCC = 1.8 V ± 0.15 V
20
VCC = 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
(1)
(2)
Operating free-air temperature
mA
24
VCC = 4.5 V
(2)
mA
–24
VCC = 4.5 V
IOL
V
1.5
mA
ns/V
5
DCU, DCT
–40
125
YZP
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CTRL = Low, XIN = GND
7.4 Thermal Information
THERMAL METRIC (1)
DCT
DCU
YZP
8 PINS
8 PINS
8 BALLS
97.5
RθJA
Junction-to-ambient thermal resistance
184.8
198.4
RθJC(top)
Junction-to-case (top) thermal resistance
115.3
73.5
1.1
RθJB
Junction-to-board thermal resistance
97.3
77.1
26.3
ψJT
Junction-to-top characterization parameter
40.9
6.1
0.5
ψJB
Junction-to-board characterization parameter
96.3
76.7
26.2
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VT+
Positivegoing
threshold
VT–
Negativegoing
threshold
ΔVT
hysteresis
(VT+ – VT– )
TEST CONDITIONS
A input
A input
A input
MIN
1.65 V
0.79
1.16
2.3 V
1.11
1.56
3V
1.5
1.87
4.5 V
2.16
2.74
VOH (2)
VOL (2)
5.5 V
2.61
3.33
0.39
0.62
2.3 V
0.58
0.87
3V
0.84
1.14
4.5 V
1.41
1.79
5.5 V
1.87
2.29
1.65 V
0.37
0.62
2.3 V
0.48
0.77
3V
0.56
0.87
4.5 V
0.71
1.04
0.71
1.11
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
IOH = –16 mA
3V
2.4
IOH = –24 mA
3V
2.3
IOH = –32 mA
4.5 V
3.8
IOL = 100 µA
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
IOL = 16 mA
3V
0.4
IOL = 24 mA
3V
0.55
IOL = 32 mA
4.5 V
0.55
IOL = 100 µA
XOUT
II
All inputs
VI = 5.5 V or GND
Ioff
Y output
VI or VO = 0 to 5.5 V
IOL = 2 mA
CTRL = Low, XIN = GND
VI = VCC or GND,
ΔICC
CTRL and A
inputs
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
CTRL and A
inputs
VI = VCC or GND
IO = 0
6
V
V
V
V
1.65 V to 5.5 V
0.1
1.65 V
0.65
V
V
0 to 5.5 V
±5
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
3.3 V
XIN
(1)
(2)
UNIT
VCC – 0.1
IOH = –4 mA
VOL
ICC
MAX
1.65 V
5.5 V
IOH = –100 µA
TYP (1)
VCC
3.5
pF
6
All typical values are at VCC = 3.3 V, TA = 25°C.
VIL = 0 V and VIH = VCC for XOUT and OSCOUT; the standard VT+ and VT– levels should be applied for the Y output.
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7.6 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
tpd
XIN
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Y
2.8
15.1
1.6
5.7
1.5
4.6
0.9
4.4
XOUT
1.7
9.6
1
3.2
1.1
2.4
0.9
1.8
OSCOUT
2.6
17.2
2
5.6
2
4.1
1.5
3.2
3
28.2
1.8
14.4
1.5
12.2
1.1
10.2
CTRL
XOUT
UNIT
ns
7.7 Switching Characteristics, CL = 30 pF or 50 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
tpd
VCC = 1.8 V
± 0.15 V
VCC = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
Y
XIN
VCC = 2.5 V
± 0.2 V
VCC = 5 V
± 0.5 V
MIN
MAX
3
17.3
1.8
7.4
1.8
6.4
1
5.3
XOUT
1.2
15.8
0.8
5.8
1
5.4
0.6
4.6
OSCOUT
3.5
25.7
2.6
7.1
2.8
7.8
2
6.7
XOUT
3.3
24.5
2.1
12
1.9
12.7
1.1
11.2
CTRL
UNIT
ns
7.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
25
26
29
39
UNIT
pF
7.9 Typical Characteristics
Figure 1 shows the open-loop-gain characteristics of the unbuffered inverter of the LVC1404 (that is, between XIN and
XOUT). The device provides a high gain over a wide range of frequencies. spacer
30
Gain − dBV
20
VCC = 5 V
VCC = 3.3 V
VCC = 2.7 V
10
0
VCC = 1.8 V
−10
0.1
1
10
Frequency − MHz
100
Figure 1. Open-Loop-Gain Characteristics
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
RL
(Except tPZ)
VM
VLOAD
CL
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
RL
(tPZ)
V∆
1 kΩ
1 kΩ
1 kΩ
1 kΩ
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
tw
VM
0V
VI
Input
VM
tsu
VM
VI
0V
Data Input
VM
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
VM
0V
VOH
VM
Output
VM
VOL
VM
VM
0V
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VI
Output
Control
tPZL
tPHL
tPLH
VM
0V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
th
VM
VOL
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + V∆
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SN74LVC1404 device consists of one inverter with a Schmitt-trigger input and two unbuffered inverters. It is
designed for 1.65-V to 5.5-V VCC operation.
XIN and XOUT pins can be connected to a crystal or resonator in oscillator applications. The SN74LVC1404
device provides an additional unbuffered inverter (OSCOUT) and a Schmitt-trigger input inverter for signal
conditioning (see the Functional Block Diagram). The control (CTRL) input disables the oscillator circuit to reduce
power consumption. The oscillator circuit is disabled and the XOUT output is set to low level when CTRL is low.
To ensure the oscillator circuit remains disabled during power up or power down, CTRL should be connected to
GND through a pulldown resistor. The minimum value of the resistor is determined by the current-sourcing
capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
9.2 Functional Block Diagram
CTRL(1)
XOUT
OSCOUT
XIN
CLOAD
RF ≅2.2 MΩ
CL ≅16 pF
RLOAD
Rs ≅1 kΩ
Optional Signal-Conditioning Stage
Y
C1 ≅32 pF
C2 ≅32 pF
A
CLOAD
RLOAD
9.3 Feature Description
•
•
•
•
10
Wide operating voltage range
– Operates from 1.65 V to 5.5 V
Has buffered output and un-buffered output from oscillator
Schmitt-trigger buffer
– Allows for extra buffering of the oscillator output
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
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9.4 Device Functional Modes
Table 1. Function Table
INPUTS
OUTPUTS
CTRL
XIN
XOUT
H
L
H
OSCOUT
L
H
H
L
H
L
X
L
H
Table 2. Function Table
INPUT
A
OUTPUT
Y
L
H
H
L
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10 Application and Implementation
10.1 Application Information
Figure 4 shows a typical application of the SN74LVC1404 device in a Pierce oscillator circuit. The output voltage
can be conditioned further by connecting OSCOUT to the Schmitt-trigger input inverter. The Schmitt-trigger input
inverter produces a rail-to-rail voltage waveform. The recommended load for the crystal, shown in this example,
is 16 pF. The value of the recommended load (CL) can be found in the crystal manufacturer's data sheet. Values
C C
CL = 1 2
C1 + C2 and C1 ≉ C2. Rs is the current-limiting resistor, and the value
of C1 and C2 are chosen so that
depends on the maximum power dissipation of the crystal. Generally, the recommended value of Rs is specified
in the crystal manufacturer's data sheet and, usually, this value is approximately equal to the reactance of C2 at
resonance frequency, that is, RS = XC2. RF is the feedback resistor that is used to bias the inverter in the linear
region of operation. Usually, the value is chosen to be within 1 MΩ to 10 MΩ.
10.2 Typical Application
CTRL(1)
Rs ≅1 kΩ
XOUT
1
8
VCC
2
7
OSCOUT
CLOAD
RLOAD
RF ≅2.2 MΩ
CL ≅16 pF
C2 ≅32 pF
XIN
3
A
6
C1 ≅ 32 pF
GND
Optional Signal-Conditioning Stage
Y
5
4
CLOAD
RLOAD
Figure 4. Typical Application Diagram
12
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Typical Application (continued)
10.2.1 Design Requirements
• The open-loop gain of the unbuffered inverter decreases as power-supply voltage decreases. This decreases
the closed-loop gain of the oscillator circuit. The value of Rs can be decreased to increase the closed-loop
gain, while maintaining the power dissipation of the crystal within the maximum limit.
• Rs and C2 form a low-pass filter and reduce spurious oscillations. Component values can be adjusted, based
on the desired cutoff frequency.
• C2 can be increased over C1 to increase the phase shift and help in start-up of the oscillator. Increasing C2
may affect the duty cycle of the output voltage.
• At high frequency, phase shift due to Rs becomes significant. In this case, Rs can be replaced by a capacitor
to reduce the phase shift.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions
– Load currents should not exceed 50 mA per output and 100 mA total for the part.
– Outputs should not be pulled above VCC.
10.2.2.1 Testing
After the selection of proper component values, the oscillator circuit should be tested, using these components,
to ensure that the oscillator circuit shows required performance over the recommended operating conditions.
• Without a crystal, the oscillator circuit should not oscillate. To check this, the crystal can be replaced by its
equivalent parallel-resonant resistance.
• When the power-supply voltage drops, the closed-loop gain of the oscillator circuit reduces. Ensure that the
circuit oscillates at the appropriate frequency at the lowest VCC and highest VCC.
• Ensure that the duty cycle, start-up time, and frequency drift over time is within the system requirements.
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Typical Application (continued)
10.2.3 Application Curves
10.2.3.1 LVC1404 in 25-MHz Crystal-Oscillator Circuit
C1 ≈ C2 = 30 pF
XC2 = 200 Ω (capacitive reactance at resonance frequency, that is, 25 MHz)
VCC = 3.3 V
(1)
(2)
(3)
3.5
Output Voltage − V
3
2.5
2
1.5
1
RS = 10 kW
0.5
RS = 2 kW
RS = 240 W
RS = 0
0
−0.5
0
20
40
Time − ns
60
80
Figure 5. Effect of RS on Oscillator Waveform (Frequency = 25 MHz)
Table 3. Effect of RS on Duty Cycle and ICC
(Frequency = 25 MHz)
14
RS
(Ω)
ICC
(mA)
Positive Duty Cycle
(%)
0
22.2
43
240
11.1
45.9
2k
7.3
47.3
10 k
8.6
46.7
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10.2.3.2 LVC1404 in 10-MHz Crystal-Oscillator Circuit
C1 ≈ C2 = 30 pF
XC2 = 480 Ω (capacitive reactance at resonance frequency, that is, 10 MHz)
VCC = 3.3 V
(4)
(5)
(6)
Output Voltage − V
3.5
3
2.5
2
1.5
1
0.5
0
0
50
100
Time − ns
150
200
RS = 10 kW
RS = 3 kW
RS = 450 W
Figure 6. Effect of RS on Oscillator Waveform (Frequency = 10 MHz)
Table 4. Effect of RS on Duty Cycle and ICC
(Frequency = 10 MHz)
RS
(Ω)
ICC
(mA)
Positive Duty Cycle
(%)
450
6.9
40
3k
8.4
47.6
10 k
15.1
43.9
10.2.3.3 LVC1404 in 2-MHz Crystal-Oscillator Circuit
C1 ≈ C2 = 30 pF
XC2 = 2.4 kΩ (capacitive reactance at resonance frequency, that is, 2 MHz)
VCC = 3.3 V
(7)
(8)
(9)
3.5
Output Voltage − V
3
2.5
2
1.5
1
0.5
0
0
200
400
600
Time − ns
800
RS = 10 kW
RS = 2 kW
RS = 240 W
Figure 7. Effect of RS on Oscillator Waveform (Frequency = 2 MHz)
Table 5. Effect of RS on Duty Cycle and ICC
(Frequency = 2 MHz)
RS
(Ω)
ICC
(mA)
Positive Duty Cycle
(%)
240
11.1
45.9
2k
7.3
47.3
10 k
8.6
46.7
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10.2.3.4 LVC1404 in 100-kHz Crystal-Oscillator Circuit
C1 ≈ C2 = 30 pF
XC2 = 48 kΩ (capacitive reactance at resonance frequency, that is, 100 kHz)
VCC = 3.3 V
(10)
(11)
(12)
3.5
Output Voltage − V
3
2.5
2
1.5
1
RS = 220 kW
RS = 100 kW
RS = 50 kW
0.5
0
0
5
10
Time − ms
15
20
Figure 8. Effect of RS on Oscillator Waveform (Frequency = 100 kHz)
Table 6. Effect of RS on Duty Cycle and ICC
(Frequency = 100 kHz)
16
RS
(Ω)
ICC
(mA)
Positive Duty Cycle
(%)
50 k
9
46.4
100 k
9.5
46.1
220 k
13.7
44.3
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11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 9 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 9. Layout Diagram
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13 Device and Documentation Support
13.1 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
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29-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC1404DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CA4
(R, Z)
SN74LVC1404DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CA4J, CA4R)
SN74LVC1404YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
44N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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