SN74LVC161284DGGR

     
 SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005 D 1.4-kΩ Pullup Resistors Integrated on All D D D D Open-Drain Outputs Eliminate the Need for Discrete Resistors ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Designed for the IEEE Std 1284-I (Level 1 Type) and IEEE Std 1284-II (Level 2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin-Shrink Small-Outline (DGG) Packages description/ordering information The SN74LVC161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LVC161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line. DGG OR DL PACKAGE (TOP VIEW) HD A9 A10 A11 A12 A13 VCC A1 A2 GND A3 A4 A5 A6 GND A7 A8 VCC PERI LOGIC IN A14 A15 A16 A17 HOST LOGIC OUT 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 DIR Y9 Y10 Y11 Y12 Y13 VCC CABLE B1 B2 GND B3 B4 B5 B6 GND B7 B8 VCC CABLE PERI LOGIC OUT C14 C15 C16 C17 HOST LOGIC IN The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low. The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant. The SN74LVC161284 is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005 Texas Instruments Incorporated   ! " #$%! "  &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%"  %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/  (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
     
 SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005 description/ordering information (continued) ORDERING INFORMATION TSSOP – DGG SSOP – DL 0°C to 70°C ORDERABLE PART NUMBER PACKAGE† TA TSSOP – DGG SSOP – DL Tape and reel SN74LVC161284DGGR Tape SN74LVC161284DL Tape and reel SN74LVC161284DLR Tape and reel 74LVC161284DGGRG4 Tape 74LVC161284DLRE4 Tape and reel 74LVC161284DLRG4 TOP-SIDE MARKING PACKAGE PREVIEW LVC161284 PACKAGE PREVIEW LVC161284 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS 2 DIR HD L L L H H L H H OUTPUT MODE Open drain A9−A13 to Y9−Y13 and PERI LOGIC IN to PERI LOGIC OUT Totem pole B1−B8 to A1−A8 and C14−C17 to A14−A17 Totem pole B1−B8 to A1−A8, A9−A13 to Y9−Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14−C17 to A14−A17 Open drain A1−A8 to B1−B8, A9−A13 to Y9−Y13, and PERI LOGIC IN to PERI LOGIC OUT Totem pole C14−C17 to A14−A17 Totem pole A1−A8 to B1−B8, A9−A13 to Y9−Y13, C14−C17 to A14−A17, and PERI LOGIC IN to PERI LOGIC OUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     
 SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005 logic diagram VCC CABLE DIR HD 42 48 See Note B See Note B 1 See Note A A1−A8 B1−B8 A9−A13 PERI LOGIC IN Y9−Y13 19 30 A14−A17 HOST LOGIC OUT PERI LOGIC OUT C14−C17 24 25 HOST LOGIC IN NOTES: A. The PMOS transistor prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. B. The PMOS transistors prevent backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The PMOS transistor is turned off when the associated driver is in the low state. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
     
 SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range: VCC CABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input and output voltage range, VI and VO: Cable side (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . −2 V to 7 V Peripheral side (see Note 1) . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO: Except PERI LOGIC OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA PERI LOGIC OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Output high sink current, ISK (VO = 5.5 V and VCC CABLE = 3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The ac input voltage pulse duration is limited to 40 ns if the amplitude is greater than −0.5 V. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) VCC CABLE VCC Supply voltage for the cable side, VCC CABLE ≥ VCC Supply voltage A, B, DIR, and HD VIH High-level input voltage Low-level input voltage VI Input voltage VO Open-drain output voltage 3.6 V V 2 0.8 C14−C17 0.8 HOST LOGIC IN 1.6 PERI LOGIC IN 0.8 Peripheral side 0 Cable side 0 HD low 0 A outputs and HOST LOGIC OUT PERI LOGIC OUT UNIT 2 A, B, DIR, and HD B and Y outputs Low-level output current 3 2.6 PERI LOGIC OUT IOL V HOST LOGIC IN A outputs and HOST LOGIC OUT High-level output current 5.5 2.3 HD high, B and Y outputs IOH MAX 3 C14−C17 PERI LOGIC IN VIL MIN V VCC 5.5 V 5.5 V −14 −4 mA −0.5 14 4 mA 84 TA Operating free-air temperature 0 70 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     
 SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005 electrical characteristics over recommended VCC CABLE = 5 V (unless otherwise noted) PARAMETER ∆Vt VOH VOL Input hysteresis VthH − VthL for the HOST LOGIC IN VthH − VthL for the C inputs free-air VCC temperature range, TYP† UNIT MIN 3.3 V 0.4 3.3 V 0.2 3.3 V 0.8 3V 3.3 V‡ 2.23 3V 2.4 3V 2.8 3.15 V 3.3 V‡ 3.1 V IOH = −14 mA HD high, A outputs, and HOST LOGIC OUT IOH = −4 mA IOH = −50 µA PERI LOGIC OUT IOH = −0.5 mA B and Y outputs IOL = 14 mA IOL = 50 µA 3V 0.77 3V 0.2 IOL = 4 mA IOL = 84 mA 3V 04 3V 3.6 Vw 0.8 50 µA 3.6 Vw −3.5 mA 3.6 V ±1 µA A outputs and HOST LOGIC OUT C inputs B outputs VI = VCC VI = GND (pullup resistors) VI = VCC or GND VO = VCC A1−A8 VO = GND (pullup resistors) VO = VCC or GND Open-drain Y outputs VO = GND (pullup resistors) 2.4 V 4.5 Leakage to VCC, B and Y outputs 3.6 V 20 µA −3.5 mA 3.6 V 3.6 Vw ±20 µA −3.5 mA 100 VI or VO = 0 to 7 V 0V VI = VCC, VI = GND (12 × pullup) ICC¶ Ci Control inputs Cio All inputs ZO R pullup Cable side IO = 0 V 3.6 Vw Leakage to GND, B and Y outputs Ioff MAX HD high, B and Y outputs All inputs except the B or C inputs IOZ TEST CONDITIONS VthH − VthL for all inputs except the C inputs and HOST LOGIC IN PERI LOGIC OUT II operating 10 3.6 V 0.8 3.6 V 45 µA A mA VI = VCC or GND VO = VCC or GND 3.3 V 3 4 pF 3.3 V 7 15 pF IOH = −35 mA VO = 0 V (in Hi Z) 3.3 V 45 Cable side † Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25°C. ‡ VCC CABLE = 4.7 V § VCC CABLE = 3.6 V ¶ A maximum current of 170 µA per pin is added to ICC if the pullup resistor pin is above VCC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3.3 V 1.15 Ω 1.65 kΩ 5 
     
 SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) A or B B or A MIN tPLH tPHL Totem pole tslew Totem pole ten Totem pole HD B, Y, and PERI LOGIC OUT tdis Totem pole HD B, Y, and PERI LOGIC OUT tdis DIR tr, tf Open drain tsk(o)‡ UNIT 40 1 40 0.05 0.4 V/ns 1 25 ns 1 25 ns 1 10 ns A 1 50 ns A 1 15 B 1 50 ten−tdis DIR MAX 1 Cable-side outputs ten TYP† A B or Y A or B B or A 2.5 ns ns 120 ns 10 ns † Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25°C. ‡ Skew is measured at 1/2 (VOH + VOL) for signals switching in the same direction. operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS Outputs enabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CL = 0, f = 10 MHz TYP 45 UNIT pF 
     
 SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005 PARAMETER MEASUREMENT INFORMATION VCC tw CL = 50 pF (see Note A) 62 Ω TP1 Input (see Note B) 1.4 V 0V tPLH Sink Load From B or Y Output Under Test 2.7 V 1.4 V tPHL tPHL Output (see Note B) tPLH VOH VOH − 1.4 V VOL VOL + 1.4 V Source Load CL = 50 pF (see Note A) 62 Ω VOLTAGE WAVEFORMS MEASURED AT TP1 PROPAGATION DELAY TIMES (A to B) SLEW RATE A-TO-B OR A-TO-Y LOAD (Totem Pole) VCC Input (see Note C) TP1 From B or Y Output 2.7 V 1.4 V 1.4 V 0V 500 Ω CL = 50 pF (see Note A) Output (see Note C) 2V VOH 2V 0.8 V 0.8 V tr VOL tf VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE A-TO-B LOAD OR A-TO-Y LOAD (Open Drain) NOTES: A. CL includes probe and jig capacitance. B. Input rise and fall times are 3 ns, 150 ns < pulse duration < 10 µs for both low-to-high and high-to-low transitions. Slew rate is measured between 0.4 V and 0.9 V for the rising edge and between 2.4 V and 1.9 V for the falling edge. C. Input rise and fall times are 3 ns. Rise and fall times (open drain) < 120 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
     
 SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test VCC × 2 V Open S1 GND CL = 50 pF (see Note A) 500 Ω LOAD CIRCUIT Input (see Note B) 1.4 V 0V tPLH tPHL 2.7 V 1.4 V 1.4 V 0V tPLZ tPZL Output Waveform 1 S1 at VCC × 2 V (see Note C) 3V 1.4 V VOL + 0.3 V VOL tPHZ tPZH VOH 50% VCC Output S1 Open VCC × 2 V GND Output Control 2.7 V 1.4 V TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 50% VCC VOL Output Waveform 2 S1 at GND (see Note C) VOH − 0.3 V 1.4 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B to A) B-TO-A LOAD (Totem Pole) VCC CL = 50 pF (see Note A) 500 Ω TP1 From B or Y Output Under Test tw 2.7 V Input (see Note D) Sink Load 1.4 V 1.4 V 0V tPHL tPLH tPLH tPHL Source Load Output 500 Ω VOL + 1.4 V CL = 50 pF (see Note A) VOH VOH − 1.4 V VOL VOLTAGE WAVEFORMS MEASURED AT TP1 PROPAGATION DELAY TIMES (A to B) A-TO-B LOAD OR A-TO-Y LOAD (Totem Pole) NOTES: A. CL includes probe and jig capacitance. B. Input rise and fall times are 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. Input rise and fall times are 3 ns. Pulse duration is 150 ns < tw < 10 µs. E. The outputs are measured one at a time, with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVC161284DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LVC161284 Samples SN74LVC161284DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LVC161284 Samples SN74LVC161284DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LVC161284 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of