SN74LVC1G07QDCKRQ1

Product Folder Order Now Technical Documents Support & Community Tools & Software SN74LVC1G07-Q1 SCES826B – MARCH 2011 – REVISED OCTOBER 2019 SN74LVC1G07-Q1 Single Buffer/Driver With Open-Drain Output 1 Features 3 Description • • The SN74LVC1G07-Q1 is a single channel opendrain buffer/driver qualified for automotive applications. This is designed for 1.65-V to 5.5-V VCC operation. 1 • • • • • • Qualified for automotive applications AEC-Q100 Qualified with the following results: – Device temperature grade 1: –40°C to +125°C ambient operating temperature – 2000-V Device human-body model (HBM) ESD classification level 2 – 1000-V Device charged-device model (CDM) ESD classification level C5 Supports 5-V VCC operation Input and open-drain output accept Voltages up to 5.5 V Max tpd of 5.7 ns at 3.3 V Low power consumption, 10-μA max ICC ±24-mA Output drive at 3.3 V Ioff Supports partial-power-down mode Operation 2 Applications • • • • • • • • • • • • • • • • • • • • • • • • Automotive infotainment Automotive ADAS camera and fusion Automotive body control module AV receiver Automotive HEV/powertrain Blu-ray player and home theater DVD recorder and player Desktop or notebook PC Digital radio or internet radio player Digital video camera (DVC) Embedded PC GPS: Personal navigation device Mobile internet device Network projector front end Portable media player Pro Audio Mixer Smoke detector Solid state drive (SSD): enterprise High-definition (HDTV) Tablet: enterprise Audio dock: portable DLP front projection system DVR and DVS Digital picture frame (DPF) Digital still camera The output of the SN74LVC1G07-Q1 device is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or activehigh wired-AND functions. The maximum sink current is 32 mA. This device is fully specified for partial-power-down applications using Ioff.The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Device Information(1) PART NUMBER SN74LVC1G07-Q1 PACKAGE (PINS) BODY SIZE (NOM) SOT-23 (5) 2.90 mm × 1.60 mm SC70 (5) 2.00 mm × 1.25 mm SON (6) 1.45 mm × 1.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) 2 A 4 Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC1G07-Q1 SCES826B – MARCH 2011 – REVISED OCTOBER 2019 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 3 3 4 4 5 5 5 5 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics ......................................... Operating Characteristics.......................................... Typical Characteristics .............................................. 7 Parameter Measurement Information (Open Drain)....................................................................... 6 8 Detailed Description .............................................. 7 7.1 PMI............................................................................ 6 8.1 8.2 8.3 8.4 9 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 7 7 7 7 Application and Implementation .......................... 8 9.1 Application Information.............................................. 8 9.2 Typical Application .................................................... 8 10 Power Supply Recommendations ....................... 9 11 Layout..................................................................... 9 11.1 Layout Guidelines ................................................... 9 11.2 Layout Example ...................................................... 9 12 Device and Documentation Support ................. 10 12.1 12.2 12.3 12.4 12.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 10 10 10 10 10 13 Mechanical, Packaging, and Orderable Information ........................................................... 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2017) to Revision B Page • Added DRY package option to Device Information table ...................................................................................................... 1 • Added DRY package as Product Preview device option to Pin Configuration and Functions .............................................. 3 • Added DRY package to Thermal Information table................................................................................................................ 4 Changes from Original (March 2011) to Revision A Page • Added Applications, Device Information table, ESD Ratings table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ............................................................................................................................................................... 1 • Changed RθJA value for DBV (SOT-23) package from: 206 to: 269.3 ................................................................................... 4 2 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC1G07-Q1 SN74LVC1G07-Q1 www.ti.com SCES826B – MARCH 2011 – REVISED OCTOBER 2019 5 Pin Configuration and Functions DBV or DCK Package 5-Pin SOT-23 or SC70 Top View N.C. 1 A 5 DRY Package 6-Pin SON Transparent Top View N.C. 1 6 A 2 5 N.C. GND 3 4 Y VCC VCC 2 N.C. – No internal connection GND 3 4 See mechanical drawings for dimensions. Y Pin Functions PIN NAME DBV, DCK DRY N.C. 1 1, 5 DESCRIPTION Not connected A 2 2 Input GND 3 3 Ground Y 4 4 Output VCC 5 6 Power Pin 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX Supply voltage –0.5 6.5 UNIT V (2) VI Input voltage –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) (3) –0.5 6.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA 150 °C 150 °C Continuous current through VCC or GND TJ Operating junction temperature Tstg Storage temperature (1) (2) (3) –65 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) Charged-device model (CDM), per AEC Q100-011 ±2000 ±1000 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC1G07-Q1 3 SN74LVC1G07-Q1 SCES826B – MARCH 2011 – REVISED OCTOBER 2019 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VCC Operating Supply voltage Data retention only 1.65 5.5 1.7 VCC = 3 V to 3.6 V 0.7 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage V V 2 VCC = 4.5 V to 5.5 V VIL UNIT 0.65 × VCC VCC = 2.3 V to 2.7 V High-level input voltage MAX 1.5 VCC = 1.65 V to 1.95 V VIH MIN 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V V 0.3 × VCC VI Input voltage 0 5.5 V VO Output voltage 0 5.5 V IOL Low-level output current 4 VCC = 2.3 V 8 16 VCC = 3 V Input transition rise or fall rate Δt/Δv VCC = 1.65 V VCC = 4.5 V 32 VCC = 1.8 V ±0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V TA (1) mA 24 ns/V 5 Operating free-air temperature –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 6.4 Thermal Information SN74LVC1G07-Q1 THERMAL METRIC (1) DBV (SOT-23) DCK (SC70) DRY (SON) UNIT 5 PINS 5 PINS 6 PINS RθJA Junction-to-ambient thermal resistance 269.3 301.2 439 °C/W RθJC(top) Junction-to-case (top) thermal resistance 175.2 186.5 277 °C/W RθJB Junction-to-board thermal resistance 104.9 111.8 271 °C/W ψJT Junction-to-top characterization parameter 73.4 78.3 84 °C/W ψJB Junction-to-board characterization parameter 104.5 110.6 271 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance – – – °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC1G07-Q1 SN74LVC1G07-Q1 www.ti.com SCES826B – MARCH 2011 – REVISED OCTOBER 2019 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOL = 100 μA VOL 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 16 mA IOL = 32 mA A input V 0.55 4.5 V VI = 5.5 V or GND UNIT 0.4 3V IOL = 24 mA II MIN TYP (1) MAX VCC 0.55 0 to 5.5 V ±5 μA Ioff VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND 3.3 V 4 pF Co VO = VCC or GND 3.3 V 5 pF (1) 0 ±10 μA 1.65 V to 5.5 V 10 μA 3 V to 5.5 V 500 μA All typical values are at VCC = 3.3 V, TA = 25°C. 6.6 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 2.4 9.8 1 7.0 1.5 5.7 1 UNIT 4.9 ns 6.7 Operating Characteristics TA = 25°C Cpd PARAMETER TEST CONDITIONS Power dissipation capacitance f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 3 3 4 6 UNIT pF 6.8 Typical Characteristics 2.5 6 TPD TPD 5 2 TPD - ns TPD - ns 4 1.5 1 3 2 0.5 0 -100 1 0 -50 0 50 Temperature - °C 100 150 0 1 2 D001 Figure 1. TPD Across Temperature at 3.3V Vcc 3 Vcc - V 4 5 6 D002 Figure 2. TPD Across Vcc at 25°C Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC1G07-Q1 5 SN74LVC1G07-Q1 SCES826B – MARCH 2011 – REVISED OCTOBER 2019 www.ti.com 7 Parameter Measurement Information (Open Drain) 7.1 PMI VLOAD S1 RL From Output Under Test Open TEST GND RL CL (see Note A) S1 tPZL (see Notes E and F) VLOAD tPLZ (see Notes E and G) VLOAD tPHZ/tPZH VLOAD LOAD CIRCUIT INPUT VCC VI 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VM tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns VCC VCC 3V VCC VLOAD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC CL RL V∆ 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI VM Input VM th VM VM Data Input 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V Output VM VOL tPHL VM tPLZ VLOAD/2 VM tPZH VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL VOH VM VI Output Control tPHL tPLH VI VOL + V∆ VOL tPHZ Output Waveform 2 S1 at VLOAD (see Note B) VM VLOAD/2 − V∆ VLOAD/2 ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VM. G. tPLZ is measured at VOL + V∆. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit And Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC1G07-Q1 SN74LVC1G07-Q1 www.ti.com SCES826B – MARCH 2011 – REVISED OCTOBER 2019 8 Detailed Description 8.1 Overview The SN74LVC1G07-Q1 device contains one open-drain buffer with a maximum sink current of 32 mA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 8.2 Functional Block Diagram 2 4 Y A Figure 4. Logic Diagram (Positive Logic) 8.3 Feature Description • • • • Wide operating voltage range. – Operates from 1.65 V to 5.5 V. Allows down-voltage translation. Inputs and outputs accept voltages to 5.5 V. Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V. 8.4 Device Functional Modes Table 1 lists the functional modes of SN74LVC1G07-Q1. Table 1. Function Table INPUT A OUTPUT Y L L H Z Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC1G07-Q1 7 SN74LVC1G07-Q1 SCES826B – MARCH 2011 – REVISED OCTOBER 2019 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74LVC1G07-Q1 is a high drive CMOS device that can be used to implement a high output drive buffer, such as an LED application. It can sink 32 mA of current at 4.5 V making it ideal for high drive and wiredOR/AND functions. It is good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant allowing it to translate up/down to VCC. 9.2 Typical Application Basic LED Driver Buffer Function VPU VPU VCC uC or Logic LVC1G07 Wired OR uC or Logic uC or Logic LVC1G07 uC or Logic LVC1G07 Figure 5. Typical Application-SN74LVC1G07-Q1 9.2.1 Design Requirements This device uses CMOS technology and has high-output drive. Care should be taken to avoid bus contention because it may drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads; so, routing and load conditions should be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions – Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table. – Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table. – Inputs are over-voltage tolerant allowing them to go as high as (VI max) in the Recommended Operating Conditions table at any valid VCC. 2. Recommended Output Conditions – Load currents should not exceed (IO max) per output and should not exceed (Continuous current through VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table. 8 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC1G07-Q1 SN74LVC1G07-Q1 www.ti.com SCES826B – MARCH 2011 – REVISED OCTOBER 2019 Typical Application (continued) – Outputs should not be pulled above 5.5 V. 9.2.3 Application Curve 1600 Icc Icc Icc Icc 1400 1200 1.8V 2.5V 3.3V 5V Icc - µA 1000 800 600 400 200 0 0 20 40 Frequency - MHz 60 80 D001 Figure 6. Icc vs Frequency 10 Power Supply Recommendations The power supply can be any voltage between the min and max supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for devices with a single supply. If there are multiple VCC pins then a 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally, they are tied to GND or VCC, whichever is more convenient. 11.2 Layout Example VCC Unused Input Input Output Unused Input Output Input Figure 7. Layout Example Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC1G07-Q1 9 SN74LVC1G07-Q1 SCES826B – MARCH 2011 – REVISED OCTOBER 2019 www.ti.com 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Community Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC1G07-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVC1G07QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CCQO SN74LVC1G07QDCKRQ1 ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 16J SN74LVC1G07QDCKTQ1 ACTIVE SC70 DCK 5 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 16J SN74LVC1G07QDRYRQ1 ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HL (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of