Product
Folder
Sample &
Buy
Technical
Documents
Support &
Community
Tools &
Software
Reference
Design
SN74LVC1G11
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
SN74LVC1G11 Single 3-Input Positive-AND Gate
1 Features
3 Description
•
The SN74LVC1G11 performs the Boolean function
Y = A • B • C or Y = A + B + C in positive logic.
1
•
•
•
•
•
•
•
•
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Maximum tpd of 4.1 ns at 3.3 V
Low Power Consumption, 10-μA Maximum ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode Operation
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AV Receivers
DLP Front Projection System
Digital Picture Frames
Digital Radio
Digital Still Cameras
Digital Video Cameras (DVC)
Embedded PCs
E-Books
Ethernet Switchs
GPS: Personal Navigation Devices
Handset: Smartphones
High-Speed Data Acquisition and Generation
Military: Radar and Sonar
Mobile Internet Devices
Notebook PC and Netbooks
Network-Attached Storage (NAS)
Power Line Communication Modems
Server PSU
STB, DVR, and Streaming Media
Speakers: USB
Tablets: Enterprise
Video Broadcasting and Infrastructure: Scalable
Platform and IP-Based Multi-Format Transcoders
Wireless Headsets, Keyboards, and Mice
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G11DBV
SOT-23 (6)
2.90 mm × 1.60 mm
SN74LVC1G11DCK
SC70 (6)
2.00 mm × 1.25 mm
SN74LVC1G11DRY
SON (6)
1.45 mm × 1.00 mm
SN74LVC1G11DSF
SON (6)
1.00 mm × 1.00 mm
SN74LVC1G11YZP
DSBGA (6)
1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
B
C
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G11
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ..................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions ...................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Switching Characteristics, CL = 15 pF, TA = –40°C to
+85°C ......................................................................... 6
6.7 Switching Characteristics, CL = 30 pF or 50 pF, TA =
–40°C to +85°C.......................................................... 6
6.8 Switching Characteristics, CL = 30 pF or 50 pF, TA =
–40°C to +125°C........................................................ 6
6.9 Operating Characteristics.......................................... 6
6.10 Typical Characteristics ............................................ 7
7
Parameter Measurement Information .................. 8
8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (December 2015) to Revision H
Page
•
Deleted 200-V Machine Model from Features ....................................................................................................................... 1
•
Changed pinout images to improve clarity of pin names and pin numbers ........................................................................... 3
•
Added DSBGA pin numbers to Pin Functions table .............................................................................................................. 3
•
Added Operating free-air temperature, TA for BGA package ................................................................................................. 5
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 14
Changes from Revision F (December2013) to Revision G
•
Page
Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
Changes from Revision E (December 2011) to Revision F
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Updated operating temperature range ................................................................................................................................... 4
Changes from Revision D (January 2007) to Revision E
•
2
Page
Added DRY and DSF packages to data sheet ...................................................................................................................... 1
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
SN74LVC1G11
www.ti.com
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
DCK Package
6-Pin SC70
Top View
A
1
6
C
GND
2
5
VCC
B
3
4
Y
A
1
6
C
GND
2
5
VCC
B
3
4
Y
Not to scale
Not to scale
YZP Package
6-Pin DSBGA
Bottom View
C
1
2
B
Y
GND
B
DRY Package
6-Pin SON
Top View
A
1
6
C
GND
2
5
VCC
B
3
4
Y
VCC
Not to scale
A
A
C
DSF Package
6-Pin SON
Top View
Not to scale
A
1
6
C
GND
2
5
VCC
B
3
4
Y
Not to scale
See mechanical drawings for dimensions.
Pin Functions
PIN
I/O
DESCRIPTION
SOT-23, SC70,
SON, SON
DSBGA
A
1
A1
I
A Input
B
3
C1
I
B Input
C
6
A2
I
C Input
GND
2
B1
—
Ground
VCC
5
B2
—
Power Supply
Y
4
C2
O
Y Output
NAME
SPACE
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
3
SN74LVC1G11
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See note (1).
VCC
Supply voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MIN
MAX
1.65
5.5
1.5
Low-level input voltage
VI
Input voltage
VO
Output voltage
1.7
High-level output current
0.7 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
4
0.3 × VCC
5.5
V
0
VCC
V
–4
VCC = 2.3 V
–8
VCC = 3 V
V
0
VCC = 1.65 V
VCC = 4.5 V
(1)
V
2
VCC = 4.5 V to 5.5 V
IOH
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
–16
mA
–24
–32
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
SN74LVC1G11
www.ti.com
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
Recommended Operating Conditions (continued)
See note(1).
MIN
MAX
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
Δt/Δv
8
16
VCC = 3 V
Input transition rise or fall rate
Operating free-air temperature
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
UNIT
ns/V
10
BGA package
–40
85
All other packages
–40
125
°C
6.4 Thermal Information
SN74LVC1G11
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
DRY (SON)
YZP (DSBGA)
DSF (SON)
6 PINS
6 PINS
6 PINS
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
195.9
260.1
424.6
105.8
413.7
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
177.4
98.1
309
1.6
226.6
°C/W
RθJB
Junction-to-board thermal resistance
51.7
63.1
292
10.8
317
°C/W
ψJT
Junction-to-top characterization parameter
61.3
2.2
135.4
3.1
37.4
°C/W
ψJB
Junction-to-board characterization parameter
51.3
62.4
292
10.8
317
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
—
—
—
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VOH
VCC
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
IOH = –32 mA
4.5 V
IOL = 100 μA
3.8
0.1
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
0.4
3V
IOL = 32 mA
All inputs
2.3
1.65 V to 5.5 V
IOL = 16 mA
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
IO = 0
V
0.55
4.5 V
VI = 5.5 V or GND
UNIT
V
IOL = 4 mA
IOL = 24 mA
II
MAX
2.4
3V
IOH = –24 mA
TYP
VCC – 0.1
IOH = –4 mA
IOH = –16 mA
VOL
MIN
0.55
0 to 5.5 V
±5
μA
0
±10
μA
1.65 V to 5.5 V
10
μA
3 V to 5.5 V
500
μA
3.3 V
3.5
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
pF
5
SN74LVC1G11
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
www.ti.com
6.6 Switching Characteristics, CL = 15 pF, TA = –40°C to +85°C
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 2)
PARAMETER
tpd
FROM
(INPUT)
A, B, or C
TO
(OUTPUT)
Y
VCC
MIN
MAX
VCC = 1.8 V ± 0.15 V
2.6
15.2
VCC = 2.5 V ± 0.2 V
1.6
5.6
VCC = 3.3 V ± 0.3 V
1.2
4.1
1
3.1
VCC = 5 V ± 0.5 V
UNIT
ns
6.7 Switching Characteristics, CL = 30 pF or 50 pF, TA = –40°C to +85°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A, B, or C
Y
VCC
MIN
MAX
VCC = 1.8 V ± 0.15 V
2.9
17.2
VCC = 2.5 V ± 0.2 V
1.4
6.2
VCC = 3.3 V ± 0.3 V
1.3
4.9
1
3.5
VCC = 5 V ± 0.5 V
UNIT
ns
6.8 Switching Characteristics, CL = 30 pF or 50 pF, TA = –40°C to +125°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A, B, or C
Y
VCC
MIN
VCC = 1.8 V ± 0.15 V
2.9
20
VCC = 2.5 V ± 0.2 V
1.4
7.8
VCC = 3.3 V ± 0.3 V
1.3
6.2
1
4.6
VCC = 5 V ± 0.5 V
MAX
UNIT
ns
6.9 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
Submit Documentation Feedback
VCC
TYP
VCC = 1.8 V
18
VCC = 2.5 V
19
VCC = 3.3 V
20
VCC = 5 V
23
UNIT
pF
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
SN74LVC1G11
www.ti.com
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
6.10 Typical Characteristics
60
40
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
I OH – mA
20
0
–20
–40
–60
–80
–100
–1
–0.5 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOH – V
Figure 1. Output Current Drive
vs HIGH-level Output Voltage
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
7
SN74LVC1G11
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
www.ti.com
7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
SN74LVC1G11
www.ti.com
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
9
SN74LVC1G11
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
www.ti.com
8 Detailed Description
8.1 Overview
This 3-input AND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G11 device features a three-input AND gate. The output state is determined by eight patterns of
3-bit input. All inputs can be connected to VCC or GND.
This device is fully-specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
A
B
C
Y
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
The SN74LVC1G11 device has a wide operating VCC range of 1.65 V to 5.5 V, which allows use in a broad
range of systems. The 5.5-V I/Os allow down translation and also allow voltages at the inputs when VCC = 0 V.
8.4 Device Functional Modes
Table 1 lists the functional modes of SN74LVC1G11.
Table 1. Function Table
INPUTS
10
A
B
C
OUTPUT
Y
H
H
H
H
L
X
X
L
X
L
X
L
X
X
L
L
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
SN74LVC1G11
www.ti.com
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Validate and test
the design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G11 device offers logical AND configuration for many design applications. This example
describes basic power sequencing using the AND gate configuration. Power sequencing is often used in
applications that require a processor or other delicate device with specific voltage timing requirements in order to
protect the device from malfunctioning. In the application below, the power-good signals from the supplies tell the
MCU to continue an operation.
9.2 Typical Application
Vcc 3.3v
0.1 F
Sup ply 1
Sup ply2
MCU
Sup ply 3
Figure 5. Typical Application Diagram
9.2.1 Design Requirements
•
•
•
Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 V at any valid VCC.
Recommended output conditions:
– Load currents must not exceed ±50 mA.
Frequency selection criterion:
– Figure 6 illustrates the effects of frequency on output current.
– Added trace resistance and capacitance can reduce maximum frequency capability. Follow the layout
practices listed in the Layout section.
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
11
SN74LVC1G11
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
www.ti.com
Typical Application (continued)
9.2.2 Detailed Design Procedure
The SN74LVC1G11 device uses CMOS technology and has balanced output drive. Avoid bus contentions that
can drive currents that can exceed maximum limits.
The SN74LVC1G11 allows for performing the logical AND function with digital signals. Maintain input signals as
close as possible to either 0 V or VCC for optimal operation.
9.2.3 Application Curve
5
Signal (V)
4
3
2
Vin
1
Vout
0
0
1
2
3
4
5
6
7
8
9
Time (ns)
10
C001
VCC = 5 V
Figure 6. Simulated Input-to-Output Voltage Response Showing Propagation Delay
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions table.
To prevent power disturbance, ensure good bypass capacitance for each VCC terminal. For devices with a singlesupply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual
supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. Place the bypass capacitor as close to the power
terminal as possible for best results.
12
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
SN74LVC1G11
www.ti.com
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs must never float.
In many cases, functions (or parts of functions) of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or when only 3 of the 4 buffer gates are used. Such input pins must
not be left unconnected, because the undefined voltages at the outside connections result in undefined
operational states. Figure 7 specifies the rules that must be observed under all circumstances. All unused inputs
of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
must be applied to any particular unused input depends on the function of the device. Generally they are tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output section of the
part when asserted, which does not disable the input section of the I/Os. Therefore, the I/Os cannot float when
disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagrams
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
13
SN74LVC1G11
SCES487H – SEPTEMBER 2003 – REVISED NOVEMBER 2016
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC1G11DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C115, C11F, C11K,
C11R)
SN74LVC1G11DBVRE4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C11F
SN74LVC1G11DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C11F
SN74LVC1G11DCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C35, C3F, C3J, C3
K, C3R)
SN74LVC1G11DCKRE4
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C35
SN74LVC1G11DCKRG4
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C35
SN74LVC1G11DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C3
SN74LVC1G11DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C3
SN74LVC1G11YZPR
ACTIVE
DSBGA
YZP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C3N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
