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SN74LVC1G66
SCES323Q – JUNE 2001 – REVISED MARCH 2017
SN74LVC1G66 Single Bilateral Analog Switch
1 Features
3 Description
•
This single analog switch is designed for 1.65-V to
5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments NanoFree™
Package
1.65-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 0.8 ns at 3.3 V
High On-Off Output Voltage Ratio
High Degree of Linearity
High Speed, Typically 0.5 ns (VCC = 3 V,
CL = 50 pF)
Low ON-State Resistance, Typically ≉5.5 Ω (VCC
= 4.5 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
•
•
The SN74LVC1G66 device can handle analog and
digital signals. The device permits bidirectional
transmission of signals with amplitudes of up to 5.5 V
(peak).
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G66DBV
SOT-23 (5)
2.90 mm × 1.60 mm
SN74LVC1G66DCK
SC70 (5)
2.00 mm × 1.25 mm
SN74LVC1G66DRL
SOT (5)
1.60 mm × 1.20 mm
SN74LVC1G66DRY
SON (6)
1.45 mm × 1.00 mm
SN74LVC1G66YZP
DSBGA (5)
1.39 mm × 0.89 mm
SN74LVC1G66DSF
SON (6)
1.00 mm x 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Wireless Devices
Audio and Video Signal Routing
Portable Computing
Wearable Devices
Signal Gating, Chopping, Modulation or
Demodulation (Modem)
Signal Multiplexing for Analog-to-Digital and
Digital-to-Analog Conversion Systems
Logic Diagram (Positive Logic)
1
A
2
B
4
C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G66
SCES323Q – JUNE 2001 – REVISED MARCH 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5
5
5
6
6
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Analog Switch Characteristics ..................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
13
13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (March 2016) to Revision Q
•
Page
Changed the YZP package pin out graphic............................................................................................................................ 4
Changes from Revision O (March 2015) to Revision P
Page
•
Added Junction temperature spec to Absolute Maximum Ratings table................................................................................ 5
•
Added "Control" to "Input transition rise and fall time" in Recommended Operating Conditions table .................................. 5
Changes from Revision N (December 2012) to Revision O
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
•
Removed Ordering Information table ..................................................................................................................................... 1
•
Added Device Information table ............................................................................................................................................. 1
Changes from Revision M (January 2012) to Revision N
•
Added jumbo reel to Ordering Information table .................................................................................................................... 1
Changes from Revision L (January 2007) to Revision M
•
2
Page
Page
Added DSF and DRY package to pin out graphic.................................................................................................................. 3
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SCES323Q – JUNE 2001 – REVISED MARCH 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
(Top View)
A
1
B
2
GND
5
3
4
DRL Package
5-Pin SOT
(Top View)
VCC
1
B
2
GND
3
5
4
1
B
2
GND
3
5
VCC
4
C
C
DSF Package
6-Pin X2SON
(Top View)
DCK Package
5-Pin SC70
(Top View)
A
A
A
1
6
VCC
B
2
5
NC
GND
3
4
C
VCC
C
DRY Package
6-Pin USON
(Top View)
A
B
GND
1
6
2
5
3
4
VCC
NC
C
Pin Functions
PIN
SOT NO.
USON,
X2SON
NO.
I/O
A
1
1
I/O
Bidirectional signal to be switched
B
2
2
I/O
Bidirectional signal to be switched
C
4
4
I
GND
3
3
—
Ground pin
NC
—
5
—
Do not connect
VCC
5
6
—
Power pin
NAME
DESCRIPTION
Controls the switch (L = OFF, H = ON)
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YZP Package
5-Pin DSBGA
(Bottom View)
1
2
C
GND
C
B
B
A
A
VCC
Pin Functions
PIN
NAME
DSBGA NO.
I/O
DESCRIPTION
A
A1
I/O
Bidirectional signal to be switched
B
B1
I/O
Bidirectional signal to be switched
C
C2
I
GND
C1
—
Ground pin
VCC
A2
—
Power pin
4
Controls the switch (L = OFF, H = ON)
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage (2)
–0.5
6.5
V
(2) (3)
–0.5
6.5
V
–0.5
VCC + 0.5
V
VI
Input voltage
VI/O
Switch I/O voltage (2) (3) (4)
IIK
Control input clamp current
VI < 0
–50
mA
IIOK
I/O port diode current
VI/O < 0 or VI/O > VCC
±50
mA
IT
ON-state switch current
VI/O < 0 to VCC
±50
mA
±100
mA
150
°C
150
°C
Continuous current through VCC or GND
Tstg
Storage Temperature
Tj
Junction Temperature
(1)
(2)
(3)
(4)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
+2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
+1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCC
Supply voltage
VI/O
I/O port voltage.
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage, control input
VI
Low-level input voltage, control input
5.5
V
0
VCC
V
VCC × 0.65
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
Δt/Δv Control input transition rise and fall time
VCC × 0.35
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
0
20
VCC = 2.3 V to 2.7 V
20
VCC = 3 V to 3.6 V
10
(1)
Operating free-air temperature
V
5.5
VCC = 1.65 V to 1.95 V
VCC = 4.5 V to 5.5 V
TA
V
VCC = 2.3 V to 2.7 V
Control input voltage
UNIT
1.65
VCC = 1.65 V to 1.95 V
VIL
MAX
V
ns/V
10
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74LVC1G66
THERMAL METRIC
RθJA
Junction-to-ambient thermal resistance
DBV
(SOT-23)
DCK
(SC70)
DRL (SOT)
DRY
(USON)
DSF
(X2SON)
YZP
(DSBGA)
5 PINS
5 PINS
5 PINS
6 PINS
6 PINS
5 PINS
206
252
142
—
—
132
UNIT
°C/W
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
ron
TEST CONDITIONS
ON-state switch resistance
VI = VCC or GND,
VC = VIH
(see Figure 2 and
Figure 1)
VCC
MIN TYP (1)
MAX
IS = 4 mA
1.65 V
12
30
IS = 8 mA
2.3 V
9
20
IS = 24 mA
3V
7.5
15
IS = 32 mA
4.5 V
5.5
10
IS = 4 mA
1.65 V
74.5
120
IS = 8 mA
2.3 V
20
30
IS = 24 mA
3V
11.5
20
IS = 32 mA
4.5 V
7.5
15
UNIT
Ω
Peak on resistance
VI = VCC or GND,
VC = VIH
(see Figure 2 and
Figure 1)
IS(off)
OFF-state switch leakage current
VI = VCC and VO = GND or
VI = GND and VO = VCC,
VC = VIL (see Figure 3)
IS(on)
ON-state switch leakage current
VI = VCC or GND, VC = VIH,
VO = Open
TA = 25°C
(see Figure 4)
5.5 V
II
Control input current
VC = VCC or GND
5.5 V
ICC
Supply current
VC = VCC or GND
ΔICC
Supply current change
VC = VCC – 0.6 V
Cic
Control input capacitance
5V
2
pF
Cio(off)
Switch input and output capacitance
5V
6
pF
Cio(on)
Switch input and output capacitance
5V
13
pF
ron(p)
(1)
Ω
±1
5.5 V
TA = 25°C
±0.1
μA
±1
TA = 25°C
±0.1
±1
±0.1
10
5.5 V
TA = 25°C
1
5.5 V
500
μA
μA
μA
μA
TA = 25°C
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
PARAMETER
tpd (1)
(2)
(3)
6
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
MIN
MIN
MIN
MAX
2
MAX
1.2
VCC = 5 V
± 0.5 V
UNIT
MAX
MIN MAX
0.8
0.6
ns
A or B
B or A
(2)
C
A or B
2.5
12
1.9
6.5
1.8
5
1.5
4.2
ns
tdis (3)
C
A or B
2.2
10
1.4
6.9
2
6.5
1.4
5
ns
ten
(1)
FROM
(INPUT)
tPLH and tPHL are the same as tpd. The propagation delay is the calculated RC time constant of the typical ON-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
tPZL and tPZH are the same as ten.
tPLZ and tPHZ are the same as tdis.
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6.7 Analog Switch Characteristics
TA = 25°C
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST
CONDITIONS
VCC
CL = 50 pF, RL = 600 Ω,
fin = sine wave
(see Figure 6)
Frequency response
(switch ON)
(1)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = sine wave
(see Figure 6)
Crosstalk
(control input to signal output)
C
A or B
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (square wave)
(see Figure 7)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 8)
Feedthrough attenuation
(switch OFF)
(2)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 8)
CL = 50 pF, RL = 10 kΩ,
fin = 1 kHz (sine wave)
(see Figure 9)
Sine-wave distortion
A or B
B or A
CL = 50 pF, RL = 10 kΩ,
fin = 10 kHz (sine wave)
(see Figure 9)
(1)
(2)
TYP
1.65 V
35
2.3 V
120
3V
175
4.5 V
195
1.65 V
>300
2.3 V
>300
3V
>300
4.5 V
>300
1.65 V
35
2.3 V
50
3V
70
4.5 V
100
1.65 V
–58
2.3 V
–58
3V
–58
4.5 V
–58
1.65 V
–42
2.3 V
–42
3V
–42
4.5 V
–42
1.65 V
0.1%
2.3 V
0.025%
3V
0.015%
4.5 V
0.01%
1.65 V
0.15%
2.3 V
0.025%
3V
0.015%
4.5 V
0.01%
UNIT
MHz
mV
dB
Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
Adjust fin voltage to obtain 0 dBm at input.
6.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
8
9
9
11
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UNIT
pF
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6.9 Typical Characteristics
TA = 25°C
100
VCC = 1.65 V
r on − Ω
VCC = 2.3 V
VCC = 3.0 V
10
1
0.0
VCC = 4.5 V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN − V
Figure 1. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
8
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7 Parameter Measurement Information
VCC
VCC
B or A
A or B
VI = VCC or GND
VO
C
VC
VIH
(ON)
GND
IS
r on +
V
VI * VO
W
IS
VI − VO
Figure 2. ON-State Resistance Test Circuit
VCC
VCC
VI
B or A
A or B
A
VIL
VO
C
VC
(OFF)
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 3. OFF-State Switch Leakage-Current Test Circuit
VCC
VCC
VI = VCC or GND
A
B or A
A or B
VO
VO = Open
VIH
C
VC
(ON)
GND
Figure 4. ON-State Switch Leakage-Current Test Circuit
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
VCC
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
10
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Parameter Measurement Information (continued)
VCC
VCC
0.1 µF
fin
50 Ω
VIH
B or A
A or B
VO
C
VC
RL
(ON)
GND
CL
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 6. Frequency Response (Switch ON)
VCC
VCC
Rin
600 Ω
VCC/2
A or B
B or A
VO
RL
600 Ω
C
VC
GND
CL
50 pF
VCC/2
50 Ω
Figure 7. Crosstalk (Control Input – Switch Output)
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Parameter Measurement Information (continued)
VCC
VCC
0.1 µF
50 Ω
fin
B or A
A or B
RL
VO
C
VC
VIL
CL
RL
(OFF)
GND
VCC/2
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 8. Feedthrough (Switch OFF)
VCC
VCC
10 µF
fin
600 Ω
VIH
10 µF
B or A
A or B
VO
RL
10 kΩ
C
VC
(ON)
GND
CL
50 pF
VCC/2
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.3 V, VI = 2 VP-P
VCC = 3 V, VI = 2.5 VP-P
VCC = 4.5 V, VI = 4 VP-P
Figure 9. Sine-Wave Distortion
12
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8 Detailed Description
8.1 Overview
This single analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G66 device can handle analog and digital signals. The device permits bidirectional transmission
of signals with amplitudes of up to 5.5 V (peak). Like all analog switches, the SN74LVC1G66 is bidirectional.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
8.2 Functional Block Diagram
1
2
A
B
4
C
Figure 10. Logic Diagram (Positive Logic)
8.3 Feature Description
The TI NanoFree package is one of TI’s smallest packages and allows customers to save board space while the
solder bumps allow for easy testing. The SN74LVC1G66 has a wide VCC range, allowing rail-to-rail operation of
signals anywhere from a 1.8-V system to a 5-V system. In addition, the control input (C Pin) is 5.5-V tolerant,
allowing higher-voltage logic to interface to the switch control system.
8.4 Device Functional Modes
Table 1. Function Table
CONTROL INPUT (C)
SWITCH
L
OFF
H
ON
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SN74LVC1G66
SCES323Q – JUNE 2001 – REVISED MARCH 2017
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G66 can be used in any situation where an SPST switch would be used and a solid-state,
voltage-controlled version is preferred.
9.2 Typical Application
2.5 V
C
or
System Logic
C
VCC
A
To/From
System
B
GND
Figure 11. Typical Application Schematic
9.2.1 Design Requirements
The SN74LVC1G66 allows on and off control of analog and digital signals with a digital control signal. All input
signals should remain between 0 V and VCC for optimal operation.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/Δv in Recommended Operating Conditions.
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
– Inputs and outputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions:
– Load currents should not exceed ±50 mA.
3. Frequency Selection Criterion:
– Maximum frequency tested is 150 MHz.
– Added trace resistance/capacitance can reduce maximum frequency capability; use layout practices as
directed in Layout.
14
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Typical Application (continued)
9.2.3 Application Curve
20
15
ron
85°C
10
25°C
−40°C
5
0
0
1
2
3
VI
Figure 12. ron vs VI, VCC = 2.5 V (SN74LVC1G66)
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and so they will have to
turn corners. Figure 13 shows progressively better techniques of rounding corners. Only the last example
maintains constant trace width and minimizes reflections.
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11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 13. Trace Example
16
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Product Folder Links: SN74LVC1G66
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SCES323Q – JUNE 2001 – REVISED MARCH 2017
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
• Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC1G66DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(C665, C66J, C66R,
C66T)
SN74LVC1G66DBVRE4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(C665, C66J, C66R,
C66T)
SN74LVC1G66DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(C665, C66J, C66R,
C66T)
SN74LVC1G66DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(C665, C66J, C66R)
SN74LVC1G66DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(C665, C66J, C66R)
SN74LVC1G66DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(C65, C6F, C6J, C6
K, C6O, C6R, C
6T)
SN74LVC1G66DCKRE4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(C65, C6F, C6J, C6
K, C6O, C6R, C
6T)
SN74LVC1G66DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(C65, C6F, C6J, C6
K, C6O, C6R, C
6T)
SN74LVC1G66DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(C65, C6J, C6R, C6
T)
SN74LVC1G66DRLR
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(C67, C6R)
SN74LVC1G66DRLRG4
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(C67, C6R)
SN74LVC1G66DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C6
SN74LVC1G66DSF2
ACTIVE
SON
DSF
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C6
SN74LVC1G66DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C6
SN74LVC1G66YZPR
ACTIVE
DSBGA
YZP
5
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C6N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2022
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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