SN74LVCC3245APWT

SN74LVCC3245A SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 SN74LVCC3245A Octal Bus Transceiver With Adjustable Output Voltage and 3-State Outputs 1 Features 3 Description • • The SN74LVCC3245A device is 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to track VCCB, which accepts voltages from 3 V to 5.5 V, and the A port is designed to track VCCA, which operates at 2.3 V to 3.6 V. This allows for translation from a 3.3-V to a 5-V system environment and vice versa, from a 2.5-V to a 3.3-V system environment and vice versa. • • • Bidirectional voltage translator 2.3 V to 3.6 V on A port and 3 V to 5.5 V on B port Control inputs VIH and VIL levels are referenced to VCCA voltage Latch-up performance exceeds 250 mA per JESD 17 ESD protection exceeds JESD 22 – 2000-V Human Body Model (A114-A) – 1000-V Charged-Device Model (C101) Package Information(1) PART NUMBER PACKAGE 2 Applications • • • • Level translation USB Interfacing Analog and digital applications SN74LVCC3245A (1) BODY SIZE (NOM) DB (SSOP, 24) 8.65 mm × 3.90 mm DW (SOIC, 24) 15.40 mm × 7.50 mm DBQ (SSOP, 24) 8.20 mm × 5.30 mm NS (SO, 24) 15.00 mm × 5.30 mm PW (TSSOP, 24) 7.80 mm × 4.40 mm For all available packages, see the orderable addendum at the end of the data sheet. 2 DIR 22 OE 3 A1 21 B1 To Seven Other Channels Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions ........................4 6.4 Thermal Information....................................................6 6.5 Electrical Characteristics.............................................6 6.6 Switching Characteristics............................................7 6.7 Operating Characteristics........................................... 8 6.8 Typical Characteristics................................................ 9 7 Parameter Measurement Information.......................... 10 7.1 A Port (VCCA = 2.5 V ± 0.2 V and VCCB = 3.3 V ± 0.3 V)...........................................................................10 7.2 B Port (VCCA = 2.5 V ± 0.2 V and VCCB = 3.3 V ± 0.3 V)........................................................................... 11 7.3 B Port (VCCA = 3.6 V and VCCB = 5.5 V)................... 12 7.4 A and B Port (VCCA and VCCB = 3.6 V)..................... 13 8 Detailed Description......................................................14 8.1 Overview................................................................... 14 8.2 Functional Block Diagram......................................... 14 8.3 Feature Description...................................................14 8.4 Device Functional Modes..........................................14 9 Power Supply Recommendations................................16 10 Layout...........................................................................17 10.1 Layout Guidelines................................................... 17 10.2 Layout Example...................................................... 17 10.3 Power-Up Considerations....................................... 17 11 Device and Documentation Support..........................18 11.1 Documentation Support.......................................... 18 11.2 Receiving Notification of Documentation Updates.. 18 11.3 Support Resources................................................. 18 11.4 Trademarks............................................................. 18 11.5 Electrostatic Discharge Caution.............................. 18 11.6 Glossary.................................................................. 18 12 Mechanical, Packaging, and Orderable Information.................................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision P (December 2015) to Revision Q (December 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Added thermal information for DB and PW package.......................................................................................... 6 • Added inclusive terminology............................................................................................................................. 15 Changes from Revision O (March 2005) to Revision P (December 2015) Page • Added Applications section, Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................................................................................................................................................................ 1 • Removed Ordering Information table..................................................................................................................1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 5 Pin Configuration and Functions VCCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCCB NC OE B1 B2 B3 B4 B5 B6 B7 B8 GND NC – No internal connection See Section 12 for dimensions. Figure 5-1. DB, DBQ, DW, NS, or PW Package, 24-Pin SSOP, SOIC, SO, or TSSOP (Top View) Table 5-1. Pin Functions PIN NAME NO. TYPE(1) DESCRIPTION A1 3 I/O A1 port A2 4 I/O A2 port A3 5 I/O A3 port A4 6 I/O A4 port A5 7 I/O A5 port A6 8 I/O A6 port A7 9 I/O A7 port A8 10 I/O A8 port B1 21 I/O B1 port B2 20 I/O B2 port B3 19 I/O B3 port B4 18 I/O B4 port B5 17 I/O B5 port B6 16 I/O B6 port B7 15 I/O B7 port B8 14 I/O B8 port DIR 2 I Dir input GND 12 — Ground — Unconnected 11 13 NC 23 OE 22 I VCCA 1 — A port power VCCB 24 — B port power (1) Output Enable active low I = input, O = output, P = power Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A 3 SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCCA VCCB MIN MAX UNIT –0.5 6 V All A ports(2) –0.5 VCCA + 0.5 All B ports(3) –0.5 VCCB + 0.5 Supply voltage VI Input voltage Except I/O ports(2) –0.5 VCCA + 0.5 All A ports –0.5 VCCA + 0.5 All B ports –0.5 VCCB + 0.5 V VO Output voltage(3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA V Continuous current through VCCA, VCCB, or GND ±100 mA TJ Junction temperature 150 °C RθJA Junction-to-ambient thermal resistance Tstg Storage temperature (1) (2) (3) (4) DW 46 NS 65 –65 °C/W 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This value is limited to 4.6 V maximum. This value is limited to 6 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions VCCA MIN NOM MAX UNIT VCCA Supply voltage 2.3 3.3 3.6 V VCCB Supply voltage 3 5 5.5 V VIHA VIHB 4 VCCB High-level input voltage High-level input voltage 2.3 V 3V 1.7 2.7 V 3V 2 3V 3.6 V 2 3.6 V 5.5 V 2 2.3 V 3V 2 2.7 V 3V 2 3V 3.6 V 2 3.6 V 5.5 V 3.85 Submit Document Feedback V V Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 6.3 Recommended Operating Conditions (continued) VILA VILB VIH Low-level input voltage Low-level input voltage High-level input voltage (control terminals) (referenced to VCCA) VCCA VCCB MIN NOM MAX 2.3 V 3V 0.7 2.7 V 3V 0.8 3V 3.6 V 0.8 3.6 V 5.5 V 0.8 2.3 V 3V 0.8 2.7 V 3V 0.8 3V 3.6 V 0.8 3.6 V 5.5 V 1.65 2.3 V 3V 1.7 2.7 V 3V 2 3V 3.6 V 2 3.6 V 5.5 V 2 2.3 V 3V 0.7 2.7 V 3V 0.8 3V 3.6 V 0.8 3.6 V 5.5 V UNIT V V V VIL Low-level input voltage (control terminals) (referenced to VCCA) VIA Input voltage 0 VCCA V VIB Input voltage 0 VCCB V VOA Output voltage 0 VCCA V VOB Output voltage 0 VCCB V IOHA IOHB IOLA High-level output current High-level output current Low-level output current IOLB Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature V 0.8 2.3 V 3V –8 2.7 V 3V –12 3V 3V –24 2.7 V 4.5 V –24 2.3 V 3V –12 2.7 V 3V –12 3V 3V –24 2.7 V 4.5 V –24 2.3 V 3V 8 2.7 V 3V 12 3V 3V 24 2.7 V 4.5 V 24 2.3 V 3V 12 2.7 V 3V 12 3V 3V 24 2.7 V 4.5 V 24 –40 mA mA mA mA 10 ns/V 85 °C Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A 5 SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 6.4 Thermal Information SN74LVCC3245A THERMAL METRIC(1) (4) DB (SSOP) DBQ (SSOP) PW (TSSOP) 24 PINS 24 PINS 24 PINS UNIT RθJA Junction-to-ambient thermal resistance 90.7 61 100.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.9 44.8 44.7 °C/W RθJB Junction-to-board thermal resistance 49.7 34.5 55.8 °C/W ψJT Junction-to-top characterization parameter 18.8 9.5 6.8 °C/W ψJB Junction-to-board characterization parameter 49.3 37.2 55.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 μA IOH = –8 mA IOH = –12 mA VOHA IOH = –24 mA IOH = –100 μA 3 3V 3V 2.9 2.3 V 3V 2 2.7 V 3V 2.2 2.5 3V 3V 2.4 2.8 2.2 2.6 2 2.3 3 3V 3V 2.7 V 4.5 V MAX 2.9 2.4 2.7 V 3V 2.4 2.8 3V 3V 2.2 2.6 2.7 V 4.5 V 3.2 4.2 3V 3V IOL = 8 mA 2.3 V 3V IOL = 12 mA 2.7 V 3V 0.1 0.5 V 0.1 0.6 3V 3V 0.2 0.5 2.7 V 4.5 V 0.2 0.5 IOL = 100 μA 3V 3V 0.1 IOL = 12 mA 2.3 V 3V 0.4 3V 3V 0.2 0.5 2.7 V 4.5 V 0.2 0.5 3.6 V ±0.1 ±1 5.5 V ±0.1 ±1 IOL = 24 mA II Control inputs VI = VCCA or GND IOZ (1) A or B ports VO = VCCA/B or GND, VI = VIL or VIH 3.6 V 3.6 V ±0.5 ±5 A port = VCCA or GND, IO = 0 3.6 V Open 5 50 B port = VCCB or GND, IO = 0 3.6 V 3.6 V 5 50 5.5 V 5 50 A port = VCCA or GND, IO = 0 3.6 V 3.6 V 5 50 5.5 V 8 80 ICCA ICCB B to A A to B 3.6 V Submit Document Feedback UNIT V 3V IOL = 24 mA 6 TYP 3V IOL = 100 μA VOLB MIN 3V IOH = –24 mA VOLA VCCB 2.3 V IOH = –12 mA VOHB VCCA V V μA μA μA μA Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 6.5 Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCCA VCCB A port VI = VCCA – 0.6 V, Other inputs at VCCA or GND, OE at GND and DIR at VCCA TYP MAX 3.6 V 3.6 V 0.35 0.5 OE VI = VCCA – 0.6 V, Other inputs at VCCA or GND, DIR at VCCA 3.6 V 3.6 V 0.35 0.5 DIR VI = VCCA – 0.6 V, Other inputs at VCCA or GND, OE at GND 3.6 V 3.6 V 0.35 0.5 ΔICCB (2) B port VI = VCCB – 2.1 V, Other inputs at VCCB or GND, OE at GND and DIR at GND 3.6 V 5.5 V 1 1.5 Ci Control inputs VI = VCCA or GND Open Open Cio A or B ports VO = VCCA/B or GND 3.3 V 5V ΔICCA (2) (1) (2) TEST CONDITIONS MIN UNIT mA mA 4 pF 18.5 pF For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified voltage levels, rather than 0 V or the associated VCC. 6.6 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1 through Figure 7-4) PARAMETER tPHL tPLH tPHL tPLH tPZL FROM (INPUT) A A B B OE TO (OUTPUT) B B A A A VCCA, VCCB MIN MAX VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 9.4 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 6 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 7.1 VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 9.1 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 5.3 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 7.2 VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 11.2 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 5.8 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 6.4 VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 9.9 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 7 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 7.6 VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 14.5 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 9.2 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 9.7 UNIT ns ns ns ns ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A 7 SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 6.6 Switching Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1 through Figure 7-4) PARAMETER tPZH tPZL tPZH tPLZ tPHZ tPLZ tPHZ FROM (INPUT) TO (OUTPUT) OE A OE B OE B OE A OE A OE B OE B VCCA, VCCB MIN MAX VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 12.9 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 9.5 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 9.5 VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 13 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 8.1 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 9.2 VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 12.8 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 8.4 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 9.9 VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 7.1 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 7 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 6.6 VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 7.3 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 7.8 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 6.9 VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 8.8 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 7.3 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 7.5 VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V 1 8.9 VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V 1 7 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V 1 7.9 UNIT ns ns ns ns ns ns ns 6.7 Operating Characteristics VCCA = 3.3 V, VCCB = 5 V, TA = 25°C PARAMETER Cpd 8 Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled Submit Document Feedback CL = 50, f = 10 MHz TYP 38 4.5 UNIT pF Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 6.8 Typical Characteristics 3 IOH @0.1mA 2.75 VOHA (min) V 2.5 VCCB@ 3V 2.25 IOH @12mA 2 IOH @8mA 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Vcca(V) Figure 6-1. VOHA(min) VS VCCA Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A 9 SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 7 Parameter Measurement Information 7.1 A Port (VCCA = 2.5 V ± 0.2 V and VCCB = 3.3 V ± 0.3 V) 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 Output Control (low-level enabling) VCC VCC/2 VCC/2 0V tPLH VCC/2 VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES C. D. E. F. G. H. VOL + 0.15 V VOL tPHZ tPZH VOH A. B. tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 0V tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES CL includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. The outputs are measured one at a time, with one transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZHare the same as ten. tPLH and tPHL are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 7.2 B Port (VCCA = 2.5 V ± 0.2 V and VCCB = 3.3 V ± 0.3 V) 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 Output Control (low-level enabling) VCC VCC/2 VCC/2 0V tPLH 0V Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 VCC/2 VOL VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES C. D. E. F. G. H. tPLZ VOL + 0.15 V VOL tPHZ tPZH tPHL VOH A. B. VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES CL includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. The outputs are measured one at a time, with one transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPLH and tPHL are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 7-2. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A 11 SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 7.3 B Port (VCCA = 3.6 V and VCCB = 5.5 V) 2 × VCC 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open LOAD CIRCUIT tw VCC B-Port Input 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION VCC 1.5 V Input 1.5 V Output Waveform 1 S1 at 2 × VCC (see Note B) 0V tPHL tPLH B-Port Output 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS A. B. C. D. E. 2.7 V Output Control 1.5 V 1.5 V 0V tPLZ tPZL VCC 50% VCC VOL + 0.3 V VOL tPHZ tPZH Output Waveform 2 S1 at Open (see Note B) 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING CL includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices. Figure 7-3. Load Circuit and Voltage Waveforms 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 7.4 A and B Port (VCCA and VCCB = 3.6 V) 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT tw 2.7 V 1.5 V Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 2.7 V 1.5 V Input 1.5 V Output Waveform 1 S1 at 7 V (see Note B) 0V tPHL tPLH VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS A. B. C. D. E. 2.7 V Output Control 1.5 V 1.5 V 0V tPLZ tPZL 3.5 V 1.5 V VOL tPHZ tPZH Output Waveform 2 S1 at Open (see Note B) VOL + 0.3 V 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING CL includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices. Figure 7-4. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A 13 SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 8 Detailed Description 8.1 Overview The SN74LVCC3245A device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. The control circuitry (DIR, OE) is powered by VCCA. 8.2 Functional Block Diagram 2 DIR 22 OE 3 A1 21 B1 To Seven Other Channels 8.3 Feature Description This device is a bidirectional level translator designed to operate from 2.3 V to 3.6 V on Port A and 3 V to 5.5 V on B port. The control inputs recommended operating specifications are referenced with respect to VCCA Voltage. 8.4 Device Functional Modes Table 8-1 lists the functional modes of the SN74LVCC3245A. Table 8-1. Function Table (Each Transceiver) INPUTS 14 OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The SN74LVCC3245A device is a bidirectional level translator designed to operate from 2.3 V to 3.6 V on Port A and 3 V to 5.5 V on B port and designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. 9.2 Typical Application 3.3 V 5V 0.1
F VCCA VCCB 0.1 F DIR OE A1 Controller B1 : : : : : : : : : : A8 Target B8 GND Figure 9-1. Typical Application 9.2.1 Design Requirements This device can be used as bidirectional level translator depending on the DIR pin. The application describes the level translation of controller with signals at 3.3 V to target operating at 5 V. The OE pin is low and DIR pin is 3.3-V high. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A 15 SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 9.2.2 Detailed Design Procedure Use the procedure that follows for the design: 1. Recommended Input Conditions • Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table. • Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table. • Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating Conditions table at any valid VCC. 2. Absolute Maximum Output Conditions • Load currents should not exceed (IO max) per output and should not exceed total current (continuous current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings table. • All the voltages on A and B ports should not exceed above VCCA or VCCB to prevent the biasing of Electrostatic discharge (ESD) diodes. 9.2.3 Application Curve 3 2.75 VOHB (min) V 2.5 IOH @12mA VCCB@ 3V IOH @12mA 2.25 IOH @24mA 2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VCCA(V) Figure 9-2. VOHB(min) vs VCCA 9 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple VCC pins then 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 10 Layout 10.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more convenient. 10.2 Layout Example VCC Unused Input Input Output Unused Input Output Input Figure 10-1. Layout Example 10.3 Power-Up Considerations TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device terminals. To guard against such power-up problems, take these precautions: 1. 2. 3. 4. Connect ground before any supply voltage is applied. Power up the control side of the device (VCCA for all four of these devices). Tie OE to VCCA with a pullup resistor so that it ramps with VCCA. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus), ramp it with VCCA. Otherwise, keep DIR low. For more information, refer to Voltage-Level-Translation Devices application note. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A 17 SN74LVCC3245A www.ti.com SCAS585Q – NOVEMBER 1996 – REVISED DECEMBER 2022 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation, see the following: • • Texas Instruments, Implications of Slow or Floating CMOS Inputs Texas Instruments, Voltage-Level-Translation Devices 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCC3245A PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVCC3245ADBQR ACTIVE SSOP DBQ 24 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVCC3245A Samples SN74LVCC3245ADBR ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245A Samples SN74LVCC3245ADBRE4 ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245A Samples SN74LVCC3245ADBRG4 ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245A Samples SN74LVCC3245ADW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC3245A Samples SN74LVCC3245ADWE4 ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC3245A Samples SN74LVCC3245ADWG4 ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC3245A Samples SN74LVCC3245ADWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 LVCC3245A Samples SN74LVCC3245ADWRG4 ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC3245A Samples SN74LVCC3245ANSR ACTIVE SO NS 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC3245A Samples SN74LVCC3245APW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245A Samples SN74LVCC3245APWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245A Samples SN74LVCC3245APWRE4 ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245A Samples SN74LVCC3245APWRG4 ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245A Samples SN74LVCC3245APWT ACTIVE TSSOP PW 24 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245A Samples SN74LVCC3245APWTG4 ACTIVE TSSOP PW 24 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of