TB3R1DG4

TB3R1, TB3R2 SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008 QUAD DIFFERENTIAL PECL RECEIVERS Check for Samples: TB3R1, TB3R2 FEATURES 1 • • • • • • • • • • • • • Low-Voltage Functional Replacements for the Agere BRF1A, BRF2A, BRS2A, and BRS2B Pin-Equivalent to General Trade 26LS32 Devices High-Input Impedance Approximately 8 kΩ 3.5-ns Maximum Propagation Delay TB3R1 Provides 50-mV Hysteresis TB3R2 With -125-mV Threshold Offset for Preferred State Output -0.5-V to 5.2-V Common Mode Range Single 3.3 V ±10% Supply Slew Rate Limited (0.5 ns min 80% to 20%) TB3R2 Output Defaults to Logic 1 When Inputs Left Open or Shorted to VCC or GND ESD Protection HBM > 3 kV, CDM > 2 kV Operating Temperature Range: -40°C to 85°C Available SOIC (D) Package The power-down loading characteristics of the receiver input circuit are approximately 8 kΩ relative to the power supplies; hence they do not load the transmission line when the circuit is powered down. The package for these differential line receivers is the 16-pin SOIC (D) package. The enable inputs of this device include internal pullup resistors of approximately 40 kΩ that are connected to VCC to ensure a logical high level input if the inputs are open circuited. PIN ASSIGNMENTS D PACKAGE (TOP VIEW) AI AI AO E1 BO BI BI GND APPLICATIONS • Digital Data or Clock Transmission Over Balanced Lines VCC DI DI DO E2 CO CI CI FUNCTIONAL BLOCK DIAGRAM DESCRIPTION AI These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels. AI The TB3R1 is a pin- and function-compatible replacement for the Agere Systems BRF1A and BRF2A; it includes 3-kV HBM and 2-kV CDM ESD protection. C1 The TB3R2 is a pin- and function-compatible replacement for the Agere Systems BRS2A and BRS2B and incorporates a -125-mV receiver input offset, preferred state output, 3-kV HBM and 2-kV CDM ESD protection. The TB3R2 preferred state feature places the output in the high state when the inputs are open, shorted to ground, or shorted to the power supply. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 AO BI BO BI C1 CO D1 DO D1 E1 E2 Enable Truth Table E1 E2 CONDITION 0 0 Active 1 0 Active 0 1 Disabled 1 1 Active 1 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TB3R1, TB3R2 SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PART NUMBER PART MARKING Package LEAD FIISH STATUS TB3R1D TB3R1 SOIC NiPdAu Production TB3R2D TB3R2 SOIC NiPdAu Production POWER DISSIPATION RATINGS PACKAGE D THERMAL RESISTANCE, JUNCTION-TO-AMBIENT WITH NO AIR FLOW Low-K (1) 763 mW High-K (2) 1190 mW 831 mW 1240 mW Low-K DW (1) (2) POWER RATING TA≤ 25°C CIRCUIT BOARD MODEL (1) High-K (2) DERATING FACTOR(1) TA≥ 25°C POWER RATING TA = 85°C 131.1°C/W 7.6 mW/°C 305 mW 84.1°C/W 11.9 mW/°C 475 mW 120.3°C/W 8.3 mW/°C 332 mW 80.8°C/W 12.4 mW/°C 494 mW In accordance with the low-K thermal metric definitions of EIA/JESD51-3. In accordance with the high-K thermal metric definitions of EIA/JESD51-7. THERMAL CHARACTERISTICs PARAMETER θJB Junction-to-Board Thermal Resistance θJC Junction-to-Case Thermal Resistance PACKAGE VALUE UNIT D 47.5 °C/W DW 53.7 °C/W D 44.2 °C/W DW 47.1 °C/W ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT Supply voltage, VCC 0 V to 6 V Magnitude of differential bus (input) voltage, |VAI - V|, |VBI - V|, |VCI - V|, |VDI - V| ESD All pins ±3 kV Charged-Device Model (3) All pins ±2 kV Continuous power dissipation See Dissipation Rating Table Storage temperature, Tstg (1) (2) (3) 2 6.5 V Human Body Model (2) -65°C to 150°C Stresses beyond those listed under„ absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under„ recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Links: TB3R1 TB3R2 TB3R1, TB3R2 www.ti.com SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008 RECOMMENDED OPERATING CONDITIONS MIN Nom 3 3.3 Supply voltage, VCC MAX UNIT 3.6 V -0.6 (1) 5.3 V Magnitude of differential input voltage, |VAI - V|, |VBI - V|, |VCI - V|, |VDI - V| 0.1 5 V Operating free-air temperature, TA -40 85 °C Bus pin input voltage, VAI, V, VBI, V, VCI, V, VDI, V (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless otherwise noted. DEVICE ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER Supply current (1) ICC (1) TEST CONDITIONS MIN TYP MAX UNIT Outputs disabled 34 mA Outputs enabled 32 mA Current is dc power draw as measured through GND pin and does not include power delivered to load. ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted parameter test conditions min VOL Output low voltage VCC = 3 V, IOL = 8 mA VOH Output high voltage VCC = 3 V, IOH = -400 µA VIL Low level enable input voltage (1) VCC = 3.6 V VIH High level enable input voltage (1) VCC = 3.6 V VIK Enable input clamp voltage VTH+ VCC = 3 V, Positive-going differential input threshold voltage (1), (Vxl - V) x = A, B, C, or D VTH- Negative-going differential input threshold voltage (1), (Vxl - V) x = A, B, C, or D VHYST Differential input threshold voltage hysteresis, (VTH+ - VTH_) TB3R1 IOZL Output off-state current, (High-Z) VCC = 3.6 V IOS Output short circuit current (4) VCC = 3.6 V IIL Enable input low current VCC = 3.6 V, IOZH IIH Enable input high current Enable input reverse current VCC = 3.6 V 0.4 2.4 V V 2 V V -1 (2) V TB3R1 100 mV TB3R2 (3) -50 mV TB3R1 -100 (2) mV TB3R2 (3) -200 (2) mV 50 VO = 0.4 V mV -20 VO = 2.4 V (2) µA 20 µA -100 (2) mA VIN = 0.4 V -400 (2) µA VIN = 2.7 V 20 µA VIN = 3.6 V 100 µA -2 (2) mA 1 mA VCC = 3.6 V, VIN = -1.2 V IIH Differential input high current VCC= 3.6 V, VIN = 5.3 V RO Output resistance (4) unit II = -5 mA Differential input low current (3) max 0.8 IIL (1) (2) typ 20 Ω The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment. This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original Agere data sheet. Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recomended that all unused positive inputs be tied to the positive power supply. No external series resistor is required.) Test must be performed one lead at a time to prevent damage to the device. Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Links: TB3R1 TB3R2 3 TB3R1, TB3R2 SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008 www.ti.com SWITCHING CHARACTERISTICS over operating free-air temperature range unless otherwise noted parameter test conditions tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tPHZ Output disable time, high-level-to-high-impedance output (2) tPLZ Output disable time, low-level-to-high-impedance output (2) tskew1 Pulse width distortion, |tPHL - tPLH| Same part output waveform skew 1.8 3.5 1.8 3.5 2.3 4 2.3 4 4.4 12 ns 3.3 12 ns 0.7 ns 4 ns 1.4 ns CL = 10 pF, TA = -40°C to 85°C, See Figure 2 and Figure 4 1.5 ns CL = 10 pF, See Figure 2 and Figure 4 0.3 ns 6 12 ns 4 12 ns 0.5 2 ns 0.5 2 ns CL = 5 pF See Figure 3 and Figure 5 CL = 10 pF, See Figure 2 and Figure 4 CL = 150 pF, See Figure 2 and Figure 4 CL = 10 pF, TA = 75°C, See Figure 2 and Figure 4 0.8 (2) tPZH Output enable time, high-impedance-to-high-level output tPZL Output enable time, high-impedance-to-low-level output (2) tTLH Rise time (20%-80%) tTHL Fall time (80%-20%) (1) (2) (3) max CL = 15 pF, See Figure 2 and Figure 4 (3) uni t typ CL = 0 pF (1), See Figure 2 and Figure 4 Δtskew1p-p Part-to-part output waveform skew (3) Δtskew min CL = 10 pF, See Figure 3 and Figure 4 CL = 10 pF, See Figure 2 and Figure 4 ns ns The propagation delay values with a 0 pF load are based on design and simulation. See Table 1. Output waveform skews are when devices operate with the same supply voltage, same temperature, have the same packages and the same test circuits. TYPICAL CHARACTERISTICS Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data transmission driver devices are measured with the following output load circuits. LOW-TO-HIGH PROPAGATION DELAY vs FREE-AIR TEMPERATURE HIGH-TO-LOW PROPAGATION DELAY vs FREE-AIR TEMPERATURE 5 t PHL - High to Low Propagation Delay - ns tPLH - Low-to-High Propagation Delay - ns 5 VCC = 3.3 V 4 Max 3 Nom 2 Min 1 -50 0 50 100 150 VCC = 3.3 V 4 Max 3 Min 2 1 -50 TA - Free-Air Temperature - 5C Figure 6. 4 Nom Submit Documentation Feedback 0 50 100 150 TA - Free-Air Temperature - 5C Figure 7. Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Links: TB3R1 TB3R2 TB3R1, TB3R2 www.ti.com SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (continued) MINIMUM VOH AND MAXIMUM VOL vs FREE-AIR TEMPERATURE TYPICAL AND MAXIMUM ICC vs FREE-AIR TEMPERATURE 35 3.5 VCC = 3.3 V VOH min ICC max at VCC = 3.6 V ICC - Supply Current - mA VO - Output Voltage - V 3 2.5 2 1.5 1 0.5 0 -50 30 25 20 ICC Typical at VCC = 3.3 V VOL max 0 50 100 TA - Free-Air Temperature - °C Figure 8. 150 15 -50 0 50 100 TA - Free-Air Temperature - 5C Figure 9. Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Links: TB3R1 TB3R2 150 5 TB3R1, TB3R2 SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008 www.ti.com APPLICATION INFORMATION Power Dissipation The power dissipation rating, often listed as the package dissipation rating, is a function of the ambient temperature, TA, and the airflow around the device. This rating correlates with the device's maximum junction temperature, sometimes listed in the absolute maximum ratings tables. The maximum junction temperature accounts for the processes and materials used to fabricate and package the device, in addition to the desired life expectancy. There are two common approaches to estimating the internal die junction temperature, TJ. In both of these methods, the device internal power dissipation PD needs to be calculated This is done by totaling the supply power(s) to arrive at the system power dissispation: ǒV Sn I SnǓ ȍ (1) and then subtracting the total power dissipation of the external load(s): ȍ(V Ln I Ln) (2) The first TJ calculation uses the power dissipation and ambient temperature, along with one parameter: θJA, the junction-to-ambient thermal resistance, in degrees Celsius per watt. The product of PD and θJA is the junction temperature rise above the ambient temperature. Therefore: T J + T A ) ǒPD q JAǓ (3) 140 Thermal Impedance − C/W 120 In this analysis, there are two parallel paths, one through the case (package) to the ambient, and another through the device to the PCB to the ambient. The system-level junction-to-ambient thermal impedance, θJA(S), is the equivalent parallel impedance of the two parallel paths: q JA(S) + 80 DW, High−K D, High−K 100 200 300 Air Flow − LFM q JA(S)Ǔ (4) where 100 60 400 500 Figure 10. Thermal Impedance vs Air Flow 6 The standardized θJA values may not accurately represent the conditions under which the device is used. This can be due to adjacent devices acting as heat sources or heat sinks, to nonuniform airflow, or to the system PCB having significantly different thermal characteristics than the standardized test PCBs. The second method of system thermal analysis is more accurate. This calculation uses the power dissipation and ambient temperature, along with two device and two system-level parameters: • θJC, the junction-to-case thermal resistance, in degrees Celsius per watt • θJB, the junction-to-board thermal resistance, in degrees Celsius per watt • θCA, the case-to-ambient thermal resistance, in degrees Celsius per watt • θBA, the board-to-ambient thermal resistance, in degrees Celsius per watt. T J + T A ) ǒPD D, Low−K DW, Low−K 40 0 Note that θJA is highly dependent on the PCB on which the device is mounted, and on the airflow over the device and PCB. JEDEC/EIA has defined standardized test conditions for measuring θJA. Two commonly used conditions are the low-K and the high-K boards, covered by EIA/JESD51-3 and EIA/JESD51-7 respectively. Figure 10 shows the lowK and high-K values of θJA versus air flow for this device and its package options. ƪǒq JC)q CAǓ ǒq JB)q BAǓƫ ǒq JC)q CA)q JB)q BAǓ (5) The device parameters θJC and θJB account for the internal structure of the device. The system-level parameters θCA and θBA take into account details of the PCB construction, adjacent electrical and mechanical components, and the environmental conditions including airflow. Finite element (FE), finite difference (FD), or computational fluid dynamics (CFD) programs can determine θCA and θBA. Details on using these programs are beyond the scope of this data sheet, but are available from the software manufacturers. Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Links: TB3R1 TB3R2 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TB3R1D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R1 Samples TB3R1DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R1 Samples TB3R2D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R2 Samples TB3R2DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R2 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of