TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
D Supports Pixel Rates Up to 165MHz
D
D
D
D
D
D 4x Over-Sampling for Reduced Bit-Error
(Including 1080p and WUXGA at 60 Hz)
Digital Visual Interface (DVI 1.0)
Specification Compliant1
Pin-for-Pin Compatible With TFP501 for
Simple Upgrade Path to HDCP2
True-Color, 24 Bit/Pixel, 16.7M Colors at
1 or 2-Pixels per Clock
Laser Trimmed (50 Ω) Input Stage for
Optimum Fixed Impedance Matching
Skew Tolerant up to One Pixel Clock Cycle
(High Clock and Data Jitter Tolerance)
D
D
D
Rates and Better Performance Over Longer
Cables
Reduced Power Consumption—1.8-V Core
Operation With 3.3 V I/Os and Supplies3
Reduced Ground Bounce Using Time
Staggered Pixel Outputs
Lowest Noise and Best Power Dissipation
Using PowerPAD™ Packaging
D Advanced Technology Using TI 0.18-μm
EPIC-5™ CMOS Process
D Supports Hot Plug Detection
description
The Texas Instruments TFP403 is a PanelBus™ flat panel display products, part of a comprehensive family of
end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the
TFP403 finds applications in any design requiring high-speed digital interface.
The TFP403 supports display resolutions up to 1080p and WUXGA in 24-bit true color pixel format. The TFP403
offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option
for time staggered pixel outputs for reduced ground bounce.
PowerPAD advanced packaging technology results in best of class power dissipation, footprint, and ultralow
ground inductance.
The TFP403 combines PanelBus™ circuit innovation with TIs advanced 0.18-μm EPIC-5™ CMOS process
technology, along with PowerPAD™ package technology to achieve a reliable, low-powered, low-noise,
high-speed digital interface solution.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1.
The Digital Visual Interface Specification (DVI) is an industry standard developed by the Digital Display Working Group (DDWG) for
high-speed digital connection to digital displays. The TFP403 is compliant with the DVI Specification Rev. 1.0.
2.
High-bandwidth digital content protection (HDCP) is the system used for protecting DVI outputs from being copied. The TFP501 is
TI’s DVI receiver with HDCP functionality.
The TFP403 has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V supplies.
3.
PanelBus, PowerPAD, and EPIC-5 are trademarks of Texas Instruments.
Copyright © 2002 − 2011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
QO22
QO21
QO20
QO19
QO18
QO17
QO16
DGND
CAP
QO15
QO14
QO13
QO12
QO11
QO10
QO9
QO8
OGND
OVDD
QO7
QO6
QO5
QO4
QO3
QO2
PZP PACKAGE
(TOP VIEW)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
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100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DFO
PD
ST
PIXS
DGND
DVDD
STAG
SCDT
PDO
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
OVDD
OGND
QE8
QE9
QE10
QE11
QE12
QE13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
OGND
QO23
OVDD
AGND
Rx2+
Rx2−
AVDD
Rx1+
Rx1−
AVDD
Rx0+
Rx0−
AVDD
RxC+
RxC−
AVDD
RSVD
RSVD
RSVD
RSVD
RSVD
PVDD
PGND
PVDD
OCK_INV
2
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QO1
QO0
HSYNC
VSYNC
DE
OGND
ODCK
OVDD
RSVD
CLT2
CLT1
DGND
DVDD
QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
OVDD
OGND
QE15
QE14
TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
functional block diagram
3.3 V
3.3 V
1.8 V
Regulator
Internal 50-Ω
Termination
3.3 V
RED(0-7)
Rx2+
Rx2-
+
_
Latch
Rx1+
Rx1-
+
_
Rx0+
Rx0-
+
_
Latch
RxC+
RxC-
+
_
PLL
Latch
Channel 2
CH2(0-9)
QE(0-23)
QO(0-23)
CTL3
CTL2
Channel 1
Data Recovery CH1(0-9)
TMDS
and
Decoder
Synchronization
Channel 0
CH0(0-9)
GRN(0-7)
CTL1
BLUE(0-7)
VSYNC
HSYNC
Panel
Interface
ODCK
DE
SCDT
CTL2
CTL1
VSYNC
HSYNC
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
79
GND
Analog ground—Ground reference and current return for analog circuitry
AVDD
82,85,88,
91
VDD
Analog VDD—Power supply for analog circuitry. Nominally 3.3 V
CAP
67
VDD
Bypass capacitor—4.7 μF tantalum and 0.01 μF ceramic connected to ground. This capacitor is optional for
the TFP403, but is required for the TFP501.
41,40
DO
General-purpose control signals—Used for user defined control. In normal mode CTL1 is not powered down
via PDO.
46
DO
Output data enable—Used to indicate time of active video display versus nonactive display or blank time.
During blank, only HSYNC, VSYNC, and CTL1-2 are transmitted. During times of active display, or nonblank,
only pixel data, QE[23:0] and QO[23:0], is transmitted.
CTL[2:1]
DE
High : Active display time
Low: Blank time
DFO
1
DI
Output clock data format—Controls the output clock (ODCK) format for either TFT or DSTN panel support. For
TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high; otherwise
ODCK is held low when DE is low.
High : DSTN support/ODCK held low when DE = low
Low: TFT support/ODCK runs continuously.
DGND
5,39,68
GND
Digital ground—Ground reference and current return for digital core
DVDD
6,38
VDD
Digital VDD—Power supply for digital core. Nominally 3.3 V
HSYNC
48
DO
Horizontal sync output
OCK_INV
100
DI
ODCK polarity—Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals
(HSYNC, VSYNC, DE, CTL1-2 ) are latched
Normal mode:
High : Latches output data on rising ODCK edge
Low : Latches output data on falling ODCK edge
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TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Output data clock—Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with
DE, HSYNC, VSYNC, and CTL[2:1] are synchronized to this clock.
ODCK
44
DO
OGND
19,28,45,
58,76
GND
Output driver ground—Ground reference and current return for digital output drivers
OVDD
18,29,43,
57,78
VDD
Output driver VDD—Power supply for output drivers. Nominally 3.3 V
2
DI
PD
Power down—An active low signal that controls the TFP403 power-down state. During power down all output
buffers are switched to a high impedance state. All analog circuits are powered down and all inputs are
disabled, except for PD.
If PD is left unconnected an internal pullup will default the TFP403 to normal operation.
High : Normal operation
Low: Power down
PDO
9
DI
Output drive power down—An active low signal that controls the power-down state of the output drivers.
During output drive powerdown, the output drivers (except SCDT and CTL1) are driven to a high impedance
state. A weak pulldown will slowly pull these outputs to a low level. When PDO is left unconnected, an internal
pullup defaults the TFP403 to normal operation.
High : Normal operation/output drivers on
Low: Output drive power down.
PGND
PIXS
98
4
GND
DI
PLL GND—Ground reference and current return for internal PLL
Pixel select—Selects between one or two pixels per clock output modes. During the 2-pixel/clock mode, both
even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During
1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even
pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the
odd pixel.)
High : 2-pixel/clock
Low: 1-pixel/clock
PVDD
97
VDD
PLL VDD—Power supply for internal PLL. Nominally 3.3 V
QE[0:7]
10-17
DO
Even blue pixel output—Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even only
blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE0/pin 10
MSB: QE7/pin 17
QE[8:15]
20-27
DO
Even green pixel output—Output for even and odd green pixels when in 1-pixel/clock mode. Output for even
only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE8/pin 20
MSB: QE15/pin 27
QE[16:23]
30-37
DO
Even red pixel output—Output for even and odd red pixels when in 1-pixel/clock mode. Output for even only
red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE16/pin 30
MSB: QE23/pin 37
QO[0:7]
49-56
DO
Odd blue pixel output—Output for odd only blue pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO0/pin 49
MSB: QO7/pin 56
QO[8:15]
59-66
DO
Odd green pixel output—Output for odd only green pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO8/pin 59
MSB: QO15/pin 66
QO[16:23]
69-75,77
DO
Odd red pixel output—Output for odd only red pixel when in 2-pixel/clock mode. Not used, and held low, when
in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO16/pin 69
MSB: QO23/pin 77
4
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TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
Terminal Functions (Continued)
TERMINAL
NAME
RSVD
NO.
I/O
DESCRIPTION
42
DO
Reserved. Must be tied high for normal operation
92−96
AI
Reserved. See TFP501 data sheet for intended future use.
RxC+
89
AI
Clock positive receiver input—Positive side of reference clock. TMDS low voltage signal differential input pair
RxC−
90
AI
Clock negative receiver input—Negative side of reference clock. TMDS low voltage signal differential input
pair
Rx0+
86
AI
Channel-0 positive receiver input—Positive side of channel-0. TMDS low voltage signal differential input pair.
Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank.
Rx0−
87
AI
Channel-0 negative receiver input—Negative side of channel-0. TMDS low voltage signal differential input
pair.
Rx1+
83
AI
Channel-1 positive receiver input—Positive side of channel-1 TMDS low voltage signal differential input pair.
Channel-1 receives green pixel data in active display and CTL1 control signals in blank.
Rx1−
84
AI
Channel-1 negative receiver input—Negative side of channel-1 TMDS low voltage signal differential input pair
Rx2+
80
AI
Channel-2 positive receiver input—Positive side of channel-2 TMDS low voltage signal differential input pair.
Channel-2 receives red pixel data in active display and CTL2 control signals in blank.
Rx2−
81
AI
Channel-2 negative receiver input—Negative side of channel-2 TMDS low voltage signal differential input
pair.
SCDT
8
DO
Sync detect—Output to signal when the link is active or inactive. The link is considered to be active when DE is
actively switching. The TFP403 monitors the state DE to determine link activity. SCDT can be tied externally to
PDO to power down the output drivers when the link is inactive.
High: Active link
Low: Inactive link
ST
3
DI
Output drive strength select—Selects output drive strength for high or low current drive. (See dc specifications
for IOH and IOL vs ST state.)
High : High drive strength
Low : Low drive strength
STAG
7
DI
Staggered pixel select—An active low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time staggers
the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels
simultaneously.
High : Normal simultaneous even/odd pixel output
Low: Time staggered even/odd pixel output
VSYNC
47
DO
Vertical sync output
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TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, DVDD, AVDD, OVDD, PVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
Input voltage range, logic/analog signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
Operating ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -−65°C to 150°C
Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Package power dissipation/PowerPAD: Soldered (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 W
Not soldered (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 W
ESD Protection, all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 KV Human Body Model
JEDEC latch up (EIA/JESD78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Specified with PowerPAD bond pad on the backside of the package soldered to a 2 oz. Cu plate PCB thermal plane. Specified at
maximum allowed operating temperature, 70°C.
2. PowerPAD bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating
temperature, 70°C.
recommended operating conditions
Supply voltage, VDD (DVDD, AVDD, PVDD, OVDD)
Pixel time, tpix‡
Operating free-air temperature, TA
6
TYP
MAX
3
3.3
3.6
V
40
ns
6.06
Single ended analog input termination resistance, Rt
‡
MIN
UNIT
45
50
55
Ω
0
25
70
°C
tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpix when in 1-pixel/clock mode
and 2tpix when in 2-pixel/clock mode.
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TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
dc digital I/O specifications
PARAMETER
VIH
High level digital input
voltage†
VIL
Low level digital input voltage†
IOH
High level output drive current‡
IOL
Low level output drive current‡
IOZ
Hi-Z output leakage current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2
DVDD
V
0
0.8
V
ST = High,
VOH = 2.4 V
5
10
18
ST = Low,
VOH = 2.4 V
3
6
12
ST = High,
VOL = 0.8 V
10
13
19
ST = Low,
VOL = 0.8 V
5
7
11
PD = Low or PDO = Low
−1
1
mA
mA
μA
†
Digital inputs are labeled DI in I/O column of Terminal Functions Table.
‡ Digital outputs are labeled DO in I/O column of Terminal Functions Table.
dc specifications
PARAMETER
TEST CONDITIONS
VID
Analog input differential voltage (see Note 3)
VIC
Analog input common mode voltage (see Note 3)
VI(OC)
Open circuit analog input voltage
MIN
TYP
MAX
75
UNIT
1200
mv
AVDD-300
AVDD-37
mv
AVDD-10
AVDD+10
mv
400
mA
IDD(2PIX)
Normal 2-pix/clock power supply current (see Note 4)
PIXEL RATE = 82.5 MHz
2-pix/clock
I(PD)
Power down current (see Note 5)
PD = Low
10
mA
I(PDO)
Output drive power down current (see Note 5)
PDO = Low
45
mA
NOTES: 3. Specified as dc characteristic with no overshoot or undershoot.
4. Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE[23:0] and QO[23:0] CL = 10 pF.
5. Analog inputs are open circuit (transmitter is disconnected from TFP403).
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TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
PARAMETER
TEST CONDITIONS
sensitivity†
MIN
TYP
150
MAX
UNIT
1560
mVp-p
VID(2)
Differential input
tps
Analog input intra-pair (+ to -) differential skew (see Note 6)
t(ccs)
Analog Input inter-pair or channel-to-channel skew
(see Note 6)
Analog Input inter-pair or channel-to-channel skew
(see Note 6)
t(ijit)
Worse case differential input clock jitter tolerance¶
(see Note 6)
Worse case differential input clock jitter tolerance¶
(see Note 6)
tf(1)
Fall time of data and control signals#, ||
ST = Low,
ST = High,
CL = 5 pF
CL = 10 pF
2.4
1.9
ns
tr(1)
Rise time of data and control signals#, ||
ST = Low,
ST = High,
CL = 5 pF
CL = 10 pF
2.4
1.9
ns
tr(2)
Rise time of ODCK clock#
ST = Low,
ST = High,
CL = 5 pF
CL = 10 pF
2.4
1.9
ns
tf(2)
Fall time of ODCK clock#
ST = Low,
ST = High,
CL = 5 pF
CL = 10 pF
2.4
1.9
ns
tsu(1)
Setup time, data, and control
signal to falling edge of ODCK
1 pixel, OCK_INV = low||,
PIXS = low
ST = Low,
ST = High,
CL = 5 pF
CL = 10 pF
1.0
ns
th(1)
Hold time
time, data
data, and control
signal
i
l to
t falling
f lli edge
d off ODCK
1 pixel,
pixel OCK
OCK_INV
INV = low||,
PIXS = low
l
ST = Low,
Low
ST = Hi
High,
h
CL = 5 pF
CL = 10 pF
F
1.0
ns
ST = Low,
Low
ST = Hi
High,
h
CL = 5 pF
CL = 10 pF
F
1.0
ns
ST = Low,
ST = High,
CL = 5 pF
CL = 10 pF
0.5
ns
tsu(2)
Setup time
time, data
data, and control
signal
i
l to
t rising
i i edge
d off ODCK
1 pixel,
pixel OCK
OCK_INV
INV =
PIXS = low
l
th(2)
Hold time, data, and control
signal to rising edge of ODCK
2 pixel and STAG
OCK_INV = high||
PIXS = high
f(ODCK)
ODCK frequency
high||,
tpd(PDOL)
Propagation delay time from PDO low to Hi-Z outputs
tt(HSC)
Transition time between DE transition to SCDT lowk
tt(FSC)
Transition time between DE transition to SCDT highk
td
1
tpix§
ps
PIX = Low (1-PIX/CLK)
25
165
PIX = High (2-PIX/CLK)
12.5
82.5
40%
Propagation delay time from PD low to Hi-Z outputs
tbit‡
50
ODCK duty-cycle
tpd(PDL)
0.4
50%
60%
9
9
Delay time, ODCK latching edge to QE[23:0] data output
STAG = Low
Pixs = High
†
MHz
ns
ns
1e6
tpix
1600
tpix
0.5
tpix
Specified as ac parameter to include sensitivity to overshoot, undershoot, and reflection.
tbit is 1/10 the pixel time, tpix
§t
pix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in
2-pixel/clock mode.
¶ Measured differentially at 50% crossing using ODCK output clock as trigger.
# Rise and fall times measured as time between 20% and 80% of signal amplitude.
|| Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1]
k Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
NOTE 6: By characterization
‡
8
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TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
PARAMETER MEASUREMENT INFORMATION
tr(2)
tf(2)
80%
ODCK
80%
20%
20%
Figure 1. Rise and Fall Time of ODCK
tr(1)
tf(1)
80%
QE(0-23), QO(0-23), DE
CTL(1-2), HSYNC, VSYNC
80%
20%
20%
Figure 2. Rise and Fall Time of Data and Control Signals
f(ODCK)
ODCK
Figure 3. ODCK Frequency
tsu(1)
tsu(2)
th(1)
VOH
VOL
ODCK
VOH
VOL
QE(0-23), QO(0-23), DE
CTL(1-2), HSYNC, VSYNC
th(2)
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
OCK_INV
Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK
VOH
ODCK
t(ps)
td
Tx+
50%
QE(O-23)
Tx-
50%
Figure 5. ODCK High to QE[23:0]
Staggered Data Output
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Figure 6. Analog Input Intra-Pair
Differential Skew
• DALLAS, TEXAS 75265
9
TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
PARAMETER MEASUREMENT INFORMATION
PD
PDO
VIL
VIL
tpd(PDL)
tpd(PDOL)
QE(0-23), QO(0-23),
ODCK, DE, CTL(1-2),
HSYNC, VSYNC, SCDT
QE(0-23), QO(0-23),
ODCK, DE, CTL2,
HSYNC, VSYNC
Figure 7. Delay From PD Low to Hi-Z Outputs
TX2
Figure 8. Delay From PDO Low to Hi-Z Outputs
50%
TX1
t(ccs)
TX0
50%
Figure 9. Analog Input Channel-to-Channel Skew
tt(HSC)
tt(FSC)
DE
SCDT
Figure 10. Time Between DE Transitions to SCDT Low and SCDT High
t(DEL)
t(DEH)
DE
Figure 11. Minimum DE Low and Maximum DE High
10
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TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
detailed description
fundamental operation
The TFP403 is a digital visual interface (DVI) compliant TMDS digital receiver that is used in digital flat panel
display systems to receive and decode TMDS encoded RGB pixel data streams. In a digital display system a
host, usually a PC or workstation, contains a DVI compatible transmitter that receives 24 bit pixel data along
with appropriate control signals. The transmitter encodes them into a high-speed low-voltage differential serial
bit stream optimized for transmission over a twisted-pair cable to a display device. The display device, usually
a flat-panel monitor, will require a DVI compatible receiver like the TI TFP403 to decode the serial bit stream
back to the same 24 bit pixel data and control signals that originated at the host. This decoded data can then
be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display
can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. To
support modern display resolutions up to UXGA a high bandwidth receiver with good jitter and skew tolerance
is required.
TMDS pixel data and control signal encoding
TMDS stands for transition minimized differential signaling. Only one of two possible TMDS characters for a
given pixel will be transmitted at a given time. The transmitter keeps a running count of the number of ones and
zeros previously sent and transmits the character that will minimize the number of transitions and approximate
a dc balance of the transmission line.
Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three
channels also receive control signals, HSYNC, VSYNC, and user defined control signals CTL[2:1]. These
control signals are received during inactive display or blanking-time. Blanking-time is when DE = low. The
following table maps the received input data to appropriate TMDS input channel in a DVI compliant system.
RECEIVED PIXEL DATA
ACTIVE DISPLAY DE = HIGH
INPUT CHANNEL
OUTPUT PINS
(VALID FOR DE = HIGH)
Red[7:0]
Channel – 2 (Rx2 ±)
QE[23:16] QO[23:16]
Green[7:0]
Channel – 1 (Rx1 ±)
QE[15:8] QO[15:8]
Blue[7:0]
Channel – 0 (Rx0 ±)
QE[7:0] QO[7:0]
RECEIVED CONTROL DATA
BLANKING DE = LOW
INPUT CHANNEL
OUTPUT PINS
(VALID FOR DE = LOW)
CTL[3:2] (see Note 7)
Channel – 2 (Rx2 ±)
CTL2
CTL[1: 0] (see Note 7)
Channel – 1 (Rx1 ±)
CTL1
HSYNC, VSYNC
Channel – 0 (Rx0 ±)
HSYNC, VSYNC
NOTE 7: Some TMDS transmitters transmit a CTL0 signal. The TFP403 decodes and
transfers CTL[2:1] and ignores CTL0 characters. CTL3 is used internally to enable
HDCP decryption. CTL3 and CTL0 are not available as TFP501 outputs.
The TFP403 discriminates between valid pixel TMDS characters and control TMDS characters to determine
the state of active display versus blanking, i.e., state of DE.
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11
TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
detailed description (continued)
TFP403 clocking and data synchronization
The TFP403 receives a clock reference from the DVI transmitter that has a period equal to the pixel time, Tpix.
The frequency of this clock is also referred to as the pixel rate. Since the TMDS encoded data on Rx[2:0]
contains 10 bits per 8 bit pixel it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example,
the required pixel rate to support an UXGA resolution with 60 Hz refresh rate is 165 MHz. The TMDS serial bit
rate is 10x the pixel rate or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on three
separate channels (or twisted-pair wires) of long distances (3-5 meters), phase synchronization between the
data steams and the input reference clock is not guaranteed. In addition, skew between the three data channels
is common. The TFP403 uses a 4x oversampling scheme of the input data streams to achieve reliable
synchronization with up to 1-Tpix channel-to-channel skew tolerance. Accumulated jitter on the clock and data
lines due to reflections and external noise sources is also typical of high speed serial data transmission, hence
the TFP403s design for high jitter tolerance.
The input clock to the TFP403 is conditioned by a phase-locked-loop (PLL) to remove high frequency jitter from
the clock. The PLL provides four 10x clock outputs of different phase to locate and sync the TMDS data streams
(4x oversampling). During active display the pixel data is encoded to be transition minimized, whereas in blank,
the control data is encoded to be transition maximized. A DVI compliant transmitter is required to transmit in
blank for a minimum period of time, 128-Tpix, to ensure sufficient time for data synchronization when the
receiver sees a transition maximized code. Synchronization during blank, when the data is transition
maximized, ensures reliable data bit boundary detection. Phase synchronization to the data streams is unique
for each of the three input channels and is maintained as long as the link remains active.
TFP403 TMDS input levels and input impedance matching
The TMDS inputs to the TFP403 receiver have a fixed single-ended termination to AVDD The TFP403 is
internally optimized using a laser trim process to precisely fix the impedance at 50 Ω. The device will function
normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current sockets.
The fixed impedance eliminates the need for an external resistor while providing optimum impedance matching
to standard 50-Ω DVI cables.
Figure 12 shows a conceptual schematic of a DVI transmitter and TFP403 receiver connection. A transmitter
drives the twisted pair cable via a current source, usually achieved with an open drain type output driver. The
internal resistor, which is matched to the cable impedance, at the TFP403 input provides a pullup to AVDD.
Naturally, when the transmitter is disconnected and the TFP403 DVI inputs are left unconnected, the TFP403
receiver inputs pullup to AVDD. The single ended differential signal and full differential signal is shown in
Figure 13. The TFP403 is designed to respond to differential signal swings ranging from 150 mV to 1.56 V with
common mode voltages ranging from (AVDD-300 mV) to (AVDD-37 mV).
12
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TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
TFP403 TMDS input levels and input impedance matching (continued)
DVI
Transmitter
TI TFP403
Receiver
AVDD
DVI Compliant Cable
Internal
Termination at 50 Ω
DATA
DATA
+
_
Current
Source
Figure 12. TMDS Differential Input and Transmitter Connection
1/2 VID
AVCC
VID
+ 1/2 VID
AVCC −1/2 VID
−1/2 VID
b) Differential Input Signal
a ) Single-Ended Input Signal
Figure 13. TMDS Inputs
TFP403 modes of operation
The TFP403 provides systems design flexibility and value by providing the system designer with configurable
options or modes of operation to support varying system architectures. The following table outlines the various
panel modes that can be supported along with appropriate external control pin settings.
PIXEL RATE
ODCK LATCH
EDGE
ODCK
DFO
PIXS
OCK_INV
TFT or 16-bit DSTN
1 pix/clock
Falling
Free run
0
0
0
TFT or 16-bit DSTN
1 pix/clock
Rising
Free run
0
0
1
TFT
2 pix/clock
Falling
Free run
0
1
0
TFT
2 pix/clock
Rising
Free run
0
1
1
24-bit DSTN
1 pix/clock
Falling
Gated low
1
0
0
NONE
1 pix/clock
Rising
Gated low
1
0
1
24-bit DSTN
2 pix/clock
Falling
Gated low
1
1
0
24-bit DSTN
2 pix/clock
Rising
Gated low
1
1
1
PANEL
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13
TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
detailed description (continued)
TFP403 output driver configurations
The TFP403 provides flexibility by offering various output driver features that can be used to optimize power
consumption, ground-bounce, and power-supply noise. The following sections outline the output driver features
and their effects.
Output driver power down (PDO = low), Pulling PDO low will place all the output drivers, except CTL1 and
SCDT, into a high-impedance state. The SCDT output which indicates link-disabled or link-inactive can be tied
directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected.
An internal pullup on the PDO pin will default the TFP403 to the normal nonpower down output drive mode if
left unconnected.
Drive Strength (ST = high for high drive strength, ST=low for low drive strength.) The TFP403 allows for
selectable output drive strength on the data, control and ODCK outputs. See the dc specifications table for the
values of IOH and IOL current drives for a given ST state. The high output strength offers approximately two times
the drive as the low output drive strength.
Time Staggered Pixel Output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high).
Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous
current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount
of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even
pixel is delayed from the latching edge of ODCK by 0.25 Tcip. (Tcip is the period of ODCK. The ODCK period
is 2Tpix when in 2-pixel/clock mode.)
Depending on system constraints of output load, pixel rate, panel input architecture and board cost the TFP403
drive strength and staggered pixel options allow flexibility to reduce system power-supply noise, ground bounce
and EMI.
Power Management. The TFP403 offers several system power management features.
The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode,
all output drivers except SCDT and CTL1 are driven to a high impedance state while the rest of the device
circuitry remains active
The TFP403 power down (PD = low) is a complete power down in that it powers down the digital core, the analog
circuitry, and output drivers. All output drivers are placed into a Hi-Z state. All inputs are disabled except for the
PD input. The TFP403 will not respond to any digital or analog inputs until PD is pulled high.
Both PDO and PD have internal pullup so if left unconnected they will default the TFP403 to normal operating
modes.
Sync Detect. The TFP403 offers an output, SCDT to indicate link activity. The TFP403 monitors activity on DE
to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, the
TFP403 considers the link inactive and SCDT is driven low. The SCDT goes high immediately after the first
transition on DE. The SCDT again becomes low when no more transitions are seen after 218 ocillator clocks.
SCDT can be used to signal a system power management circuit to initiate a system power down when the link
is considered inactive. The SCDT can also be tied directly to the TFP403 PDO input to power down the output
drivers when the link is inactive. It is not recommended to use the SCDT to drive the PD input since, once in
complete power down, the analog inputs are ignored and the SCDT state does not change. An external system
power management circuit to drive PD is preferred.
14
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TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
detailed description (continued)
PowerPAD 100-TQFP package
The TFP403 is packaged in TI’s thermally enhanced PowerPAD 100TQFP packaging. The PowerPAD package
is a 14 mm × 14 mm × 1 mm TQFP outline with 0.5 mm lead-pitch. The PowerPAD package has a specially
designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline.
The TI 100-TQFP PowerPAD package offers a back-side solder plane that connects directly to the die mount
pad for enhanced thermal conduction. Soldering the back side of the TFP403 to the application board is not
required thermally, as the device power dissipation is well within the package capability when not soldered.
Soldering the back side of the device to the PCB ground plane is recommended for electrical considerations.
Since the die pad is electrically connected to the chip substrate and hence chip ground, connection of the
PowerPAD back side to a PCB ground plane will help to improve EMI, ground bounce, and power supply noise
performance.
Table 1 outlines the thermal properties of the TI 100-TQFP PowerPAD package. The 100-TQFP non-PowerPAD
package is included only for reference.
Table 1. TI 100-TQFP (14 × 14 × 1 mm)/0.5 mm Lead Pitch
WITHOUT
PowerPAD
PowerPAD
NOT CONNECTED TO PCB
THERMAL PLANE
PowerPAD
CONNECTED TO PCB
THERMAL PLANE†
Theta-JA†,‡
45°C/W
27.3°C/W
17.3°C/W
Theta-JC†,‡
3.11°C/W
0.12°C/W
0.12°C/W
1.6 W
2.7 W
4.3 W
PARAMETER
Maximum power dissipation†,‡,§
†
Specified with 2 oz. Cu PCB plating.
‡ Airflow is at 0 LFM (no airflow)
§ Measured at ambient temperature, T = 70°C.
A
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15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TFP403PZP
ACTIVE
HTQFP
PZP
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TFP403PZP
TFP403PZPG4
ACTIVE
HTQFP
PZP
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TFP403PZP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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