THS4211DRB

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  SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004   

    
     FEATURES D Unity Gain Stability D Wide Bandwidth: 1 GHz D High Slew Rate: 970 V/µs D Low Distortion APPLICATIONS D High Linearity ADC Preamplifier D Differential to Single-Ended Conversion D DAC Output Buffer D Active Filtering D Video Applications − −90 dBc THD at 30 MHz D High Output Drive, IO = 200 mA D Excellent Video Performance D THS4211 − 130 MHz Bandwidth (0.1 dB, G = 2) − 0.007% Differential Gain − 0.003° Differential Phase Supply Voltages − +5 V, ±5 V, +12 V, +15 V Power Down Functionality (THS4215) NC IN− IN+ VS− D D Evaluation Module Available DESCRIPTION The THS4211 and THS4215 are high slew rate, unity gain stable voltage feedback amplifiers designed to run from supply voltages as low as 5 V and as high as 15 V. The THS4215 offers the same performance as the THS4211 with the addition of power-down capability. The combination of high slew rate, wide bandwidth, low distortion, and unity gain stability make the THS4211 and THS4215 high performance devices across multiple ac specifications. 7 3 6 4 5 NC VS+ VOUT NC RELATED DEVICES DEVICE DESCRIPTION THS4271 1.4 GHz voltage feedback amplifier THS4503 Wideband fully differential amplifier THS3202 Dual, wideband current feedback amplifier HARMONIC DISTORTION vs FREQUENCY +5 V −50 50 Ω Gain = 2 Rf = 392 Ω RL = 150 Ω VO = 2 VPP VS = ±5 V 49.9 Ω THS4211 _ −5 V 392 Ω 392 Ω NOTE: Power supply decoupling capacitors not shown VO Harmonic Distortion − dBc −55 + VI 8 2 Designers using the THS4211 are rewarded with higher dynamic range over a wider frequency band without the stability concerns of decompensated amplifiers. The devices are available in SOIC, MSOP with PowerPAD, and leadless MSOP with PowerPAD packages. Low-Distortion, Wideband Application Circuit 50 Ω Source 1 −60 −65 −70 −75 −80 HD2 −85 HD3 −90 −95 −100 1 10 f − Frequency − MHz 100 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.  
 
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 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT 16.5 V Supply voltage, VS ±VS Input voltage, VI Output current, IO (2) Continuous power dissipation See Dissipation Rating Table Maximum junction temperature, TJ (3) 150°C Maximum junction temperature, continuous operation, long term reliability TJ (4) 125°C Operating free-air temperature range, TA −40°C to 85°C Storage temperature range, Tstg −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds PACKAGE DISSIPATION RATINGS 300°C HBM 4000 V CDM ESD ratings: ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 100 mA 1500 V MM 200 V PACKAGE θJC (°C/W) θJA(1) (°C/W) POWER RATING(2) TA ≤ 25°C 1.02 W TA = 85°C 410 mW D (8 pin) 38.3 97.5 DGN (8 pin) 4.7 58.4 1.71 W 685 mW DGK (8 pin) 54.2 260 385 mW 154 mW DRB (8 pin) 5 45.8 2.18 W 873 mW (1) This data was taken using the JEDEC standard High-K test PCB. (2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long term reliability. (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The THS4211/5 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally enhanced package. (3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process. (4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. RECOMMENDED OPERATING CONDITIONS Supply voltage, (VS+ and VS−) MIN MAX Dual supply ±2.5 ±7.5 Single supply 5 15 VS− + 1.2 VS+ − 1.2 Input common-mode voltage range UNIT V V PACKAGING/ORDERING INFORMATION TEMPERATURE −40°C to 85°C PLASTIC SMALL OUTLINE (D) (1) ORDERABLE PACKAGE AND NUMBER PLASTIC MSOP (1) LEADLESS MSOP 8 (2) PowerPAD (DRB) PACKAGE MARKING (DGN) PLASTIC MSOP (1) PACKAGE MARKING (DGK) PACKAGE MARKING THS4211D THS4211DRB BET THS4211DGN BFN THS4211DGK BEJ THS4215D THS4215DRB BEU THS4215DGN BFQ THS4215DGK BEZ (1) All packages are available taped and reeled. The R suffix standard quantity is 2500 (e.g., THS4211DGNR). (2) All packages are available taped and reeled. The R suffix standard quantity is 3000. The T suffix standard quantity is 250 (e.g., THS4211DBVT). PIN ASSIGNMENTS (TOP VIEW) 2 D, DRB, DGK, DGN THS4211 NC 1 8 NC IN− 2 7 VS+ IN+ 3 6 VS− 4 5 (TOP VIEW) REF D, DRB, DGK, DGN THS4215 1 8 PD IN− 2 7 VS+ VOUT IN+ 3 6 VOUT NC VS− 4 5 NC 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS VS = ±5 V RF = 392 Ω, RL = 499 Ω, G = +1, unless otherwise noted. TYP PARAMETER TEST CONDITIONS 25°C OVER TEMPERATURE 25°C 0°C TO 70°C −40°C TO 85°C UNITS MIN/ TYP/ MAX AC PERFORMANCE G = 1, POUT = −7 dBm G = −1, POUT = −16 dBm G = 2, POUT = −16 dBm 1 GHz Typ 325 MHz Typ 325 MHz Typ G = 5, POUT = −16 dBm G = 10, POUT = −16 dBm 70 MHz Typ 35 MHz Typ G = 1, 70 MHz Typ 350 MHz Typ 77 MHz Typ 970 V/µs Typ G = −1, VO = 2 V Step G = −1, VO = 4 V Step 850 V/µs Typ 22 ns Typ G = −1, VO = 4 V Step G = 1, VO = 1 VPP, f = 30 MHz 55 ns Typ Second harmonic distortion RL = 150 Ω RL = 499 Ω −78 dBc Typ −90 dBc Typ Third harmonic distortion RL = 150 Ω RL = 499 Ω −100 dBc Typ −100 dBc Typ Harmonic distortion G = 2, −68 dBc Typ RL = 499 Ω RL = 150 Ω −70 dBc Typ −80 dBc Typ −82 dBc Typ Third order intermodulation (IMD3) RL = 499 Ω G = 2, VO = 2 VPP, RL = 150 Ω, f = 70 MHz −53 dBc Typ Third order output intercept (OIP3) G = 2, VO = 2 VPP, RL = 150 Ω, f = 70 MHz 32 dBm Typ Differential gain (NTSC, PAL) G = 2, 0.007 % Typ Differential phase (NTSC, PAL) G = 2, 0.003 _ Typ Input voltage noise f = 1 MHz 7 nV/√Hz Typ Input current noise f = 1 MHz 4 pA√Hz Typ Small signal bandwidth 0.1 dB flat bandwidth Gain bandwidth product Full-power bandwidth Slew rate Settling time to 0.1% Settling time to 0.01% Harmonic distortion Second harmonic distortion Third harmonic distortion POUT = −7 dBm G > 10 , f = 1 MHz G = −1, VO = 2 Vp G = 1, VO = 2 V Step VO = 2 VPP, f = 30 MHz RL = 150 Ω RL = 150 Ω RL = 150 Ω DC PERFORMANCE Open-loop voltage gain (AOL) Input offset voltage Average offset voltage drift Input bias current Average bias current drift Input offset current Average offset current drift VO = ±0.3 V, VCM = 0 V RL = 499 Ω 70 65 62 60 dB Min 3 12 14 14 mV Max VCM = 0 V VCM = 0 V ±40 ±40 µV/°C Typ 7 15 18 20 µA Max VCM = 0 V VCM = 0 V ±10 ±10 nA/°C Typ 0.3 6 7 8 µA Max ±10 ±10 nA/°C Typ VCM = 0 V 3 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS VS = ±5 V (continued) RF = 392 Ω, RL = 499 Ω, G = +1, unless otherwise noted. TYP PARAMETER TEST CONDITIONS OVER TEMPERATURE UNITS MIN/ TYP/ MAX ±3.6 V Min 48 dB Min 4 MΩ Typ 0.3 / 0.2 pF Typ 25°C 25°C 0°C to 70°C ±4 ±3.8 ±3.7 56 52 50 −40°C to 85°C INPUT CHARACTERISTICS Common-mode input range Input resistance VCM = ± 1 V Common-mode Input capacitance Common-mode / differential Common-mode rejection ratio OUTPUT CHARACTERISTICS ±4.0 ±3.8 ±3.7 ±3.6 V Min 220 200 190 180 mA Min Output current (sinking) RL = 10 Ω RL = 10 Ω 170 140 130 120 mA Min Output impedance f = 1 MHz 0.3 Ω Typ Output voltage swing Output current (sourcing) POWER SUPPLY Specified operating voltage ±5 ±7.5 ±7.5 ±7.5 V Max Maximum quiescent current 19 22 23 24 mA Max Minimum quiescent current 19 16 15 14 mA Min 64 58 54 54 dB Min 65 60 56 56 dB Min Power supply rejection (+PSRR) Power supply rejection (−PSRR) VS+ = 5.5 V to 4.5 V, VS− = 5 V VS+ = 5 V, VS− = −5.5 V to −4.5 V POWER-DOWN CHARACTERISTICS (THS4215 ONLY) Power-down voltage level Power-down quiescent current REF = 0 V, or VS− Enable REF = VS+ or Floating Enable Power-down Power-down REF+1.8 V Min REF+1 V Max REF−1 V Min REF−1.5 V Max PD = Ref +1.0 V, Ref = 0 V 650 850 900 1000 µA Max PD = Ref −1.5 V, Ref = 5 V 450 650 800 900 µA Max µs Typ Turnon time delay(t(ON)) 50% of final supply current value 4 Turnoff time delay (t(Off)) 50% of final supply current value 3 µs Typ 4 GΩ Typ 250 kΩ Typ Input impedance Output impedance 4 f = 1 MHz 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS VS = 5 V RF = 392 Ω, RL = 499 Ω, G = +1, unless otherwise noted TYP PARAMETER TEST CONDITIONS 25°C OVER TEMPERATURE 25°C 0°C to 70°C −40°C to 85°C UNITS MIN/ TYP/ MAX AC PERFORMANCE G = 1, POUT = −7 dBm G = −1, POUT = −16 dBm G = 2, POUT = −16 dBm 980 MHz Typ 300 MHz Typ 300 MHz Typ G = 5, POUT = −16 dBm G = 10, POUT = −16 dBm 65 MHz Typ 30 MHz Typ G = 1, 90 MHz Typ 300 MHz Typ 64 MHz Typ 800 V/µs Typ G = −1, VO = 2 V Step G = −1, VO = 2 V Step 750 V/µs Typ 22 ns Typ G = −1, VO = 2 V Step G = 1, VO = 1 VPP, f = 30 MHz 84 ns Typ Second harmonic distortion RL = 150 Ω RL = 499 Ω −60 dBc Typ −60 dBc Typ Third harmonic distortion RL = 150 Ω RL = 499 Ω −68 dBc Typ −68 dBc Typ Third order intermodulation (IMD3) G = 1, VO = 1 VPP , RL = 150 Ω, f = 70 MHz −70 dBc Typ Third order output intercept (OIP3) G = 1, VO = 1 VPP, RL = 150 Ω, f = 70 MHz 34 dBm Typ Input-voltage noise f = 1 MHz 7 nV/√Hz Typ Input-current noise f = 10 MHz 4 pA/√Hz Typ Small signal bandwidth 0.1 dB flat bandwidth Gain bandwidth product Full-power bandwidth Slew rate Settling time to 0.1% Settling time to 0.01% Harmonic distortion POUT = −7 dBm G > 10, f = 1 MHz G = −1, VO = 2 Vp G = 1, VO = 2 V Step DC PERFORMANCE Open-loop voltage gain (AOL) Input offset voltage Average offset voltage drift Input bias current Average bias current drift Input offset current Average offset current drift VO = ± 0.3 V, VCM = VS/2 RL = 499 Ω 68 63 60 60 dB Min 3 12 14 14 mV Max VCM = VS/2 VCM = VS/2 ±40 ±40 µV/°C Typ 7 15 17 18 µA Max VCM = VS/2 VCM = VS/2 ±10 ±10 nA/°C Typ 0.3 6 7 8 µA Max ±10 ±10 nA/°C Typ VCM = VS/2 INPUT CHARACTERISTICS Common-mode input range 1/4 1.2 / 3.8 1.3 / 3.7 1.4 / 3.6 V Min 54 50 48 45 dB Min Input resistance VCM = ± 0.5 V, VO = 2.5 V Common-mode 4 MΩ Typ Input capacitance Common-mode / differential 0.3 / 0.2 pF Typ Common-mode rejection ratio OUTPUT CHARACTERISTICS Output voltage swing 1/4 1.2 / 3.8 1.3 / 3.7 1.4 / 3.6 V Min 230 210 190 180 mA Min Output current (sinking) RL = 10 Ω RL = 10 Ω 150 120 100 90 mA Min Output impedance f = 1 MHz 0.3 Ω Typ Output current (sourcing) 5 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS VS = 5 V (continued) RF = 392 Ω, RL = 499 Ω, G = +1, unless otherwise noted TYP PARAMETER OVER TEMPERATURE UNITS MIN/ TYP/ MAX 15 V Max 24 mA Max 15 14 mA Min 58 54 54 dB Min 60 56 56 dB Min REF+1.8 V Min Power down REF+1 V Max Enable REF−1 V Min REF−1.5 V Max TEST CONDITIONS 25°C 25°C 0°C to 70°C Specified operating voltage 5 15 15 Maximum quiescent current 19 22 23 Minimum quiescent current 19 16 63 65 −40°C to 85°C POWER SUPPLY Power supply rejection (+PSRR) Power supply rejection (−PSRR) VS+ = 5.5 V to 4.5 V, VS− = 0 V VS+ = 5 V, VS− = −0.5 V to 0.5 V POWER-DOWN CHARACTERISTICS (THS4215 ONLY) Enable REF = 0 V, or VS− Power-down voltage level REF = VS+ or floating Power down Power-down quiescent current PD = Ref +1.0 V, Ref = 0 V 450 650 750 850 µA Max Power-down quiescent current PD = Ref −1.5 V, Ref = 5 V 400 650 750 850 µA Max Turnon-time delay(t(ON)) 50% of final value 4 µs Typ Turnoff-time delay (t(Off)) 50% of final value 3 µns Typ 6 GΩ Typ 75 kΩ Typ Input impedance Output impedance 6 f = 1 MHz 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS Table of Graphs (±5 V) FIGURE Small-signal unity gain frequency response 1 Small-signal frequency response 2 0.1 dB gain flatness frequency response 3 Large-signal frequency response 4 Slew rate vs Output voltage 5 Harmonic distortion vs Frequency Harmonic distortion vs Output voltage swing 6, 7, 8, 9 10, 11, 12, 13 Third order intermodulation distortion vs Frequency 14, 16 Third order output intercept point vs Frequency 15, 17 Voltage and current noise vs Frequency 18 Differential gain vs Number of loads 19 Differential phase vs Number of loads 20 Settling time 21 Quiescent current vs supply voltage 22 Output voltage vs Load resistance 23 Frequency response vs Capacitive load 24 Open-loop gain and phase vs Frequency 25 Open-loop gain vs Case temperature 26 Rejection ratios vs Frequency 27 Rejection ratios vs Case temperature 28 Common-mode rejection ratio vs Input common-mode range 29 Input offset voltage vs Case temperature 30 Input bias and offset current vs Case temperature 31 Small signal transient response 32 Large signal transient response 33 Overdrive recovery 34 Closed-loop output impedance vs Frequency 35 Power-down quiescent current vs Supply voltage 36 Power-down output impedance vs Frequency 37 Turnon and turnoff delay times 38 7 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS Table of Graphs (5 V) FIGURE Small-signal unity gain frequency response 39 Small-signal frequency response 40 0.1 dB gain flatness frequency response 41 Large signal frequency response 42 Slew rate vs Output voltage 43 Harmonic distortion vs Frequency 44, 45, 46, 47 Harmonic distortion vs Output voltage swing 48, 49, 50, 51 Third order intermodulation distortion vs Frequency 52, 54 Third order intercept point vs Frequency 53, 55 Voltage and current noise vs Frequency 56 Settling time 57 Quiescent current vs Supply voltage 58 Output voltage vs Load resistance 59 Frequency response vs Capacitive load 60 Open-loop gain and phase vs Frequency 61 Open-loop gain vs Case temperature 62 Rejection ratios vs Frequency 63 Rejection ratios vs Case temperature 64 Common-mode rejection ratio vs Input common-mode range 65 Input offset voltage vs Case temperature 66 Input bias and offset current vs Case temperature 67 Small signal transient response 68 Large signal transient response 69 Overdrive recovery 70 Closed-loop output impedance vs Frequency 71 Power-down quiescent current vs Supply voltage 72 Power-down output impedance vs Frequency 73 Turnon and turnoff delay times 74 8 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS (±5 V GRAPHS) SMALL SIGNAL UNITY GAIN FREQUENCY RESPONSE 0.1 22 20 Gain = 1 RL = 499 Ω VO = 250 mV VS = ±5 V 3 2 1 0 −1 −2 0 Gain = 10 18 Small Signal Gain − dB 4 16 Small Signal Gain − dB 5 Small Signal Gain − dB 0.1 dB GAIN FLATNESS FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE Gain = 5 14 RL = 499 Ω Rf = 392 Ω VO = 250 mV VS = ±5 V 12 10 8 6 Gain = 2 4 2 −4 100 k 1M 10 M 100 M 1G Gain = −1 −2 −4 100 k 1M 10 G f − Frequency − Hz Figure 1 10 M 100 M f − Frequency − Hz −1 −2 Gain = 1 RL = 499 Ω VO = 2 VPP VS = ±5 V 1000 800 Fall, Gain =− 1 Rise, Gain = −1 600 400 RL = 499 Ω Rf = 392 Ω VS = ±5 V 0 0.5 Figure 4 1.5 2 2.5 3 3.5 4 4.5 5 1 −80 −85 −90 HARMONIC DISTORTION vs FREQUENCY −80 Figure 7 100 HD2, RL = 150Ω −90 −100 10 HD2, RL = 499Ω −85 −100 f − Frequency − MHz HD3, RL = 150Ω, and RL = 499 Ω −75 Gain = 2 Rf = 392 Ω VO = 2 VPP VS = ±5 V −55 −70 −95 100 −50 −65 −95 10 Figure 6 Harmonic Distortion − dBc Harmonic Distortion − dBc HD2, RL = 150 Ω 1 −90 f − Frequency − MHz Gain = 2 Rf = 392 Ω VO = 1 VPP VS = ±5 V −60 HD2, RL = 499 Ω −75 HD2, RL = 499 Ω −85 HARMONIC DISTORTION vs FREQUENCY −65 −70 HD2, RL = 150 Ω −80 −100 −55 −60 HD3, RL = 150 Ω and RL = 499 Ω −75 Figure 5 HARMONIC DISTORTION vs FREQUENCY Harmonic Distortion − dBc 1 −70 VO − Output Voltage − V HD3, RL = 150 Ω and RL = 499 Ω 1G −95 0 1G Gain = 1 VO = 1 VPP VS = ±5 V −65 200 100 M 10 M 100 M f − Frequency − Hz HARMONIC DISTORTION vs FREQUENCY Fall, Gain = 1 f − Frequency − Hz −55 Gain = 1 RL = 499 Ω VO = 250 mV VS = ±5 V Figure 3 Harmonic Distortion − dBc SR − Slew Rate − V/ µ s Large Signal Gain − dB 0 Gain = 1 VO = 2 VPP VS = ±5 V −0.7 −60 1200 −50 −0.6 −1 1M 1G Rise, Gain = 1 10 M −0.5 −0.9 1400 1M −0.4 SLEW RATE vs OUTPUT VOLTAGE 1 −4 100 k −0.3 Figure 2 LARGE SIGNAL FREQUENCY RESPONSE −3 −0.2 −0.8 0 −3 −0.1 −60 −65 −70 HD2, RL = 499Ω −75 HD2, RL = 150Ω −80 HD3, RL = 150Ω, and RL = 499 Ω −85 −90 −95 1 10 f − Frequency − MHz Figure 8 100 −100 1 10 100 f − Frequency − MHz Figure 9 9 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING HD3, RL = 499Ω −85 −90 HD2, RL = 499Ω −95 −65 HD2, RL = 499Ω −70 HD2, RL = 150Ω −75 −80 −85 −90 −95 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 HD3, RL = 499Ω HD2, RL = 499Ω −70 −75 HD2, RL = 150Ω −85 −90 −95 −100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Third-Order Intermodulation Distortion − dBc 0.5 1 1.5 2 −100 4.5 5 0 −55 −60 −65 −70 VO = 2 VPP −75 −80 −85 −90 −95 VO = 1 VPP −100 10 −55 −60 −65 −70 VO = 2 VPP −75 −80 −85 −90 VO = 1 VPP −95 −100 10 100 f − Frequency − MHz Figure 16 50 45 VO = 1 VPP 40 VO = 2 VPP 35 30 0 100 20 40 60 80 Figure 15 VOLTAGE AND CURRENT NOISE vs FREQUENCY 100 50 45 VO = 1 VPP 40 100 f − Frequency − MHz Gain = 2 RL = 150 Ω VS = ±5 V 200 kHz Tone Spacing 55 4.5 5 Gain = 1 RL = 150 Ω VS = ±5 V 200 kHz Tone Spacing 55 THIRD ORDER OUTPUT INTERCEPT POINT vs FREQUENCY Third-Order Output Intersept Point − dBm −50 3.5 4 60 60 Gain = 2 RL = 150 Ω VS = ±5 V 200 kHz Tone Spacing 2.5 3 THIRD ORDER OUTPUT INTERCEPT POINT vs FREQUENCY Figure 14 −40 1.5 2 Figure 12 f − Frequency − MHz THIRD ORDER INTERMODULATION DISTORTION vs FREQUENCY −45 0.5 1 VO − Output Voltage Swing − ±V Gain = 1 RL = 150 Ω VS = ±5 V 200 kHz Tone Spacing −50 Figure 13 Third-Order Intermodulation Distortion − dBc 3.5 4 −45 VO − Output Voltage Swing − ±V 10 2.5 3 100 Hz Harmonic Distortion − dBc HD3, RL = 150Ω −80 HD2, RL = 150Ω −95 THIRD ORDER INTERMODULATION DISTORTION vs FREQUENCY −60 −65 HD3, RL = 499Ω −90 Figure 11 −40 −55 −85 VO − Output Voltage Swing − ±V HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING −50 HD3, RL = 150Ω −80 HD3, RL = 499Ω Figure 10 Gain = 2 Rf = 249 Ω f = 32 MHz VS = ±5 V HD2, RL = 499Ω −100 VO − Output Voltage Swing − ±V −45 −75 Vn − Voltage Noise − nV/ −100 Gain = 2 Rf = 249 Ω f = 8 MHz VS = ±5 V −70 Hz HD2, RL = 150Ω −60 HD3, RL = 150Ω Vn 10 35 VO = 2 VPP 30 10 In 25 1 20 0 20 40 60 f − Frequency − MHz Figure 17 80 100 1k 10 k 100 k 1M f − Frequency − Hz Figure 18 10 M 1 100 M I n − Current Noise − pA/ −80 −65 Gain = 1 f= 32 MHz VS = ±5 V −55 HD3, RL = 150Ω Third-Order Output Intersept Point − dBm −75 HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING Harmonic Distortion − dBc −50 Gain = 1 f= 8 MHz VS = ±5 V Harmonic Distortion − dBc Harmonic Distortion − dBc −70 HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 DIFFERENTIAL GAIN vs NUMBER OF LOADS DIFFERENTIAL PHASE vs NUMBER OF LOADS 0.030 0.015 ° Differential Phase − 0.020 Gain = 2 Rf = 392 Ω VS = ±5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.18 PAL NTSC 0.010 0.16 0.14 2 VO − Output Voltage − V Gain = 2 Rf = 392 Ω VS = ±5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.025 Differential Gain − % SETTLING TIME 3 0.20 0.12 0.10 PAL 0.08 0.06 NTSC 0.04 0.005 Rising Edge 1 −1 Gain = −1 RL = 499 Ω Rf = 392 Ω f= 1 MHz VS = ±5 V −2 Falling Edge 0 0.02 0 1 2 3 4 5 6 7 0 8 0 Number of Loads − 150 Ω 1 2 5 6 7 −3 8 TA = 85°C VO − Output Voltage − V TA = 25°C 18 TA = −40°C 16 14 12 5 1 4 0.5 3 2 1 4 4.5 TA = −40 to 85°C 0 −1 −2 10 5 100 100 30 80 20 60 10 40 0 20 10 M f − Frequency − Hz Figure 25 100 M 0 1G 1M 10 M 100 M 1G REJECTION RATIOS vs FREQUENCY 70 VS = ±5 V PSRR− 60 TA = 85°C 80 75 TA = −40°C 70 65 1M −2 Figure 24 Rejection Ratios − dB 40 Phase − ° 120 R(ISO) = 25 Ω CL = 10 pF Capacitive Load − Hz TA = 25°C 85 Open-Loop Gain − dB Open-Loop Gain − dB 50 100 k −1.5 −3 100 k 1000 90 160 140 R(ISO) = 15 Ω CL = 50 pF −1 OPEN-LOOP GAIN vs CASE TEMPERATURE 60 −10 10 k −0.5 Figure 23 OPEN-LOOP GAIN AND PHASE vs FREQUENCY 70 VS =±5 V R(ISO) = 10 Ω CL = 100 pF 0 RL − Load Resistance − Ω 180 25 −2.5 Figure 22 VS = ±5 V 20 −3 VS − Supply Voltage − ±V 80 15 FREQUENCY RESPONSE vs CAPACITIVE LOAD −5 3.5 10 Figure 21 −4 10 3 5 t − Time − ns OUTPUT VOLTAGE vs LOAD RESISTANCE 22 2.5 0 Figure 20 QUIESCENT CURRENT vs SUPPLY VOLTAGE Quiescent Current − mA 4 Number of Loads − 150 Ω Figure 19 20 3 Normalized Gain − dB 0 50 CMRR 40 30 PSRR+ 20 10 60 2.5 3 3.5 4 Case Temperature − °C Figure 26 4.5 5 0 100 k 1M 10 M 100 M 1G f − Frequency − Hz Figure 27 11 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 REJECTION RATIOS vs CASE TEMPERATURE COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE PSRR− 50 CMMR PSRR+ 40 30 20 10 0 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 8 50 45 40 35 30 25 20 15 10 VS = ±5 V TA = 25°C 5 0 −4.5 Case Temperature − °C −3 −1.5 Figure 28 0.65 6.4 6.3 0.6 0.55 IIB− 0.5 6.2 IOS 6.1 0.4 6 5.9 0.45 0.35 IIB+ 5.8 0.3 5.7 0.25 5.6 VO − Output Voltage − V VS = ±5 V 1 TC − Case Temperature − °C Figure 30 LARGE SIGNAL TRANSIENT RESPONSE 1 0.04 0.02 0 −0.02 Gain = −1 RL = 499 Ω Rf =392 Ω tr/tf = 300 ps VS = ±5 V −0.04 −0.06 −0.12 −1 0 1 2 3 4 5 6 t − Time − ns 0.5 0 −1 7 8 9 −1.5 −2 0 10 4 2 3 1.5 2 1 1 0.5 0 0 −1 −0.5 −2 −1 −3 −1.5 −4 −2 −5 −2.5 −6 −3 1 Closed-Loop Output Impedance − Ω 2.5 10 k 1k 10 1 0.1 1M 10 M 100 M f − Frequency − Hz Figure 35 6 8 10 12 14 16 18 20 POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE 800 RL = 499 Ω, RF = 392 Ω, PIN = −4 dBm VS = ±5 V 100 0.01 100 k 4 Figure 33 100 k 3 2 t − Time − ns CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY VS = ±5 V Gain = −1 RL = 499 Ω Rf = 392 Ω tr/tf = 300 ps VS = ±5 V −0.5 Figure 32 VI − Input Voltage − V Single-Ended Output Voltage − V 12 2 0 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 4.5 0.06 −0.1 OVERDRIVE RECOVERY Figure 34 3 0.08 Figure 31 t − Time − µs VS = 5 V 4 1.5 −0.08 0.2 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 5 0.12 0.1 TC − Case Temperature − °C 6 5 3 SMALL SIGNAL TRANSIENT RESPONSE 0.7 I OS − Input Offset Current − µ A I IB − Input Bias Current − µ A 6.5 1.5 VS = ±5 V 6 Figure 29 INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE 6.6 0 7 Input Common-Mode Range − V VO − Output Voltage − V Rejection Ratios − dB 60 9 55 Power-Down Quiescent Current − µ A 70 60 VOS − Input Offset Voltage − mV VS = ±5 V CMRR − Common-Mode Rejection Ratio − dB 80 INPUT OFFSET VOLTAGE vs CASE TEMPERATURE 1G TA = 85°C 700 600 500 TA = 25°C 400 TA = −40°C 300 200 100 0 2.5 3 3.5 4 4.5 VS − Supply Voltage − ±V Figure 36 5 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 0.1 10 M 100 M f − Frequency − Hz Figure 37 1G 4.5 0.03 10 1M 6 0.035 10 G 3 1.5 0.025 0.02 0 0.015 Gain = −1 RL = 499 Ω VS = ±5 V 0.01 −3 −4.5 0.005 −6 0 −0.005 −0.01 −1.5 V I − Input Voltage Level − V 0.04 Gain = 1 RL = 499 Ω PIN = −1 dBm VS = ±5 V 1000 0.001 100 k TURNON AND TURNOFF TIMES DELAY TIME VO − Output Voltage Level − V Power-Down Output Impedance − Ω POWER-DOWN OUTPUT IMPEDANCE vs FREQUENCY −7.5 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 t − Time − ns Figure 38 13 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS (5 V GRAPHS) SMALL SIGNAL UNITY GAIN FREQUENCY RESPONSE 4 22 1 0 −1 −2 1M 10 M 100 M 1G 16 Gain = 5 14 RL = 499 Ω Rf = 392 Ω VO = 250 mV VS = 5 V 12 10 8 6 Gain = 2 4 2 0 Gain = −1 −2 −4 100 k 1M −3 −4 100 k 10 G f − Frequency − Hz Figure 39 −1 −2 Gain = 1 RL = 499 Ω VO = 2 VPP VS = 5 V 10 M 100 M f − Frequency − Hz −1 1M 1G 800 Rise, G = 1 600 Rise, G = −1 500 Fall, G = −1 400 300 RL = 499 Ω Rf = 392 Ω VS = 5 V 0.4 −65 HD2 −75 −80 Figure 45 HD3 −85 −90 0.8 1 1.2 1.4 1.6 VO − Output Voltage −V 1.8 2 1 HD2 −70 100 HD3 −80 Gain = 2 VO = 1 VPP Rf = 392 Ω RL = 150 Ω and 499 Ω VS = 5 V 1 10 f − Frequency − MHz Figure 46 100 HARMONIC DISTORTION vs FREQUENCY −40 −60 10 f − Frequency − MHz Figure 44 −50 −100 −90 f − Frequency − MHz −80 −30 −90 10 HD2 −75 −40 −85 1 0.6 Harmonic Distortion − dBc Harmonic Distortion − dBc HD3 −70 −70 HARMONIC DISTORTION vs FREQUENCY Gain = 1 VO = 2 VPP RL = 150 Ω, and 499 Ω VS = 5 V −60 −65 Figure 43 HARMONIC DISTORTION vs FREQUENCY −55 −60 −100 Figure 42 −50 Gain = 1 VO = 1 VPP RL = 150 Ω, and 499 Ω VS = 5 V −95 0 −40 1G HARMONIC DISTORTION vs FREQUENCY 700 100 1G 10 M 100 M f − Frequency − Hz Figure 41 −55 200 100 M Gain = 1 RL = 499 Ω VO = 250 mV VS = 5 V −0.7 −50 f − Frequency − Hz −45 −0.6 −0.9 Harmonic Distortion − dBc SR − Slew Rate − V/ µ s Large Signal Gain − dB 0 10 M −0.5 Fall, G = 1 900 1M −0.4 −0.8 1000 −4 100 K −0.3 SLEW RATE vs OUTPUT VOLTAGE 1 −3 −0.2 Figure 40 LARGE SIGNAL FREQUENCY RESPONSE Harmonic Distortion − dBc 0 −0.1 Gain = 10 18 Small Signal Gain − dB Small Signal Gain − dB 2 0.1 20 Small Signal Gain − dB Gain = 1 RL = 499 Ω VO = 250 mV VS = 5 V 3 14 0.1 dB GAIN FLATNESS FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE 100 −50 HD2 HD3 −60 −70 Gain = 2 VO = 2 VPP Rf = 392 Ω RL = 150 Ω and 499 Ω VS = 5 V −80 −90 1 10 f − Frequency − MHz Figure 47 100 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING −45 −50 −65 −50 −55 −75 HD3 −80 −85 Gain = 1 RL = 150 Ω, and 499 Ω, f = 8 MHz VS = 5 V 0.5 1 1.5 2 VO − Output Voltage Swing − V HD3 −70 −75 Gain = 1 RL = 150 Ω, and 499 Ω, f = 32 MHz VS = 5 V −80 −85 −90 0.5 1 1.5 2 VO − Output Voltage Swing − V Figure 48 −50 −55 HD3 −60 Gain = 2 Rf = 392 Ω RL = 150 Ω and 499 Ω f = 32 MHz VS = 5 V −75 −80 0.5 1 1.5 2 2.5 0 −50 −55 −60 −65 VO = 2VPP −70 −75 −80 −85 VO = 1VPP −90 −95 −100 VO = 1VPP VO = 2VPP 35 30 0 10 VO = 1 VPP −90 −100 10 100 f − Frequency − MHz 20 30 40 50 60 35 VO = 1 VPP 30 80 Figure 53 VOLTAGE AND CURRENT NOISE vs FREQUENCY 100 40 70 f − Frequency − MHz Gain = 2 RL = 150 Ω VS = 5 V 200 kHz Tone Spacing 45 2.5 40 THIRD ORDER OUTPUT INTERCEPT POINT vs FREQUENCY Third-Order Output Intersept Point − dBm VO = 2 VPP 2 Gain = 1 RL = 150 Ω VS = 5 V 200 kHz Tone Spacing 45 100 50 −60 1.5 50 Figure 52 Gain = 1 RL = 150 Ω VS = 5 V 200 kHz Tone Spacing Figure 54 1 THIRD ORDER OUTPUT INTERCEPT POINT vs FREQUENCY f − Frequency − MHz −30 −80 0.5 VO − Output Voltage Swing − V Figure 50 10 THIRD ORDER INTERMODULATION DISTORTION vs FREQUENCY −70 2.5 Gain = 1 RL = 150 Ω VS = 5 V 200 kHz Tone Spacing −45 Figure 51 −50 −95 −40 VO − Output Voltage Swing − V −40 −90 100 Hz 0 Third-Order Intermodulation Distortion − dBc Harmonic Distortion − dBc HD2 −70 Gain = 2 Rf = 392 Ω RL = 150 Ω and 499 Ω f = 8 MHz VS = 5 V −85 THIRD ORDER INTERMODULATION DISTORTION vs FREQUENCY −40 −65 −80 Figure 49 HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING −45 −75 −100 0 2.5 HD3 −70 Vn − Voltage Noise − nV/ 0 −65 −65 Hz −100 −60 HD2 −60 Third-Order Output Intersept Point − dBm −90 HD2 Vn 10 VO = 2 VPP 25 20 10 In I n − Current Noise − pA/ −70 −55 Harmonic Distortion − dBc HD2 −95 Third-Order Intermodulation Distortion − dBc HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING −60 Harmonic Distortion − dBc Harmonic Distortion − dBc HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING 15 1 10 0 20 40 60 f − Frequency − MHz Figure 55 80 100 1k 10 k 100 k 1M 10 M 1 100 M f − Frequency − Hz Figure 56 15 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 QUIESCENT CURRENT vs SUPPLY VOLTAGE SETTLING TIME 1.5 OUTPUT VOLTAGE vs LOAD RESISTANCE 22 2 Rising Edge TA = 85°C 20 Gain = −1 RL = 499 Ω Rf = 392 Ω f= 1 MHz VS = 5 V 0 −0.5 Falling Edge −1 TA = 25°C 18 VO − Output Voltage − V 0.5 Quiescent Current − mA VO − Output Voltage − V 1 1.5 TA = −40°C 16 14 1 0.5 TA = −40 to 85°C 0 −0.5 −1 12 −1.5 −1.5 10 10 15 t − Time − ns 20 25 −2 2.5 3 Open-Loop Gain − dB R(ISO) = 15 Ω CL = 50 pF R(ISO) = 10 Ω CL = 100 pF 60 140 50 120 40 100 30 80 20 60 10 40 0 20 1M 10 M 100 M 1G −10 10 k 100 k 1M 80 75 TA = −40°C 70 PSRR− Rejection Ratios − dB 70 CMRR 40 30 PSRR+ 10 60 50 PSRR+ CMMR 40 30 20 10 1M 10 M 100 M f − Frequency − Hz Figure 63 60 2.5 1G 0 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 Case Temperature − °C Figure 64 3 3.5 4 4.5 5 Case Temperature − °C Figure 62 VS = 5 V PSRR− 20 0 1G 80 VS = 5 V 50 100 M REJECTION RATIOS vs CASE TEMPERATURE 70 60 10 M Figure 61 REJECTION RATIOS vs FREQUENCY Rejection Ratios − dB TA = 85°C f − Frequency − Hz Figure 60 16 TA = 25°C 85 65 VS = 5 V Capacitive Load − Hz 0 100 k 1000 90 160 COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE CMRR − Common-Mode Rejection Ratio − dB Normalized Gain − dB −3 100 k 100 RL − Load Resistance − Ω OPEN-LOOP GAIN vs CASE TEMPERATURE 180 VS = 5 V 70 R(ISO) = 25 Ω, CL = 10 pF −2 −2.5 10 Figure 59 80 0 −1.5 5 OPEN-LOOP GAIN AND PHASE vs FREQUENCY 1 −1 4.5 Figure 58 FREQUENCY RESPONSE vs CAPACITIVE LOAD −0.5 4 VS − Supply Voltage − ±V Figure 57 0.5 3.5 Phase − ° 5 Open-Loop Gain − dB 0 60 VS = 5 V 55 50 45 40 35 30 25 20 15 10 5 0 0 1 2 3 4 5 Input Common-Mode Voltage Range − V Figure 65 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE 8 6.5 6 5 VS = 5 V 4 3 2 0.65 6.4 0.6 IIB− 6.3 0.55 6.2 0.5 6.1 0.45 IIB+ 6 0.4 5.9 0.35 IOS 5.8 0.3 1 5.7 0 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 0.2 5.6 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 0.12 0.1 0 Gain = −1 RL = 499 Ω Rf = 392 Ω tr/tf = 300 ps VS = 5 V 1.5 2 1 1 0.5 0 0 −0.5 −2 −1 −3 −1.5 0 8 10 12 14 16 18 20 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 500 TA = 25°C TA = −40°C 300 200 100 0 3 3.5 4 4.5 VS − Supply Voltage − ±V 5 7 8 9 10 100 10 1 0.1 1M 10 M 100 M f − Frequency − Hz 1G Figure 71 0.035 Gain = 1 RL = 499 Ω PIN = −1 dBm VS = 5 V 0.1 1M 10 M 100 M f − Frequency − Hz Figure 73 1G 3 0.025 10 0.001 100 k 4.5 0.03 VO − Output Voltage Level − V 600 3 4 5 6 t − Time − ns POWER-DOWN OUTPUT IMPEDANCE vs FREQUENCY TURNON AND TURNOFF TIMES DELAY TIME Power-Down Output Impedance − Ω Power-Down Quiescent Current − µ A TA = 85°C 2 RL = 499 Ω, RF = 392 Ω, PIN = −4 dBm VS = 5 V 0.01 100 k 1000 800 Figure 72 1k Figure 70 POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE 2.5 10 k t − Time − µs Figure 69 1 100 k −1 t − Time − ns 400 0 CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY VI − Input Voltage − V 0.5 700 −0.06 −0.1 OVERDRIVE RECOVERY Single-Ended Output Voltage − V VO − Output Voltage − V 1 6 Gain = −1 RL = 499 Ω Rf =392 Ω tr/tf = 300 ps VS = 5 V −0.04 −0.12 −1 VS = 5 V 4 −0.02 Figure 68 3 1.5 2 0.02 0 Figure 67 LARGE SIGNAL TRANSIENT RESPONSE −1.5 −2 0 0.04 TC − Case Temperature − °C Figure 66 −1 0.06 −0.08 0.25 TC − Case Temperature − °C −0.5 0.08 10 G 1.5 0 0.02 0.015 −1.5 −3 0.01 0.005 0 −0.005 −0.01 0 Gain = −1 RL = 499 Ω VS = 5 V V I − Input Voltage Level − V VS = ±5 V VS = 5 V Closed-Loop Output Impedance − Ω 7 SMALL SIGNAL TRANSIENT RESPONSE 0.7 VO − Output Voltage − V 6.6 I OS − Input Offset Current − µ A 9 I IB − Input Bias Current − µ A VOS − Input Offset Voltage − mV INPUT OFFSET VOLTAGE vs CASE TEMPERATURE −4.5 −6 −7.5 0.01 0.02 0.03 0.04 0.05 0.06 0.07 t − Time − ns Figure 74 17 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 APPLICATION INFORMATION HIGH-SPEED OPERATIONAL AMPLIFIERS The THS4211 and the THS4215 operational amplifiers set new performance levels, combining low distortion, high slew rates, low noise, and a unity-gain bandwidth in excess of 1 GHz. To achieve the full performance of the amplifier, careful attention must be paid to printed-circuit board layout and component selection. The THS4215 provides a power-down mode, providing the ability to save power when the amplifier is inactive. A reference pin is provided to allow the user the flexibility to control the threshold levels of the power-down control pin. Applications Section Contents D D D D D D D D D D D D D D D D D D Wideband, Noninverting Operation Wideband, Inverting Gain Operation Single Supply Operation Saving Power With Power-Down Functionality and Setting Threshold Levels With the Reference Pin Power Supply Decoupling Techniques and Recommendations Using the THS4211 as a DAC Output Buffer Driving an ADC With the THS4211 Active Filtering With the THS4211 Building a Low-Noise Receiver With the THS4211 Linearity: Definitions, Terminology, Circuit Techniques and Design Tradeoffs An Abbreviated Analysis of Noise in Amplifiers Driving Capacitive Loads Printed-Circuit Board Layout Techniques for Optimal Performance Power Dissipation and Thermal Considerations Performance vs Package Options Evaluation Fixtures, Spice Models, and Applications Support Additional Reference Material Mechanical Package Drawings WIDEBAND, NONINVERTING OPERATION The THS4211 and the THS4215 are unity gain stable 1-GHz voltage feedback operational amplifiers, with and without power-down capability, designed to operate from a single 5-V to 15-V power supply. Figure 75 is the noninverting gain configuration of 2 V/V used to demonstrate the typical performance curves. Most of the curves were characterized using signal sources with 18 50-Ω source impedance, and with measurement equipment presenting a 50-Ω load impedance. In Figure 75, the 49.9-Ω shunt resistor at the VIN terminal matches the source impedance of the test generator. The total 499-Ω load at the output, combined with the 784-Ω total feedback network load, presents the THS4211 and THS4215 with an effective output load of 305 Ω for the circuit of Figure 75. Voltage feedback amplifiers, unlike current feedback designs, can use a wide range of resistors values to set their gain with minimal impact on their stability and frequency response. Larger-valued resistors decrease the loading effect of the feedback network on the output of the amplifier, but this enhancement comes at the expense of additional noise and potentially lower bandwidth. Feedback resistor values between 392 Ω and 1 kΩ are recommended for most situations. 5 V +V S + 100 pF 50 Ω Source 0.1 µF 6.8 µF + VI VO THS4211 49.9 Ω _ Rf 392 Ω 499 Ω 392 Ω Rg 0.1 µF 6.8 µF 100 pF −5 V + −VS Figure 75. Wideband, Noninverting Gain Configuration WIDEBAND, INVERTING GAIN OPERATION Since the THS4211 and THS4215 are general-purpose, wideband voltage-feedback amplifiers, several familiar operational amplifier applications circuits are available to the designer. Figure 76 shows a typical inverting configuration where the input and output impedances and noise gain from Figure 75 are retained in an inverting circuit configuration. Inverting operation is one of the more common requirements and offers several performance benefits. The inverting configuration shows improved slew rates and distortion due to the pseudo-static voltage maintained on the inverting input. 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 5 V +V S + 100 pF 0.1 µF 6.8 µF + RT 200 Ω CT 0.1 µF 50 Ω Source VI VO THS4211 _ 499 Ω Rg Rf 392 Ω RM 57.6 Ω 392 Ω 0.1 µF 100 pF −5 V The last major consideration in inverting amplifier design is setting the bias current cancellation resistor on the noninverting input. If the resistance is set equal to the total dc resistance looking out of the inverting terminal, the output dc error, due to the input bias currents, is reduced to (input offset current) multiplied by Rf in Figure 76, the dc source impedance looking out of the inverting terminal is 392 Ω || (392 Ω + 26.8 Ω) = 200 Ω. To reduce the additional high-frequency noise introduced by the resistor at the noninverting input, and power-supply feedback, RT is bypassed with a capacitor to ground. 6.8 µF + −VS Figure 76. Wideband, Inverting Gain Configuration In the inverting configuration, some key design considerations must be noted. One is that the gain resistor (Rg) becomes part of the signal channel input impedance. If the input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace, or other transmission line conductors), Rg may be set equal to the required termination value and Rf adjusted to give the desired gain. However, care must be taken when dealing with low inverting gains, as the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of 2, setting Rg to 49.9 Ω for input matching eliminates the need for RM but requires a 100-Ω feedback resistor. This has an advantage of the noise gain becoming equal to 2 for a 50-Ω source impedance—the same as the noninverting circuit in Figure 75. However, the amplifier output now sees the 100-Ω feedback resistor in parallel with the external load. To eliminate this excessive loading, it is preferable to increase both Rg and Rf, values, as shown in Figure 76, and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of Rg and RM. The next major consideration is that the signal source impedance becomes part of the noise gain equation and hence influences the bandwidth. For example, the RM value combines in parallel with the external 50-Ω source impedance (at high frequencies), yielding an effective source impedance of 50 Ω || 57.6 Ω = 26.8 Ω. This impedance is then added in series with Rg for calculating the noise gain. The result is 1.9 for Figure 76, as opposed to the 1.8 if RM is eliminated. The bandwidth is lower for the gain of –2 circuit, Figure 76, (NG=+1.9) than for the gain of +2 circuit in Figure 75. SINGLE SUPPLY OPERATION The THS4211 is designed to operate from a single 5-V to 15-V power supply. When operating from a single power supply, care must be taken to ensure the input signal and amplifier are biased appropriately to allow for the maximum output voltage swing. The circuits shown in Figure 77 demonstrate methods to configure an amplifier in a manner conducive for single supply operation. +VS 50 Ω Source + VI 49.9 Ω RT THS4211 VO _ 499 Ω +VS 2 Rf Rg 392 Ω +VS 2 392 Ω Rf 392 Ω 50 Ω Source VI 57.6 Ω +VS 2 VS Rg 392 Ω RT _ THS4211 + VO 499 Ω +VS 2 Figure 77. DC-Coupled Single Supply Operation Saving Power With Power-Down Functionality and Setting Threshold Levels With the Reference Pin The THS4215 features a power-down pin (PD) which lowers the quiescent current from 19-mA down to 650-µA, ideal for reducing system power. The power-down pin of the amplifiers defaults to the positive supply voltage in the absence of an applied voltage, putting the amplifier in the power-on mode of operation. To turn off the amplifier in an effort to conserve power, the power-down pin can be driven towards the 19 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 negative rail. The threshold voltages for power-on and power-down are relative to the supply rails and given in the specification tables. Above the Enable Threshold Voltage, the device is on. Below the Disable Threshold Voltage, the device is off. Behavior in between these threshold voltages is not specified. Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. The power-down mode is not intended to provide a highimpedance output. In other words, the power-down functionality is not intended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain setting resistors, but the output impedance of the device itself varies depending on the voltage applied to the outputs. The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach 50% of the nominal quiescent current. The time delays are on the order of microseconds because the amplifier moves in and out of the linear mode of operation in these transitions. Power-Down Reference Pin Operation In addition to the power-down pin, the THS4215 also features a reference pin (REF) which allows the user to control the enable or disable power-down voltage levels applied to the PD pin. Operation of the reference pin as it relates to the power-down pin is described below. In most split-supply applications, the reference pin will be connected to ground. In some cases, the user may want to connect it to the negative or positive supply rail. In either case, the user needs to be aware of the voltage level thresholds that apply to the power-down pin. The table below illustrates the relationship between the reference voltage and the power-down thresholds. POWER-DOWN PIN VOLTAGE REFERENCE VOLTAGE VS− to 0.5(VS− + VS+) 0.5(VS− + VS+) to VS+ DEVICE DISABLED DEVICE ENABLED ≤ Ref + 1.0 V ≥ Ref + 1.8 V ≤ Ref – 1.5 V ≥ Ref – 1 V The recommended mode of operation is to tie the reference pin to mid-rail, thus setting the threshold levels to mid-rail +1.0 V and midrail +1.8 V. NO. OF CHANNELS PACKAGES Single (8-pin) THS4215D, THS4215DGN, and THS4215DRB 20 Power Supply Decoupling Techniques and Recommendations Power supply decoupling is a critical aspect of any high-performance amplifier design process. Careful decoupling provides higher quality ac performance (most notably improved distortion performance). The following guidelines ensure the highest level of performance. 1. Place decoupling capacitors as close to the power supply inputs as possible, with the goal of minimizing the inductance of the path from ground to the power supply. 2. Placement priority should put the smallest valued capacitors closest to the device. 3. Use of solid power and ground planes is recommended to reduce the inductance along power supply return current paths, with the exception of the areas underneath the input and output pins. 4. Recommended values for power supply decoupling include a bulk decoupling capacitor (6.8 to 22 µF), a mid-range decoupling capacitor (0.1 µF) and a high frequency decoupling capacitor (1000 pF) for each supply. A 100 pF capacitor can be used across the supplies as well for extremely high frequency return currents, but often is not required. APPLICATION CIRCUITS Driving an Analog-to-Digital Converter With the THS4211 The THS4211 can be used to drive high-performance analog-to-digital converters. Two example circuits are presented below. The first circuit uses a wideband transformer to convert a single-ended input signal into a differential signal. The differential signal is then amplified and filtered by two THS4211 amplifiers. This circuit provides low intermodulation distortion, suppressed even-order distortion, 14 dB of voltage gain, a 50-Ω input impedance, and a single-pole filter at 100 MHz. For applications without signal content at dc, this method of driving ADCs can be very useful. Where dc information content is required, the THS4500 family of fully differential amplifiers may be applicable. 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 5V 3.3 V 3.3 V 392 Ω + VCM 100 Ω THS4211 100 Ω +5 V _ 50 Ω (1:4 Ω) Source 1:2 196 Ω 392 Ω DAC5675 −5 V 392 Ω 14-Bit, 400 MSps 24.9 Ω 196 Ω RF + 14-Bit, 62 Msps LO −5 V 392 Ω 15 pF 196 Ω 49.9 Ω THS4211 392 Ω ADS5422 15 pF _ 24.9 Ω 392 Ω Figure 80. Differential to Single-Ended Conversion of a High-Speed DAC Output _ THS4211 + VCM Figure 78. A Linear, Low Noise, High Gain ADC Preamplifier The second circuit depicts single-ended ADC drive. While not recommended for optimum performance using converters with differential inputs, satisfactory performance can sometimes be achieved with single-ended input drive. An example circuit is shown here for reference. 50 Ω Source +5 V For cases where a differential signaling path is desirable, a pair of THS4211 amplifiers can be used as output buffers. The circuit depicts differential drive into a mixer’s IF inputs, coupled with additional signal gain and filtering. THS4211 + 3.3 V 3.3 V _ 100 Ω 100 Ω CF 1 nF 1 nF IF+ + VI 49.9 Ω RT RISO 0.1 µF _ −5 V 16.5 Ω Rf 392 Ω Rg DAC5675 THS4211 IN 68 pf ADS807 12-Bit, CM 53 Msps IN 1.82 kΩ 0.1 µF 14-Bit, 400 MSps 392 Ω 100 Ω 392 Ω 392 Ω 49.9 Ω 392 Ω 49.9 Ω RF(out) IF− 1 nF 1 nF _ CF 392 Ω + THS4211 NOTE: For best performance, high-speed ADCs should be driven differentially. See the THS4500 family of devices for more information. Figure 79. Driving an ADC With a Single-Ended Input Using the THS4211 as a DAC Output Buffer Two example circuits are presented here showing the THS4211 buffering the output of a digital-to-analog converter. The first circuit performs a differential to single-ended conversion with the THS4211 configured as a difference amplifier. The difference amplifier can double as the termination mechanism for the DAC outputs as well. Figure 81. Differential Mixer Drive Circuit Using the DAC5675 and the THS4211 Active Filtering With the THS4211 High-frequency active filtering with the THS4211 is achievable due to the amplifier’s high slew-rate, wide bandwidth, and voltage feedback architecture. Several options are available for high-pass, low-pass, bandpass, and bandstop filters of varying orders. A simple two-pole low pass filter is presented here as an example, with two poles at 100 MHz. 21 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 100 Ω 3.9 pF + VI− 50 Ω Source 392 Ω Rf1 5V 57.6 Ω _ Rf2 _ 392 Ω VI Rg2 THS4211 Rg1 49.9 Ω THS4211 VO + 33 pF _ −5 V Rg2 THS4211 100 Ω Figure 82. A Two-Pole Active Filter With Two Poles Between 90 MHz and 100 MHz _ Rf1 49.9 Ω VO THS4211 + 49.9 Ω + Rf2 VI+ Figure 84. A High-Speed Instrumentation Amplifier ǒ A Low-Noise Receiver With the THS4211 A combination of two THS4211 amplifiers can create a high-speed, low-distortion, low-noise differential receiver circuit as depicted in Figure 83. With both amplifiers operating in the noninverting mode of operation, the circuit presents a high load impedance to the source. The designer has the option of controlling the impedance through termination resistors if a matched termination impedance is desired. VI+ 100 Ω + 49.9 Ω VO+ _ 392 Ω 787 Ω Ǔ ǒ Ǔ 2R f1 ǒ R f2 VO + 1 1 ) V i)–V i–Ǔ 2 Rg1 Rg2 100 Ω (1) THEORY AND GUIDELINES Distortion Performance The THS4211 provides excellent distortion performance into a 150-Ω load. Relative to alternative solutions, it provides exceptional performance into lighter loads, as well as exceptional performance on a single 5-V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd harmonic will dominate the total harmonic distortion with a negligible 3rd harmonic component. Focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. The total load includes the feedback network; in the noninverting configuration (Figure 75) this is the sum of Rf and Rg, while in the inverting configuration (Figure 76), only Rf needs to be included in parallel with the actual load. 392 Ω _ VI− 100 Ω 49.9 Ω VO− + Figure 83. A High Input Impedance, Low Noise, Differential Receiver A modification on this circuit to include a difference amplifier turns this circuit into a high-speed instrumentation amplifier, as shown in Figure 84. 22 LINEARITY: DEFINITIONS, TERMINOLOGY, CIRCUIT TECHNIQUES, AND DESIGN TRADEOFFS The THS4211 features execllent distortion performance for monolithic operational amplifiers. This section focuses on the fundamentals of distortion, circuit techniques for reducing nonlinearity, and methods for equating distortion of operational amplifiers to desired linearity specifications in RF receiver chains. Amplifiers are generally thought of as linear devices. The output of an amplifier is a linearly scaled version of the input signal applied to it. However, amplifier transfer functions are nonlinear. Minimizing amplifier nonlinearity is a primary design goal in many applications. 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 Intercept points are specifications long used as key design criteria in the RF communications world as a metric for the intermodulation distortion performance of a device in the signal chain (e.g., amplifiers, mixers, etc.). Use of the intercept point, rather than strictly the intermodulation distortion, allows simpler system-level calculations. Intercept points, like noise figures, can be easily cascaded back and forth through a signal chain to determine the overall receiver chain’s intermodulation distortion performance. The relationship between intermodulation distortion and intercept point is depicted in Figure 85 and Figure 86. Power PO PO ∆fc = fc − f1 ∆fc = f2 − fc IMD3 = PS − PO PS fc − 3∆f f2 However, with an operational amplifier, the output does not require termination as an RF amplifier would. Because closed-loop amplifiers deliver signals to their outputs regardless of the impedance present, it is important to comprehend this when evaluating the intercept point of an operational amplifier. The THS4211 yields optimum distortion performance when loaded with 150 Ω to 1 kΩ, very similar to the input impedance of an analog-to-digital converter over its input frequency band. As a result, terminating the input of the ADC to 50 Ω can actually be detrimental to systems performance. The discontinuity between open-loop, class-A amplifiers and closed-loop, class-AB amplifiers becomes apparent when comparing the intercept points of the two types of devices. Equations 1 and 2 gives the definition of an intercept point, relative to the intermodulation distortion. PS f1 fc Due to the intercept point’s ease of use in system level calculations for receiver chains, it has become the specification of choice for guiding distortion-related design decisions. Traditionally, these systems use primarily class-A, single-ended RF amplifiers as gain blocks. These RF amplifiers are typically designed to operate in a 50-Ω environment. Giving intercept points in dBm implies an associated impedance (50 Ω). fc + 3∆f OIP 3 + P O ) f − Frequency − MHz ǒ Figure 85 P O + 10 log POUT (dBm) 1X ǒŤIMD2 ŤǓ where 3 Ǔ V 2P 2RL 0.001 (2) (3) NOTE: PO is the output power of a single tone, RL is the load resistance, and VP is the peak voltage for a single tone. OIP3 NOISE ANALYSIS PO IMD3 IIP3 3X PS Figure 86 PIN (dBm) High slew rate, unity gain stable, voltage-feedback operational amplifiers usually achieve their slew rate at the expense of a higher input noise voltage. The 7 nV/√Hz input voltage noise for the THS4211 and THS4215 is, however, much lower than comparable amplifiers. The input-referred voltage noise, and the two input-referred current noise terms (4 pA/√Hz), combine to give low output noise under a wide variety of operating conditions. Figure 87 shows the amplifier noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. 23 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 THS4211/THS4215 ENI of the THS4211. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the THS4211 output pin (see Board Layout Guidelines). + RS IBN ERS EO _ 4kTRS Rf Rg 4kT Rg IBI ERF The criterion for setting this R(ISO) resistor is a maximum bandwidth, flat frequency response at the load. For a gain of +2, the frequency response at the output pin is already slightly peaked without the capacitive load, requiring relatively high values of R(ISO) to flatten the response at the load. Increasing the noise gain also reduces the peaking. 4kTRf 4kT = 1.6E−20J at 290K Figure 87. Noise Analysis Model FREQUENCY RESPONSE vs CAPACITIVE LOAD The total output shot noise voltage can be computed as the square of all square output noise voltage contributors. Equation 3 shows the general form for the output noise voltage using the terms shown in Figure 87: Ǹǒ Ǔ ENI 2 ) ǒIBNRSǓ ) 4kTR S NG 2 ) ǒIBIRfǓ ) 4kTRfNG 2 2 0.5 (4) Normalized Gain − dB EO + 1 Dividing this expression by the noise gain (NG=(1+ Rf/Rg)) gives the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 4: EO + Ǹ E NI 2 ǒ Ǔ 2 I R ) ǒI BNRSǓ ) 4kTR S ) BI f NG 2 4kTR f ) NG VS =±5 V R(ISO) = 10 Ω CL = 100 pF 0 −0.5 R(ISO) = 15 Ω CL = 50 pF −1 −1.5 R(ISO) = 25 Ω CL = 10 pF −2 −2.5 (5) −3 100 k 1M 10 M 100 M 1G Capacitive Load − Hz Driving Capacitive Loads One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter, including additional external capacitance, which may be recommended to improve A/D linearity. A high-speed, high open-loop gain amplifier like the THS4211 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. When the primary considerations are frequency response flatness, pulse response fidelity, or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended isolation resistor vs capacitive load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2 pF can begin to degrade the performance 24 Figure 88. Isolation Resistor Diagram BOARD LAYOUT Achieving optimum performance with a high frequency amplifier like the THS4211 requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include the following: 1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. 2. Minimize the distance (< 0.25”) from the power supply pins to high frequency 0.1-µF de-coupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the 

 www.ti.com SLOS400C − SEPTEMBER 2002 − REVISED JANUARY 2004 a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary onboard, and in fact a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined on the basis of board material and trace dimensions, a matching series resistor into the trace from the output of the THS4211 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of R(ISO) vs capacitive load. This setting does not preserve signal integrity or a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. 3. 4. Careful selection and placement of external components preserves the high frequency performance of the THS4211. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wire-wound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input-termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2.0 kΩ, this parasitic capacitance can add a pole and/or a zero below 400 MHz that can effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. A good starting point for design is to set the Rf to 249 Ω for low-gain, noninverting applications. This setting automatically keeps the resistor noise terms low and minimizes the effect of their parasitic capacitance. Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of recommended RISO vs capacitive load. Low parasitic capacitive loads (