TL082CP/PB

TL082-N www.ti.com SNOSBW5C – APRIL 1998 – REVISED APRIL 2013 TL082 Wide Bandwidth Dual JFET Input Operational Amplifier Check for Samples: TL082-N FEATURES DESCRIPTION • • • • • • • • • • • These devices are low cost, high speed, dual JFET input operational amplifiers with an internally trimmed input offset voltage ( BI-FET II™ technology). They require low supply current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The TL082 is pin compatible with the standard LM1558 allowing designers to immediately upgrade the overall performance of existing LM1558 and most LM358 designs. 1 23 Internally Trimmed Offset Voltage: 15 mV Low Input Bias Current: 50 pA Low Input Noise Voltage: 16nV/√Hz Low Input Noise Current: 0.01 pA/√Hz Wide Gain Bandwidth: 4 MHz High Slew Rate: 13 V/μs Low Supply Current: 3.6 mA High Input Impedance: 1012Ω Low Total Harmonic Distortion: ≤0.02% Low 1/f Noise Corner: 50 Hz Fast Settling Time to 0.01%: 2 μs These amplifiers may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The devices also exhibit low noise and offset voltage drift. Typical Connection Connection Diagram Figure 1. PDIP/SOIC Package (Top View) See Package Number D0008A or P0008E 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. BI-FET II is a trademark of dcl_owner. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2013, Texas Instruments Incorporated TL082-N SNOSBW5C – APRIL 1998 – REVISED APRIL 2013 www.ti.com Simplified Schematic These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage Power Dissipation ±18V (3) (4) Operating Temperature Range 0°C to +70°C Tj(MAX) 150°C Differential Input Voltage Input Voltage Range ±30V (5) ±15V Output Short Circuit Duration Continuous Storage Temperature Range −65°C to +150°C Lead Temp. (Soldering, 10 seconds) 260°C ESD rating to be determined. (1) (2) (3) (4) (5) 2 “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The power dissipation limit, however, cannot be exceeded. For operating at elevated temperature, the device must be derated based on a thermal resistance of 115°C/W junction to ambient for the P0008E package. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: TL082-N TL082-N www.ti.com SNOSBW5C – APRIL 1998 – REVISED APRIL 2013 DC Electrical Characteristics Symbol VOS (1) Parameter Conditions Input Offset Voltage TL082C Min RS = 10 kΩ, TA = 25°C Max 5 15 mV 20 mV Over Temperature ΔVOS/ΔT Average TC of Input Offset Voltage RS = 10 kΩ IOS Input Offset Current Tj = 25°C, 25 Tj ≤ 70°C IB Input Bias Current Tj = 25°C, μV/°C 10 (1) (2) (1) (2) Units Typ 50 Tj ≤ 70°C 200 pA 4 nA 400 pA 8 nA 1012 Ω 100 V/mV RIN Input Resistance Tj = 25°C AVOL Large Signal Voltage Gain VS = ±15V, TA = 25°C, VO = ±10V, RL = 2 kΩ Over Temperature 15 VO Output Voltage Swing VS = ±15V, RL = 10 kΩ ±12 ±13.5 V VCM Input Common-Mode Voltage Range VS = ±15V ±11 +15 V CMRR Common-Mode Rejection Ratio RS ≤ 10 kΩ PSRR Supply Voltage Rejection Ratio IS Supply Current (3) 25 V/mV −12 V 70 100 dB 70 100 3.6 dB 5.6 mA These specifications apply for VS = ±15V and 0°C ≤TA ≤ +70°C. VOS, IB and IOS are measured at VCM = 0. The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature, Tj. Due to the limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj = TA + θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS = ±6V to ±15V. (1) (2) (3) AC Electrical Characteristics Symbol (1) Parameter Conditions TL082C Min Typ −120 Max Units Amplifier to Amplifier Coupling TA = 25°C, f = 1Hz-20 kHz (Input Referred) SR Slew Rate VS = ±15V, TA = 25°C 13 V/μs GBW Gain Bandwidth Product VS = ±15V, TA = 25°C 4 MHz en Equivalent Input Noise Voltage TA = 25°C, RS = 100Ω, f = 1000 Hz 25 nV/√Hz in Equivalent Input Noise Current Tj = 25°C, f = 1000 Hz 0.01 pA/√Hz THD Total Harmonic Distortion AV = +10, RL = 10k, VO = 20 Vp − p, BW = 20 Hz−20 kHz