! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
+
−
DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE
vs
FREQUENCY
description
80
240
VDD = 1.8 V & 2.7 V
RL= 2 kΩ
CL = 10 pF
TA = 25° C
70
60
50
40
210
180
150
120
Phase
30
90
20
60
30
10
0
Gain
0
−10
Phase Margin − °
D
D
Operational Amplifier
Supply Voltage Range . . . 1.8 V to 3.6 V
Rail-to-Rail Input/Output
High Bandwidth . . . 8 MHz
High Slew Rate . . . 4.8 V/µs
VICR Exceeds Rails . . . −0.2 V to VDD+ 0.2
Supply Current . . . 650 µA/Channel
Input Noise Voltage . . . 9 nV/√Hz at 10 kHz
Specified Temperature Range:
0°C to 70°C . . . Commercial Grade
−40°C to 125°C . . . Industrial Grade
Ultrasmall Packaging
Universal Operational Amplifier EVM
A VD − Differential Voltage Amplification − dB
D
D
D
D
D
D
D
D
−30
The TLV278x single supply operational amplifiers
−60
−20
provide rail-to-rail input and output capability. The
−30
−90
TLV278x takes the minimum operating supply
−120
−40
1k
10 k
100 k
1M
10 M
voltage down to 1.8 V over the extended industrial
f − Frequency − Hz
temperature range (−40°C to 125°C) while adding
the rail-to-rail output swing feature. The TLV278x also provides 8 MHz bandwidth from only 650 µA of supply
current. The maximum recommended supply voltage is 3.6 V, which allows the devices to be operated from
(±1.8 V supplies down to ±0.9 V) two rechargeable cells.
The combination of wide bandwidth, low noise, and low distortion makes it ideal for high speed and high
resolution data converter applications.
All members are available in PDIP, SOIC, and the newer, smaller SOT-23 (singles), MSOP (duals), and TSSOP
(quads).
FAMILY PACKAGE TABLE
DEVICE
VDD
[V]
VIO
[µV]
IDD/ch
[µA]
IIB
[pA]
GBW
[MHz]
SLEW RATE
[V/µs]
Vn, 1 kHz
[nV/√Hz]
IO
[mA]
SHUTDOWN
RAIL-TORAIL
TLV278x(A)
1.8−3.6
250
650
2.5
8
5
18
10
Y
I/O
TLV276x(A)
1.8−3.6
550
20
3
0.5
0.23
95
5
Y
I/O
TLV246x(A)
2.7−6
150
550
1300
6.4
1.6
11
25
Y
I/O
TLV247x(A)
2.7−6
250
600
2.5
2.8
1.5
15
20
Y
I/O
TLV244x(A)
2.7−10
300
750
1
1.81
1.4
16
2
—
O
TLV277x(A)
2.5−5.5
360
1000
2
5.1
10.5
17
6
Y
O
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000−2005, Texas Instruments Incorporated
" #$%&'()*#&$ #+ ,-''.$* )+ &% /-01#,)*#&$ 2)*.
'&2-,*+ ,&$%&'( *& +/.,#%#,)*#&$+ /.' *3. *.'(+ &% .
)+ $+*'-(.$*+
+*)$2)'2 4)'')$*5 '&2-,*#&$ /'&,.++#$6 2&.+ $&* $.,.++)'#15 #$,1-2.
*.+*#$6 &% )11 /)')(.*.'+
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1
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
TLV2780 and TLV2781 AVAILABLE OPTIONS(1)
PACKAGED DEVICES
VIOmax
AT 25°C
TA
0°C to 70°C
SOT-23
SMALL OUTLINE
(D)†
(DBV)‡
SYMBOL
PLASTIC DIP
(P)
3000 µV
TLV2780CD
TLV2781CD
TLV2780CDBV
TLV2781CDBV
VASC
VATC
—
—
3000 µV
TLV2780ID
TLV2781ID
TLV2780IDBV
TLV2781IDBV
VASI
VATI
TLV2780IP
TLV2781IP
2000 µV
TLV2780AID
TLV2781AID
—
—
—
—
—
—
- 40°C to 125°C
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2780CDR).
‡ This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suffix (i.e., TLV2780CDBVR). For
smaller quantities (250 pieces per mini-reel), add a T suffix to the part number (e.g. TLV2780CDBVT).
TLV2782 and TLV2783 AVAILABLE OPTIONS(1)
PACKAGED DEVICES
VIOmax
AT 25°C
TA
0°C to 70°C
SMALL
OUTLINE†
(D)
(DGK)†
SYMBOL
(DGS)†
3000 µV
TLV2782CD
TLV2783CD
TLV2782CDGK
—
xxTIADL
—
3000 µV
TLV2782ID
TLV2783ID
TLV2782IDGK
—
2000 µV
TLV2782AID
TLV2783AID
—
—
−40°C to 125°C
SYMBOL
PLASTIC
DIP
(N)
PLASTIC
DIP
(P)
—
TLV2783CDGS
—
xxTIADN
—
—
—
—
xxTIADM
—
—
TLV2783IDGS
—
xxTIADO
—
TLV2783IN
TLV2782IP
—
—
—
—
—
—
—
—
—
—
—
MSOP
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2782CDR).
TLV2784 and TLV2785 AVAILABLE OPTIONS(1)
PACKAGED DEVICES
TA
VIOmax
AT 25°C
0°C to 70°C
SMALL OUTLINE
(D)
PLASTIC DIP
(N)
TSSOP†
(PW)
3000 µV
TLV2784CD
TLV2785CD
—
—
TLV2784CPW
TLV2785CPW
3000 µV
TLV2784ID
TLV2785ID
TLV2784IN
TLV2785IN
TLV2784IPW
TLV2785IPW
2000 µV
TLV2784AID
TLV2785AID
−40°C to 125°C
—
—
TLV2784AIPW
TLV2785AIPW
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number
(e.g., TLV2784CDR).
1. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
2
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! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
TLV278x PACKAGE PINOUTS
TLV2780
D OR P PACKAGE
(TOP VIEW)
TLV2780
DBV PACKAGE
(TOP VIEW)
OUT
1
6
VDD
GND
2
5
SHDN
IN+
3
4
IN −
TLV2781
D OR P PACKAGE
(TOP VIEW)
NC
IN −
IN +
GND
1OUT
1IN −
1IN+
GND
NC
1SHDN
NC
1
8
2
7
3
6
4
5
NC
IN −
IN +
GND
1
8
2
7
3
6
4
5
TLV2781
DBV PACKAGE
(TOP VIEW)
SHDN
VDD
OUT
NC
OUT
1
GND
2
IN+
3
1OUT
1IN −
1IN +
GND
1
8
2
7
3
6
4
5
VDD
2OUT
2IN −
2IN+
VDD
4
IN −
TLV2783
DGS PACKAGE
(TOP VIEW)
TLV2782
D, DGK, OR P PACKAGE
(TOP VIEW)
NC
VDD
OUT
NC
5
1OUT
1IN −
1IN+
GND
1SHDN
1
2
3
4
5
10
9
8
7
6
VDD
2OUT
2IN −
2IN+
2SHDN
TLV2783
D OR N PACKAGE
TLV2784
D, N, OR PW PACKAGE
TLV2785
D, N, OR PW PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VDD
2OUT
2IN −
2IN+
NC
2SHDN
NC
1OUT
1IN −
1IN+
VDD
2IN+
2IN −
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN −
4IN+
GND
3IN+
3IN −
3OUT
1OUT
1IN −
1IN+
VDD
2IN+
2IN −
2OUT
1/2SHDN
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
4OUT
4IN −
4IN+
GND
3IN +
3IN−
3OUT
3/4SHDN
NC − No internal connection
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3
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VDD
Input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
ΘJC
(°C/W)
ΘJA
(°C/W)
TA ≤ 25°C
25 C
POWER RATING
TA = 125
125°C
C
POWER RATING
D (8)
38.3
176
710 mW
142 mW
D (14)
26.9
122.3
1022 mW
204.4 mW
D (16)
25.7
114.7
1090 mW
218 mW
DBV (5)
55
324.1
385 mW
77.1 mW
DBV (6)
55
294.3
425 mW
85 mW
DGK (8)
54.2
259.9
481 mW
96.2 mW
DGS (10)
54.1
257.7
485 mW
97 mW
N (14, 16)
32
78
1600 mW
320.5 mW
P (8)
41
104
1200 mW
240.4 mW
PW (14)
29.3
173.6
720 mW
144 mW
PW (16)
28.7
161.4
774 mW
154.9 mW
recommended operating conditions
Single supply
Supply voltage, VDD
Split supply
Common-mode input voltage range, VICR
Operating free-air temperature, TA
Shutdown on/off voltage level‡
C-suffix
I-suffix
VIH
VDD < 2.7 V
VDD = 2.7 to 3.6 V
VIL
MAX
1.8
3.6
±0.9
±1.8
V
−0.2
V
0
VDD+0.2
70
−40
125
0.75VDD
2
WWW.TI.COM
UNIT
°C
V
0.6
‡ Relative to GND.
4
MIN
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
electrical characteristics at specified free-air temperature, VDD = 1.8 V, 2.7 V (unless otherwise
noted)
dc performance
PARAMETER
TEST CONDITIONS
TA†
MIN
25°C
TLV278x
VIO
αVIO
Input offset voltage
VO = VDD/2,
RL = 2 kΩ,
RS = 50 Ω
AVD
3000
250
Full range
2000
VIC = 0 to VDD,
RS = 50 Ω
RL = 2 kΩ,
VO(PP) = 1 V
VDD = 1.8 V
VDD = 2.7 V/ 3.6 V
VDD = 2.7 V/ 3.6 V
VDD = 1.8 V
UNIT
µV
V
3000
V/°C
µV/°C
8
VIC = 1.2 V to VDD,
RS = 50 Ω
Large-signal differential voltage
amplification
250
4500
Temperature coefficient of input offset
voltage
CMRR Common-mode rejection ratio
MAX
Full range
25°C
TLV278xA
TYP
25°C
50
Full range
50
25°C
55
Full range
50
25°C
70
Full range
70
25°C
200
Full range
50
25°C
200
76
80
dB
100
600
V/mV
1000
VDD = 2.7 V/ 3.6 V
Full range
70
† Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is − 40°C to 125°C.
input characteristics
PARAMETER
IIO
IIB
ri(d)
TEST CONDITIONS
Input offset current
VO = VDD/2,
RL = 2 kΩ,
RS = 50 Ω
Input bias current
TA†
25°C
MIN
TYP
MAX
2.5
15
TLV278xC
Full range
100
TLV278xI
Full range
300
25°C
2.5
Full range
100
TLV278xI
Full range
300
25°C
pA
15
TLV278xC
Differential input resistance
UNIT
pA
1000
GΩ
Ci(c)
Common-mode input capacitance
f = 1 kHz
25°C
19
† Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is − 40°C to 125°C.
pF
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5
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
electrical characteristics at specified free-air temperature, VDD = 1.8 V, 2.7 V (unless otherwise
noted) (continued)
output characteristics
PARAMETER
IOH = − 1 mA
VOH
TA†
MIN
TYP
25°C
1.7
1.77
VDD = 1.8 V
Full range
1.63
25°C
2.6
VDD = 2.7 V
Full range
2.6
VDD = 3.6 V
25°C
TEST CONDITIONS
High-level output voltage
IOH = − 5 mA
2.68
1.5
VDD = 1.8 V
Full range
1.46
25°C
2.5
VDD = 2.7 V
Full range
2.45
VDD = 3.6 V
25°C
2.55
3.55
70
Full range
80
25°C
Low-level output voltage
VDD = 1.8 V
Full range
VDD = 2.7 V
Full range
IOL = 5 mA
IO
IOS
180
Output current
VDD = 2.7 V,
VO = 0.5 V from
120
170
10
Negative rail
15
25°C
mA
17
Negative rail
23
13
Sourcing
VDD = 1.8 V
VDD = 2.7 V
Sinking
VDD = 1.8 V
VDD = 2.7 V
Short-circuit output current
mV
200
Positive rail
Positive rail
240
290
25°C
VDD = 1.8 V,
VO = 0.5 V from
V
1.55
25°C
VOL
UNIT
3.58
25°C
IOL = 1 mA
MAX
35
25°C
mA
21
45
† Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is − 40°C to 125°C.
power supply
PARAMETER
IDD
kSVR
Supply current (per channel)
Supply voltage rejection ratio
((∆V
VDD //∆V
VIO)
TEST CONDITIONS
VO = VDD/2,
SHDN = VDD
VDD = 1.8 V to 2.7 V,
VIC = VDD /2
No load,
VDD = 2.7 V to 3.6 V,
VIC = VDD /2
No load,
VDD = 1.8 V to 3.6 V,
VIC = VDD /2
No load,
TA†
25°C
MIN
TYP
MAX
650
770
Full range
820
25°C
60
Full range
58
25°C
75
Full range
70
25°C
65
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µA
A
75
90
dB
80
Full range
60
† Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is − 40°C to 125°C.
6
UNIT
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
electrical characteristics at specified free-air temperature, VDD = 1.8 V, 2.7 V (unless otherwise
noted) (continued)
dynamic performance
PARAMETER
UGBW
SR+
Unity gain bandwidth
Positive slew rate at unity gain
TA†
TEST CONDITIONS
RL = 2 kΩ,
CL = 25 pF
VO(PP) = 1 V,
RL = 2 kΩ,
kΩ
CL = 50 pF
MIN
25°C
25°C
3.3
Full range
3.1
25°C
3.8
VDD = 2.7 V
Full range
3.5
25°C
SR−
φm
Negative slew rate at unity gain
Settling time
4
Full range
3.6
25°C
2.1
VDD = 1.8 V
Full range
1.89
25°C
2.2
VDD = 2.7 V
Full range
1.97
25°C
3.5
VDD = 3.6 V
Full range
3.4
Phase margin
Gain margin
ts
VO(PP) = 1 V,
RL = 2 kΩ,
kΩ
CL = 50 pF
MAX
8
VDD = 1.8 V
VDD = 3.6 V
TYP
UNIT
MHz
4.3
4.8
5
V/ s
V/µs
2.8
2.8
4.2
58°
25°C
RL = 2 kΩ,
CL = 25 pF
VDD = 1.8 V,
V(STEP)PP = 1 V,
AV = −1,
CL = 10 pF, RL = 2 kΩ
0.1%
VDD = 2.7 V,
V(STEP)PP = 1 V,
AV = −1,
CL = 10 pF, RL = 2 kΩ
0.1%
1.7
0.01%
2.4
8
dB
1.7
0.01%
2.8
µss
25°C
† Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is − 40°C to 125°C.
noise/distortion performance
PARAMETER
THD + N
Total harmonic distortion plus noise
TEST CONDITIONS
VO(PP) = VDD/2,
RL = 2 kΩ,
f = 10 kHz
Equivalent input noise voltage
In
Equivalent input noise current
MIN
AV = 1
AV = 10
AV = 100
f = 1 kHz
Vn
TA
TYP
MAX
UNIT
0.055%
0.08%
0.45%
25°C
18
f = 10 kHz
nV/√Hz
9
f = 1 kHz
0.9
fA /√Hz
shutdown characteristics
PARAMETER
IDD(SHDN)
Supply current, per channel in shutdown mode
(TLV2780, TLV2783, TLV2785)
TEST CONDITIONS
SHDN = 0 V
TA†
25°C
Full range
MIN
TYP
MAX
900
1400
1700
UNIT
nA
t(on)
Amplifier turnon time‡
RL = 2 kΩ
800
25°C
ns
t(off)
Amplifier turnoff time‡
RL = 2 kΩ
200
† Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is − 40°C to 125°C.
‡ Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
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7
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
CMRR
Input offset voltage
vs Common-mode input voltage
Common-mode rejection ratio
vs Frequency
VOH
VOL
High-level output voltage
vs High-level output current
4, 6
Low-level output voltage
vs Low-level output current
5, 7
VO(PP)
Zo
Maximum peak-to-peak output voltage
vs Frequency
Output impedance
vs Frequency
9
IDD
IDD
Supply current
vs Supply voltage
10
Supply current
vs Free-air temperature
11
PSRR
Power supply rejection ratio
vs Frequency
12
AVD
Differential voltage amplification & phase
vs Frequency
13
Gain-bandwidth product
vs Free-air temperature
14
vs Supply voltage
1, 2
3
8
15
SR
Slew rate
φm
Vn
Phase margin
vs Load capacitance
18
Equivalent input noise voltage
vs Frequency
19
Voltage-follower large-signal pulse response
vs Time
20
Voltage-follower small-signal pulse response
vs Time
21
Inverting large-signal pulse response
vs Time
22
Inverting small-signal pulse response
vs Time
23
Crosstalk
vs Frequency
24
Shutdown forward & reverse isolation
vs Frequency
25
IDD(SHDN)
IDD(SHDN)
Shutdown supply current
vs Free-air temperature
26
Shutdown supply current
vs Supply voltage
27
IDD(SHDN)
Shutdown supply current/output voltage
vs Time
28
8
vs Free-air temperature
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16, 17
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
400
100
VDD=1.8 V
50
TA=25° C
VIO − Input Offset Voltage − µ V
VIO − Input Offset Voltage − µ V
200
VDD=2.7 V
0
−200
−400
−600
−800
TA=25 °C
0
−50
−100
−150
−200
−250
−300
−350
−1000
−0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VICR − Common-Mode Input Voltage − V
−400
−0.2 0.2 0.6
1
1.4 1.8 2.2 2.6 3
VICR − Common-Mode Input Voltage − V
Figure 1
Figure 2
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
1.2
1.0
TA = 125°C
0.8
TA = 70°C
TA = 25°C
TA = 0°C
TA = −40°C
0.6
0.4
0.2
1.6
1.4
TA=125°C
1.2
TA=70°C
1.0
TA=25°C
TA=0°C
TA=−40°C
0.8
0.6
0.4
0.2
4
6
8
10
12
14
0
16
VDD= 2.7 V
2.4
2.1
TA=125°C
1.8
TA= 70°C
TA=25°C
TA=0°C
TA=−40°C
1.5
1.2
0.9
0.6
0.3
0.0
0
5
10 15 20 25 30 35 40 45 50 55
IOL − Low-Level Output Current − mA
Figure 7
V O(PP) − Maximum Peak-To-Peak Output Voltage − V
2.7
1.8
1.5
TA=125°C
1.2
TA=70°C
0.9
TA=25°C
TA=0°C
TA=−40°C
0.6
0.3
0
0
5
10
2.2
2.0
1.8
VO(PP)= 1.8 V
1.4
1.2
0.4
100
35
40
VDD = 2.7 V
TA = 25° C
VO(PP)= 2.7 V
2.4
0.6
30
100
2.6
0.8
25
OUTPUT IMPEDANCE
vs
FREQUENCY
2.8
1.0
20
Figure 6
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
1.6
15
IOH − High-Level Output Current − mA
Figure 5
Figure 4
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
10M
2.1
IOL − Low-Level Output Current − mA
IOH − High-Level Output Current − mA
1M
VDD = 2.7 V
2.4
2 4 6 8 10 12 14 16 18 20 22 24 26 28
Z o − Output Impedance − Ω
2
1k 10k 100k
100
f − Frequency − Hz
10
2.7
0.0
0.0
0
VDD = 1.8 V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
V OH − High-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
V OH − High-Level Output Voltage − V
1.4
VDD = 2.7 V
Figure 3
VDD=1.8 V
VDD=1.8 V
VDD = 3.6 V
0
1.8
1.6
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1.8
VOL − Low-Level Output Voltage − V
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR − Common-Mode Rejection Ratio − dB
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
AV = −10
RL=2 kΩ
CL = 10 pF
TA = 25° C
1k
10 k
100 k
f − Frequency − Hz
Figure 8
WWW.TI.COM
1M
10 M
10
1
AV = 10
AV = 1
0.1
100
1k
10k
100k
f − Frequency − Hz
1M
10M
Figure 9
9
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
TYPICAL CHARACTERISTICS
1.4
600
1.35
I DD − Supply Current − mA
I DD − Supply Current − µ A
700
TA = 125°C
500
TA = −40°C
400
TA = 25°C
300
200
1.3
VDD = 2.7 V
1.2
VDD = 1.8 V
1.15
0.6
1.2
1.8
2.4
3
AV = 1
VIC = VDD/2
1.1
1.05
1
−40 −25 −10 5 20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
0
0
VDD = 3.6 V
1.25
AV= 1
VIC = VDD/2 V
100
3.6
VDD − Supply Voltage − V
Figure 10
VDD=2.7 V
TA=25°C
100
80
60
40
20
0
10
60
50
240
9
210
8
180
150
120
Phase
30
90
20
60
10
30
Gain
0
Gain-Bandwidth Product − MHz
VDD = 1.8 V & 2.7 V
RL= 2 kΩ
CL = 10 pF
TA = 25° C
70
0
−10
−30
−20
−60
−30
1M
10 M
VDD = 1.8 V
6
5
VDD = 2.7 V
4
3
2
1
RL = 2 kΩ
CL = 10 pF
f = 10 kHz
TA − Free-Air Temperature − °C
Figure 14
SLEW RATE
vs
SUPPLY VOLTAGE
SR+
5
AV = 1
RL = 2 kΩ
CL =10 pF
VO = 1 VPP
VIC = VDD/2
TA = 25° C
3
2
2
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD − Supply Voltage − V
Figure 15
4
SR−
3
VDD = 1.8 V
AV = 1
RL=2 kΩ
CL=10 pF
VIC = VDD/2
2
1
0
−40 −25 −10 5 20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
Figure 16
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SR − Slew Rate − V/µs
SR+
SR − Slew Rate − V/µs
SR − Slew Rate − V/µs
5
SR−
1
10
6
6
7
0
1.8
SLEW RATE
vs
FREE-AIR TEMPERATURE
SLEW RATE
vs
FREE-AIR TEMPERATURE
8
4
10 M
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
Figure 13
5
100 k 1 M
0
−40 −25 −10 5 20 35 50 65 80 95 110 125
−120
100 k
10 k
7
−90
10 k
1k
f − Frequency − Hz
f − Frequency − Hz
6
100
Figure 12
Phase Margin − °
A VD − Differential Voltage Amplification − dB
80
−40
1k
120
Figure 11
DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE
vs
FREQUENCY
40
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
PSRR − Power Supply Rejection Ratio − dB
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
4
SR+
SR−
3
VDD = 2.7 V
AV = 1
RL= 2 kΩ
CL = 10 pF
VO = 1 VPP
VIC = VDD/2
2
1
0
−40 −25 −10 5 20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
Figure 17
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
100
Hz
140
90
V n − Equivalent Input Noise Voltage − nV/
PHASE MARGIN
vs
LOAD CAPACITANCE
120
TA = 25°C
Rnull=50 Ω
60
50
40
Rnull=20 Ω
30
VDD = 2.7 V
RL = 2 kΩ
AV = 1
TA = 25°C
20
10
Rnull=0 Ω
0
10
100
1k
10 k
VDD = 2.7 V
100
80
60
40
20
VDD = 1.8 V
0
10
100
Figure 18
1.5
1
V O − Output Voltage − V
VI
0.5
2.5
VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE
vs
TIME
VI
1.40
1.35
1.30
V O − Output Voltage − V
2
VO
1.25
1.40
2
VO
1
0.5
0
0
VDD = 2.7 V
RL = 2 kΩ
CL = 10 pF
AV = 1
TA = 25°C
0.2 0.4 0.6 0.8
VDD = 2.7 V
RL = 2 kΩ
CL = 10 pF
AV = 1
TA = 25°C
1.35
1.30
1.25
0
1 1.2 1.4 1.6 1.8
0.2
Figure 20
−0.5
−1
1.5
1
VO
1
1.2
1.4
VDD = 2.7 V
RL = 2 kΩ
CL = 10 pF
AV = −1
TA = 25°C
0.10
0.05
0
VI
−0.05
V O − Output Voltage − V
0.5
0
2
0.8
INVERTING SMALL-SIGNAL PULSE RESPONSE
vs
TIME
V I − Input Voltage − V
1
2.5
0.6
Figure 21
INVERTING LARGE-SIGNAL PULSE RESPONSE
vs
TIME
VI
0.4
t − Time − µs
t − Time − µs
V O − Output Voltage − V
100 k
1.45
V I − Input Voltage − V
2.5
0.5
10 k
Figure 19
VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE
vs
TIME
1.5
1k
f − Frequency − Hz
CL − Load Capacitance − pF
V I − Input Voltage − V
70
0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3
t − Time − µs
VDD = 2.7 V
RL = 2 kΩ
CL = 10 pF
AV = −1
TA = 25°C
1.40
1.35
1.30
V I − Input Voltage − V
φ m − Phase Margin − °
80
VO
1.25
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
t − Time − µs
Figure 22
Figure 23
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11
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
TYPICAL CHARACTERISTICS
SHUTDOWN FORWARD
AND REVERSE ISOLATION
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
Crosstalk − dB
−40
VDD = 1.8 V & 2.7 V
VIC = 60% of VDD
AV = 1
RL= 2 kΩ
TA = 25°C
All Channels
−80
−100
−120
120
I DD − Shutdown Supply Current − µ A
Shutdown Forward Isolation - dB
Crosstalk in Shutdown
−60
3
140
0
−20
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
Forward and Reverse Isolation
100
80
60
VDD = 1.8 & 2.7 V
VIC = VDD /2
RL = 2 kΩ
CL= 10 pF
AV = 1
TA = 25°C
40
20
Crosstalk/No Shutdown
0
−140
10
100
1k
10 k
f − Frequency − Hz
100 k
10
100
1k
10 k
100 k
1M
10 M
2.5
Shutdown = 0V
VIC = VDD/2
AV = 1
2.0
1.5
VDD= 3.6 V
1
VDD = 2.7 V
0.5
VDD = 1.8 V
0
−40 −25 −10 5 20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
f − Frequency − Hz
Figure 24
Figure 25
Figure 26
SHUTDOWN SUPPLY CURRENT / OUTPUT VOLTAGE
vs
TIME
Shutdown = 0 V
VIC = VDD/2
AV = 1
2.4
I DD − Supply Current − µ A
2.2
2
1.8
TA = 125°C
1.6
1.4
TA = −40°C
1.2
1
0.8
0.6
0.4
TA = 25°C
0.2
SD − Shutdown Pulse − V
2.6
V O − Output Voltage − mV
SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
3.0
2.5
2.0
1.5
1.0
0.5
0.0
SD
1.5
1.3
1.0
0.8
0.5
0.3
0.0
VO
0
0.4 0.8 1.2 1.6
2
2.4 2.8
VDD − Supply Voltage − V
Figure 27
3.2 3.6
I DD(SD) − Shutdown Current − µ A
0
1.8
1.5
1.3
1.0
0.8
0.5
0.3
0.0
−1
VDD = 2.7 V
AV = 1
RL = 10 kΩ
CL = 10 pF
VIC = VDD/2
TA = 25° C
IDD(SD)
0
1
2
3
4
5
Figure 28
12
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6
t − Time − µsec
7
8
9
10
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
PARAMETER MEASUREMENT INFORMATION
RNULL
_
+
RL
CL
Figure 29
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as
shown in Figure 30.
RF
RG
−
Input
RF
RG
RNULL
Output
+
RL
RNULL
−
Input
Output
+
Snubber
CL
RL
CL
C
(a)
(b)
Figure 30. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
IIB−
RG
+
−
VI
RS
IIB+
V
OO
+V
IO
ǒ ǒ ǓǓ
1)
R
R
F
G
VO
+
"I
IB)
R
S
ǒ ǒ ǓǓ
1)
R
R
F
G
"I
IB–
R
F
Figure 31. Output Offset Voltage Model
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13
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 32).
RG
RF
−
VO
+
VI
R1
C1
f
V
O +
V
I
ǒ
1)
R
R
F
G
+
–3dB
Ǔǒ
1
2pR1C1
Ǔ
1
1 ) 2pfR1C1
Figure 32. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
RG =
Figure 33. 2-Pole Low-Pass Sallen-Key Filter
14
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–3dB
+
(
1
2pRC
RF
1
2−
Q
)
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV278x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D Ground planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
D Short trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
D Surface-mount passive components − Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
shutdown function
Three members of the TLV278x family (TLV2780/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 900 nA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown.
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15
! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 34 and is calculated by the following formula:
P
D
+
Where:
ǒ
T
Ǔ
–T
MAX A
q
JA
PD = Maximum power dissipation of TLV278x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
Maximum Power Dissipation − W
1.75
PDIP Package
Low-K Test PCB
θJA = 104°C/W
1.5
1.25
TJ = 150°C
MSOP Package
Low-K Test PCB
θJA = 260°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
1
0.75
0.5
0.25
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
0
−55 −40 −25 −10 5
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 34. Maximum Power Dissipation vs Free-Air Temperature
16
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! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 9.1, the model generation
software used with Microsim PSpice . The Boyle macromodel (see Note 2) and subcircuit in Figure 35 are
generated using TLV278x typical electrical and operating characteristics at TA = 25°C. Using this information,
output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing
D Unity-gain frequency
D Maximum negative output voltage swing
D Common-mode rejection ratio
D Slew rate
D Phase margin
D Quiescent power dissipation
D DC output resistance
D Input bias current
D AC output resistance
D Open-loop voltage amplification
D Short-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
3
99
VDD
+
egnd
rd1
rd2
rss
ro2
css
fb
rp
−
c1
7
11
12
+
c2
vlim
1
+
r2
9
6
IN+
−
vc
D
D
8
+
−
vb
ga
2
G
G
−
IN−
ro1
gcm
ioff
53
S
S
OUT
dp
91
10
iss
GND
4
+
dc
−
dlp
ve
+ 54
vlp
−
90
dln
+
hlim
−
5
92
−
vln
+
de
* TLV2782_HVDD operational amplifier ”macromodel” subcircuit
* created using Model Editor release 9.1 on 03/3/00 at 9:47
* Model Editor is an OrCAD product.
*
* connections: non−inverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
| | | | |
.subckt TLV2782_HVDD
12345
*
c1
11
12
49.58E−15
c2
6
7
10.200E−12
css
10
99
1.0000E−30
dc
5
53
dy
de
54
5
dy
dlp
90
91
dx
dln
92
90
dx
dp
4
3
dx
egnd
99
0
poly(2) (3,0) (4,0) 0 .5 .5
fb
7
99
poly(5) vb vc ve vlp vln 0
41.096E6 −1E3 1E3 41E6
−41E6
ga
gcm
iss
hlim
j1
J2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
6
0
10
90
11
12
6
3
3
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
jx2
0
11 12 544.75E−6
6
10 99 1.1538E−9
4
dc 56.957E−6
0
vlim 1K
2
10 jx1
1
10 jx2
9
100.00E3
11
1.8357E3
12
1.8357E3
5
10
99
10
4
2.1845E3
99
3.5114E6
0
dc 0
53
dc .81911
4
dc .81911
8
dc 0
0
dc 45.400
92
dc 45.400
D(Is=800.00E−18)
D(Is=800.00E−18 Rs=1m Cjo=10p)
NJF(Is=500.00E−15 Beta=5.2102E−3 Vto=−1)
NJF(Is=500.00E−15 Beta=5.2102E−3 Vto=−1)
Figure 35. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
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17
PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2780CDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VASC
TLV2780CDBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VASC
TLV2780CDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VASC
TLV2780CDBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VASC
TLV2780IDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VASI
TLV2780IDBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VASI
TLV2780IDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VASI
TLV2780IDBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VASI
TLV2780IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T2780I
TLV2780IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T2780I
TLV2781CDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VATC
TLV2781CDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VATC
TLV2781CDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VATC
TLV2781CDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VATC
TLV2781ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T2781I
TLV2781IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VATI
TLV2781IDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VATI
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2781IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VATI
TLV2781IDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VATI
TLV2781IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T2781I
TLV2781IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T2781I
TLV2781IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T2781I
TLV2782AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2782AI
TLV2782AIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2782AI
TLV2782CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2782C
TLV2782CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2782C
TLV2782CDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
0 to 70
ADL
TLV2782CDGKG4
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ADL
TLV2782CDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
0 to 70
ADL
TLV2782CDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ADL
TLV2782CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2782C
TLV2782CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2782C
TLV2782ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2782I
TLV2782IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2782I
TLV2782IDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
ADM
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2782IDGKG4
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
ADM
TLV2782IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
ADM
TLV2782IDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
ADM
TLV2782IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2782I
TLV2782IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2782I
TLV2782IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2782IP
TLV2782IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2782IP
TLV2783CDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV2783C
TLV2783CDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV2783C
TLV2783ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2783I
TLV2783IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2783I
TLV2783IDGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
ADO
TLV2783IDGSG4
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
ADO
TLV2783IDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
ADO
TLV2783IDGSRG4
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
ADO
TLV2783IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2783I
TLV2783INE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2783I
TLV2784AID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2784AI
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2784AIDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2784AI
TLV2784AIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2784AI
TLV2784AIDRG4
ACTIVE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 125
TLV2784CPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2784C
TLV2784CPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2784C
TLV2784ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2784I
TLV2784IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2784I
TLV2784IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2784I
TLV2784IDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2784I
TLV2784IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2784I
TLV2784IPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2784I
TLV2784IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2784I
TLV2784IPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2784I
TLV2785AID
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2785AI
TLV2785AIDG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2785AI
TLV2785CPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2785C
TLV2785CPWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2785C
TLV2785IDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Addendum-Page 4
TLV2785I
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2785IDRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2785I
TLV2785IN
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2785I
TLV2785INE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2785I
TLV2785IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2785I
TLV2785IPWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2785I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 5
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 6
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TLV2780CDBVR
SOT-23
DBV
6
3000
180.0
9.0
TLV2780CDBVT
SOT-23
DBV
6
250
180.0
TLV2780IDBVR
SOT-23
DBV
6
3000
180.0
TLV2780IDBVT
SOT-23
DBV
6
250
TLV2780IDR
SOIC
D
8
TLV2781CDBVR
SOT-23
DBV
TLV2781CDBVT
SOT-23
DBV
TLV2781IDBVR
SOT-23
TLV2781IDBVT
TLV2781IDR
3.15
3.2
1.4
4.0
8.0
Q3
9.0
3.15
3.2
1.4
4.0
8.0
Q3
9.0
3.15
3.2
1.4
4.0
8.0
Q3
180.0
9.0
3.15
3.2
1.4
4.0
8.0
Q3
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
5
3000
180.0
9.0
3.15
3.2
1.4
4.0
8.0
Q3
5
250
180.0
9.0
3.15
3.2
1.4
4.0
8.0
Q3
DBV
5
3000
180.0
9.0
3.15
3.2
1.4
4.0
8.0
Q3
SOT-23
DBV
5
250
180.0
9.0
3.15
3.2
1.4
4.0
8.0
Q3
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2782CDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2782CDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2782CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2782IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2782IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2782IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2783CDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLV2783IDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLV2784AIDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLV2784CPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLV2784IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLV2784IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLV2785CPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLV2785IDR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TLV2785IPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV2780CDBVR
SOT-23
DBV
6
3000
182.0
182.0
20.0
TLV2780CDBVT
SOT-23
DBV
6
250
182.0
182.0
20.0
TLV2780IDBVR
SOT-23
DBV
6
3000
182.0
182.0
20.0
TLV2780IDBVT
SOT-23
DBV
6
250
182.0
182.0
20.0
TLV2780IDR
SOIC
D
8
2500
367.0
367.0
35.0
TLV2781CDBVR
SOT-23
DBV
5
3000
182.0
182.0
20.0
TLV2781CDBVT
SOT-23
DBV
5
250
182.0
182.0
20.0
TLV2781IDBVR
SOT-23
DBV
5
3000
182.0
182.0
20.0
TLV2781IDBVT
SOT-23
DBV
5
250
182.0
182.0
20.0
TLV2781IDR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV2782CDGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
TLV2782CDGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
TLV2782CDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2782IDGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
TLV2782IDGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
TLV2782IDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2783CDR
SOIC
D
14
2500
367.0
367.0
38.0
TLV2783IDGSR
VSSOP
DGS
10
2500
358.0
335.0
35.0
TLV2784AIDR
SOIC
D
14
2500
367.0
367.0
38.0
TLV2784CPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TLV2784IDR
SOIC
D
14
2500
367.0
367.0
38.0
TLV2784IPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TLV2785CPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
TLV2785IDR
SOIC
D
16
2500
367.0
367.0
38.0
TLV2785IPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 3
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