TMS320C30GEL40

TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 D D D D D D D High-Performance Floating-Point Digital Signal Processor (DSP) – TMS320C30-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS – TMS320C30-40 (5 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS – TMS320C30-33 (5 V) 60-ns Instruction Cycle Time 183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS – TMS320C30-27 (5 V) 74-ns Instruction Cycle Time 148.5 MOPS, 27 MFLOPS, 13.5 MIPS 32-Bit High-Performance CPU 16- / 32-Bit Integer and 32- / 40-Bit Floating-Point Operations 32-Bit Instruction Word, 24-Bit Addresses Two 1K × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks One 4K × 32-Bit Single-Cycle Dual-Access On-Chip ROM Block On-Chip Memory-Mapped Peripherals: – Two Serial Ports – Two 32-Bit Timers – One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation D D D D D D D D D D D D D D D Two 32-Bit External Ports 24- and 13-Bit Addresses 0.7-µm Enhanced Performance Implanted CMOS (EPIC) Technology 208-Pin Plastic Quad Flat Package ( PPM Suffix ) 181-Pin Grid Array Ceramic Package (GEL Suffix) Eight Extended-Precision Registers Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Two- and Three-Operand Instructions Parallel Arithmetic and Logic Unit (ALU) and Multiplier Execution in a Single Cycle Block-Repeat Capability Zero-Overhead Loops With Single-Cycle Branches Conditional Calls and Returns Interlocked Instructions for Multiprocessing Support Two Sets of Memory Strobes (STRB and MSTRB) and One I / O Strobe (IOSTRB) Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation description The TMS320C30 is the newest member of the TMS320C3x generation of DSPs from Texas Instruments (TI). The TMS320C30 is a 32-bit floating-point processor manufactured in 0.7-µm triple-level-metal CMOS technology. The TMS320C30’s internal busing and special DSP instruction set have the speed and flexibility to execute up to 50 MFLOPS (million floating-point operations per second). The TMS320C30 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. The TMS320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I / O, and a short machine-cycle time. High performance and ease of use are results of these features. General-purpose applications are enhanced greatly by the large address space, multiprocessor interface, internally and externally generated wait states, two external interface ports, two timers, serial ports, and multiple interrupt structure. The TMS320C30 supports a wide variety of system applications from host processor to dedicated coprocessor. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and TI are trademarks of Texas Instruments Incorporated. Copyright  1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 description (continued) High-level language support is implemented easily through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic. pinout and pin assignments TMS320C30 GEL pinout and pin assignments The TMS320C30 digital signal processor is available in a 181-pin grid array (PGA) package. The pinout of this package is shown in the following two illustrations. The pin assignments are listed in the TMS320C30 GEL pin assignments (alphabetical) table and the TMS320C30 GEL pin assignments (numerical) table. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 H3 D2 D3 D7 D10 D13 D16 D17 D19 D22 D25 D28 XA0 XA1 XA5 H1 D4 D8 D11 D15 D18 D20 D24 D27 D31 XA4 IVSS XA6 A X2/CLKIN CVSS B EMU5 X1 DVSS D0 D5 D9 D14 VSS D21 D26 D30 XA3 DVSS XA7 XA10 XR/W XRDY VBBP DDVDD D1 D6 D12 VDD D23 D29 XA2 ADVDD XA9 XA11 MC/MP XA8 XA12 EMU3 EMU1 EMU4/SHZ EMU2 EMU0 A0 C D RDY HOLDA MSTRB VSUBS LOCATOR DDVDD E RESET STRB HOLD IOSTRB IACK XF0 XF1 R/W INT1 INT0 VSS VDD INT2 INT3 RSV0 RSV2 RSV3 RSV4 F A1 A2 A3 A4 VDD VSS A6 A5 RSV1 A11 A9 A8 A7 RSV5 RSV7 A17 A14 A12 A10 RSV6 RSV9 CLKR1 A22 A18 A15 A13 RSV8 RSV10 FSR1 PDVDD CLKX0 DR1 CLKX1 DVSS CLKR0 FSX1 DX1 FSR0 DR0 FSX0 DX0 G TMS320C30 Top View MDVDD H ADVDD J K IODVDD L EMU6 XD5 VDD XD16 XD22 XD27 IODVDD A21 A19 A16 TCLK1 XD2 XD7 VSS XD14 XD19 XD23 XD28 DVSS A23 A20 TCLK0 XD1 XD4 XD8 XD10 XD13 XD17 XD20 XD24 XD29 CVSS XD31 XD0 XD3 XD6 XD9 XD11 XD12 XD15 XD18 XD21 XD25 XD26 XD30 M N P R TMS320C30 GEL Pinout (Top View) 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 TMS320C30 GEL pinout and pin assignments (continued) 15 XA5 14 XA1 13 12 11 10 9 8 7 6 5 4 3 2 1 XA0 D28 D25 D22 D19 D17 D16 D13 D10 D7 D3 D2 H3 A XA6 IVSS XA4 D31 D27 D24 D20 D18 D15 D11 D8 D4 H1 XA10 XA7 DVSS XA3 D30 D26 D21 VSS D14 D9 D5 D0 DVSS X1 EMU5 MC/MP XA11 XA9 ADVDD XA2 D29 D23 VDD D12 D6 D1 DDVDD VBBP XRDY XR/W CVSS X2/CLKIN B C D EMU1 EMU3 XA12 XA8 A0 EMU0 EMU2 EMU4/SHZ DDVDD LOCATOR VSUBS MSTRB HOLDA RDY E IOSTRB HOLD STRB RESET F A4 A3 A2 A1 A5 A6 VSS VDD R/W XF1 XF0 IACK VDD VSS INT0 INT1 G TMS320C30 Bottom View ADVDD MDVDD H A7 A8 A9 A11 RSV1 RSV0 INT3 INT2 A10 A12 A14 A17 RSV7 RSV5 RSV3 RSV2 A13 A15 A18 A22 CLKR1 RSV9 RSV6 RSV4 A16 A19 A21 IODVDD CLKX0 PDVDD FSR1 RSV10 RSV8 J K IODVDD L XD27 XD22 XD16 VDD XD5 EMU6 M A20 A23 DVSS XD28 XD23 XD19 XD14 VSS XD7 XD2 TCLK1 CLKR0 DVSS CLKX1 DR1 XD31 CVSS XD29 XD24 XD20 XD17 XD13 XD10 XD8 XD4 XD1 TCLK0 FSR0 DX1 FSX1 N P XD30 XD26 XD25 XD21 XD18 XD15 XD12 XD11 XD9 XD6 XD3 XD0 DX0 FSX0 DR0 R TMS320C30 GEL Pinout (Bottom View) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 TMS320C30 GEL Pin Assignments (Alphabetical)† PIN NAME PIN NO. NAME PIN NO. NAME PIN NO. A0 A1 A2 A3 A4 F15 G12 G13 G14 G15 D8 D9 D10 D11 D12 B5 C6 A5 B6 D7 EMU6 FSR0 FSR1 FSX0 FSX1 M6 P3 M3 R2 P1 A5 A6 A7 A8 A9 H15 H14 J15 J14 J13 D13 D14 D15 D16 D17 A6 C7 B7 A7 A8 H1 H3 HOLD HOLDA IACK B3 A1 F3 E2 G1 A10 A11 A12 A13 A14 K15 J12 K14 L15 K13 D18 D19 D20 D21 D22 B8 A9 B9 C9 A10 INT0 INT1 INT2 INT3 IODVDD A15 A16 A17 A18 A19 L14 M15 K12 L13 M14 D23 D24 D25 D26 D27 D9 B10 A11 C10 B11 A20 A21 A22 A23 ADVDD N15 M13 L12 N14 D12 D28 D29 D30 D31 DDVDD ADVDD CLKR0 CLKR1 CLKX0 CLKX1 H11 N4 L4 M5 N2 CVSS CVSS D0 D1 D2 B2 P14 C4 D5 A2 DDVDD DR0 DR1 DVSS DVSS DVSS DVSS DX0 DX1 EMU0 NAME PIN NO. NAME NO. D3 D8 H4 H12 M8 XD15 XD16 XD17 XD18 XD19 R10 M9 P10 R11 N10 C8 H3 H13 N8 E4 XD20 XD21 XD22 XD23 XD24 P11 R12 M10 N11 P12 H2 H1 J1 J2 L8 VBBP VDD VDD VDD VDD VSS VSS VSS VSS VSUBS X1 X2/CLKIN XA0 XA1 XA2 C2 B1 A13 A14 D11 XD25 XD26 XD27 XD28 XD29 R13 R14 M11 N12 P13 IODVDD IOSTRB IVSS LOCATOR MC/MP M12 F4 B14 E5 D15 XA3 XA4 XA5 XA6 XA7 C12 B13 A15 B15 C14 XD30 XD31 XF0 XF1 XRDY R15 P15 G2 G3 D2 A12 D10 C11 B12 D4 MDVDD MSTRB PDVDD RDY RESET H5 E3 M4 E1 F1 XA8 XA9 XA10 XA11 XA12 E12 D13 C15 D14 E13 XR/W D1 E8 R1 N1 C3 C13 RSV0 RSV1 RSV2 RSV3 RSV4 J3 J4 K1 K2 L1 XD0 XD1 XD2 XD3 XD4 R4 P5 N6 R5 P6 N3 N13 R3 P2 F14 RSV5 RSV6 RSV7 RSV8 RSV9 K3 L2 K4 M1 L3 XD5 XD6 XD7 XD8 XD9 M7 R6 N7 P7 R7 D3 A3 EMU1 E15 RSV10 M2 XD10 P8 D4 B4 EMU2 F13 R/W G4 XD11 R8 STRB D5 C5 EMU3 E14 F2 XD12 R9 D6 D6 EMU4/SHZ F12 P4 XD13 P9 TCLK0 D7 A4 C1 N5 XD14 N9 TCLK1 EMU5 † ADVDD, CVSS, DDVDD, DVSS, IODVDD, IVSS, MDVDD, PDVDD, VDD, and VSS pins are on a common plane internal to the device. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 TMS320C30 GEL Pin Assignments (Numerical)† PIN NAME PIN NO. NAME PIN NO. NAME PIN NO. H3 D2 D3 D7 D10 A1 A2 A3 A4 A5 D30 XA3 DVSS XA7 XA10 C11 C12 C13 C14 C15 XF1 R/W A1 A2 A3 G3 G4 G12 G13 G14 D13 D16 D17 D19 D22 A6 A7 A8 A9 A10 XR/W XRDY VBBP DDVDD D1 D1 D2 D3 D4 D5 D25 D28 XA0 XA1 XA5 A11 A12 A13 A14 A15 D6 D12 VDD D23 D29 D6 D7 D8 D9 D10 A4 INT1 INT0 VSS VDD MDVDD ADVDD VDD VSS A6 X2/CLKIN CVSS H1 D4 D8 B1 B2 B3 B4 B5 XA2 ADVDD XA9 XA11 MC/MP D11 D12 D13 D14 D15 D11 D15 D18 D20 D24 B6 B7 B8 B9 B10 RDY HOLDA MSTRB VSUBS LOCATOR D27 D31 XA4 IVSS XA6 B11 B12 B13 B14 B15 EMU5 X1 DVSS D0 D5 C1 C2 C3 C4 C5 NAME PIN NO. L15 M1 M2 M3 M4 G15 H1 H2 H3 H4 A13 RSV8 RSV10 FSR1 PDVDD CLKX0 EMU6 XD5 VDD XD16 H5 H11 H12 H13 H14 A5 INT2 INT3 RSV0 RSV1 E1 E2 E3 E4 E5 DDVDD XA8 XA12 EMU3 EMU1 RESET STRB HOLD IOSTRB EMU4/SHZ NAME NO. P10 P11 P12 P13 P14 M5 M6 M7 M8 M9 XD17 XD20 XD24 XD29 CVSS XD31 DR0 FSX0 DX0 XD0 XD22 XD27 IODVDD A21 A19 M10 M11 M12 M13 M14 XD3 XD6 XD9 XD11 XD12 R5 R6 R7 R8 R9 H15 J1 J2 J3 J4 A16 DR1 CLKX1 DVSS CLKR0 M15 N1 N2 N3 N4 XD15 XD18 XD21 XD25 XD26 R10 R11 R12 R13 R14 A11 A9 A8 A7 RSV2 J12 J13 J14 J15 K1 TCLK1 XD2 XD7 VSS XD14 N5 N6 N7 N8 N9 XD30 R15 E8 E12 E13 E14 E15 RSV3 RSV5 RSV7 A17 A14 K2 K3 K4 K12 K13 XD19 XD23 XD28 DVSS A23 N10 N11 N12 N13 N14 F1 F2 F3 F4 F12 A12 A10 RSV4 RSV6 RSV9 K14 K15 L1 L2 L3 A20 FSX1 DX1 FSR0 TCLK0 N15 P1 P2 P3 P4 P15 R1 R2 R3 R4 D9 C6 EMU2 F13 CLKR1 L4 XD1 P5 D14 C7 EMU0 F14 IODVDD L8 XD4 P6 A22 VSS C8 A0 F15 L12 XD8 P7 A18 D21 C9 IACK G1 L13 XD10 P8 A15 D26 C10 G2 L14 XD13 P9 XF0 † ADVDD, CVSS, DDVDD, DVSS, IODVDD, IVSS, MDVDD, PDVDD, VDD, and VSS pins are on a common plane internal to the device. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 TMS320C30 PPM pinout and pin assignments NC IODV DD IODV DD XD30 XD29 XD28 XD27 XD26 XD25 XD24 XD23 XD22 XD21 XD20 XD19 XD18 XD17 XD16 XD15 XD14 XD13 XD12 XD11 VSS VSS DVSS VDD VDD XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 IODV DD IODV DD XD2 XD1 XD0 EMU6 TCLK1 TCLK0 DX0 FSX0 CLKX0 CLKR0 FSR0 DR0 PDV DD PDV DD The TMS320C30 PPM device is packaged in a 208-pin plastic quad flatpack (PQFP) JEDEC standard package. The following illustration shows the pinout for this package. The pin assignments are listed in the TMS320C30 PPM pin assignments (alphabetical) table and the TMS320C30 PPM pin assignments (numerical) table. 53 104 VSS DVSS CVSS CVSS XD31 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 ADVDD ADVDD A13 A12 A11 A10 A9 A8 A7 A6 VDD VDD DVSS CVSS A5 A4 A3 A2 A1 A0 EMU0 EMU1 EMU2 EMU3 EMU4 / SHZ MC/MP XA12 XA11 XA10 XA9 XA8 XA7 XA6 IVSS IVSS DVSS VSS 105 52 156 1 208 ADVDD ADVDD XA5 XA4 XA3 XA2 XA1 XA0 D31 D30 D29 D28 D27 D26 DDVDD DDVDD D25 D24 D23 D22 D21 D20 D19 D18 V DD V DD CVSS DV SS V SS D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 H1 H3 DDV DD DDV DD NC 157 TMS320C30 PPM Pinout 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 CVSS DVSS DX1 FSX1 CLKX1 CLKR1 FSR1 DR1 RSV10 RSV9 RSV8 RSV7 RSV6 RSV5 RSV4 RSV3 RSV2 RSV1 RSV0 INT3 INT2 INT1 VSS VSS NC VDD VDD INT0 IACK XF0 XF1 RESET R/W STRB RDY MDVDD MDVDD HOLD HOLDA XR/W IOSTRB MSTRB XRDY EMU5 NC VSUBS X1 X2 / CLKIN CVSS CVSS DVSS VSS TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 TMS320C30 PPM Pin Assignments (Alphabetical)† PIN NAME PIN NO. A0 139 A1 138 A2 137 A3 136 A4 A5 NAME PIN NO. NAME PIN NO. NAME PIN NO. NAME PIN NO. NAME NO. CVSS CVSS 107 D31 165 INT2 32 TCLK1 62 XD2 66 108 DDVDD 171 INT3 33 26 XD3 69 CVSS CVSS 133 DDVDD 172 67 27 XD4 70 183 DDVDD 206 IODVDD IODVDD VDD VDD 77 XD5 71 135 D0 203 DDVDD 207 102 78 XD6 72 134 D1 202 DR0 55 XD7 73 129 D2 201 DR1 45 VDD VDD 130 A6 IODVDD IODVDD IOSTRB VDD VDD 131 XD8 74 A7 128 D3 200 XD9 75 199 VDD VDD 181 D4 182 XD10 76 A9 126 D5 198 105 XD11 82 125 D6 197 16 29 XD12 83 A11 124 D7 196 132 MDVDD MDVDD VSS VSS VSS 1 A10 DVSS DVSS DVSS IVSS IVSS MC/MP 153 127 DVSS DVSS 2 A8 30 XD13 84 A12 123 D8 195 MSTRB 11 XD14 85 D9 194 156 NC 8 81 XD15 86 A14 119 D10 193 184 NC 28 105 XD16 87 A15 118 D11 192 DVSS DX0 VSS VSS VSS 80 122 DVSS DVSS 155 A13 60 NC 104 156 XD17 88 A16 117 D12 191 DX1 50 NC 208 VSS VSS 185 XD18 89 A17 116 D13 190 EMU0 140 XD19 90 D14 189 EMU1 141 54 VSUBS X1 7 115 PDVDD PDVDD 53 A18 6 XD20 91 A19 114 D15 188 EMU2 142 RDY 18 X2/CLKIN 5 XD21 92 A20 113 D16 187 EMU3 143 RESET 21 XA0 164 XD22 93 A21 112 D17 186 EMU4/SHZ 144 RSV0 34 XA1 163 XD23 94 A22 111 D18 180 EMU5 9 RSV1 35 XA2 162 XD24 95 A23 110 D19 179 EMU6 63 RSV2 36 XA3 161 XD25 96 ADVDD ADVDD 120 D20 178 FSR0 56 RSV3 37 XA4 160 XD26 97 121 D21 177 FSR1 46 RSV4 38 XA5 159 XD27 98 ADVDD ADVDD 157 D22 176 FSX0 59 RSV5 39 XA6 152 XD28 99 158 D23 175 FSX1 49 RSV6 40 XA7 151 XD29 100 CLKR0 57 D24 174 H1 204 RSV7 41 XA8 150 XD30 101 CLKR1 47 D25 173 H3 205 RSV8 42 XA9 148 XD31 109 CLKX0 58 D26 170 HOLD 15 RSV9 43 XA10 149 XF0 23 CLKX1 48 D27 169 HOLDA 14 RSV10 44 XA11 147 XF1 22 CVSS 3 D28 168 IACK 24 R/W 20 XA12 146 XRDY 10 CVSS 4 D29 167 INT0 25 STRB 19 XD0 64 XR/W 13 51 106 68 103 12 154 145 17 CVSS 52 D30 166 INT1 31 TCLK0 61 XD1 65 † ADVDD, CVSS, DDVDD, DVSS, IODVDD, IVSS, MDVDD, PDVDD, VDD, and VSS pins are on a common plane internal to the device. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 TMS320C30 PPM Pin Assignments (Numerical)† PIN NO. 1 NAME PIN NO. PIN NAME NO. NAME PIN NO. NAME PIN NO. NAME 43 RSV9 85 XD14 127 A8 169 D27 2 VSS DVSS 44 RSV10 86 XD15 128 A7 170 D26 3 CVSS 45 DR1 87 XD16 129 A6 171 DDVDD 4 CVSS 46 FSR1 88 XD17 130 172 DDVDD 5 X2 / CLKIN 47 CLKR1 89 XD18 131 VDD VDD 173 D25 6 X1 48 CLKX1 90 XD19 132 DVSS 174 D24 7 49 FSX1 91 XD20 133 CVSS 175 D23 8 VSUBS NC 50 DX1 92 XD21 134 A5 176 D22 9 EMU5 51 93 XD22 135 A4 177 D21 10 XRDY 52 DVSS CVSS 94 XD23 136 A3 178 D20 11 MSTRB 53 95 XD24 137 A2 179 D19 12 IOSTRB 54 PDVDD PDVDD 96 XD25 138 A1 180 D18 13 XR/W 55 DR0 97 XD26 139 A0 181 14 HOLDA 56 FSR0 98 XD27 140 EMU0 182 VDD VDD 15 HOLD 57 CLKR0 99 XD28 141 EMU1 183 CVSS 16 58 CLKX0 100 XD29 142 EMU2 184 DVSS 17 MDVDD MDVDD 59 FSX0 101 XD30 143 EMU3 185 18 RDY 60 DX0 102 144 EMU4/SHZ 186 19 STRB 61 TCLK0 103 IODVDD IODVDD VSS D17 145 MC/MP 187 D16 20 R/W 62 TCLK1 104 NC 146 XA12 188 D15 21 RESET 63 EMU6 105 XA11 189 D14 XF1 64 XD0 106 VSS DVSS 147 22 148 XA10 190 D13 23 XF0 65 XD1 107 CVSS 149 XA9 191 D12 24 IACK 66 XD2 108 CVSS 150 XA8 192 D11 25 INT0 67 109 XD31 151 XA7 193 D10 26 68 110 A23 152 XA6 194 D9 27 VDD VDD IODVDD IODVDD 69 XD3 111 A22 153 195 D8 28 NC 70 XD4 112 A21 154 IVSS IVSS 196 D7 29 71 XD5 113 A20 155 DVSS 197 D6 30 VSS VSS 72 XD6 114 A19 156 198 D5 31 INT1 73 XD7 115 A18 157 VSS ADVDD 199 D4 32 INT2 74 XD8 116 A17 158 200 D3 33 INT3 75 XD9 117 A16 159 ADVDD XA5 201 D2 34 RSV0 76 XD10 118 A15 160 XA4 202 D1 35 RSV1 77 119 A14 161 XA3 203 D0 36 RSV2 78 VDD VDD 120 37 RSV3 79 38 RSV4 80 39 RSV5 81 40 RSV6 41 42 XA2 204 H1 121 ADVDD ADVDD 162 DVSS VSS 163 XA1 205 H3 122 A13 164 XA0 206 DDVDD VSS XD11 123 A12 165 D31 207 DDVDD 82 124 A11 166 D30 208 NC RSV7 83 XD12 125 A10 167 D29 RSV8 84 XD13 126 A9 168 D28 † ADVDD, CVSS, DDVDD, DVSS, IODVDD, IVSS, MDVDD, PDVDD, VDD, and VSS pins are on a common plane internal to the device. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 pin functions This section provides signal descriptions for the TMS320C30 in the microprocessor mode. The following tables list each signal, the number of pins, type of operating mode(s) (that is, input, output, or high-impedance state as indicated by I, O, or Z), and a brief description of its function. All pins labeled NC have special functions and should not be connected by the user. A line over a signal name (for example, RESET) indicates that the signal is active low (true at logic 0 level). The signals are grouped according to function. TMS320C30 Pin Functions PIN NAME QTY‡ TYPE† DESCRIPTION CONDITIONS WHEN SIGNAL IS Z TYPE§ PRIMARY BUS INTERFACE D31 – D0 32 I/O/Z 32-bit data port of the primary bus interface S H R A23 – A0 24 O/Z 24-bit address port of the primary bus interface S H R S H R S H R/W 1 O/Z Read / write for primary bus interface. R / W is high when a read is performed and low when a write is performed over the parallel interface. STRB 1 O/Z External access strobe for the primary bus interface RDY 1 I Ready. RDY indicates that the external device is prepared for a primary-bus-interface transaction to complete. I Hold for primary bus interface. When HOLD is a logic low, any ongoing transaction is completed. A23 – A0, D31 – D0, STRB, and R / W are in the high-impedance state and all transactions over the primary bus interface are held until HOLD becomes a logic high or the NOHOLD bit of the primary-bus-control register is set. O/Z Hold acknowledge for primary bus interface. HOLDA is generated in response to a logic low on HOLD. HOLDA indicates that A23 – A0, D31 – D0, STRB, and R / W are in the high-impedance state and that all transactions over the bus are held. HOLDA is high in response to a logic high of HOLD or when the NOHOLD bit of the primary-bus-control register is set. HOLD HOLDA 1 1 S EXPANSION BUS INTERFACE XD31 – XD0 32 I/O/Z 32-bit data port of the expansion bus interface S R XA12 – XA0 13 O/Z 13-bit address port of the expansion bus interface S R S R XR / W 1 O/Z Read / write signal for expansion bus interface. When a read is performed, XR / W is held high; when a write is performed, XR / W is low. MSTRB 1 O/Z External memory access strobe for the expansion bus interface S IOSTRB 1 O/Z External I / O access strobe for the expansion bus interface S XRDY 1 I Ready signal. XRDY indicates that the external device is prepared for an expansionbus-interface transaction to complete. CONTROL SIGNALS RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector. INT3 – INT0 4 I External interrupts IACK 1 O/Z MC / MP 1 I XF1, XF0 2 I/O/Z Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used to indicate the beginning or end of an interrupt-service routine. S Microcomputer / microprocessor mode External flags. XF1 and XF0 are used as general-purpose I / Os or to support interlocked processor instructions. S R † I = input, O = output, Z = high-impedance state. All pins labeled NC have specified functions and should not be connected by the user. ‡ Quantity is the same for GEL and PPM packages unless otherwise noted. § S = SHZ active, H = HOLD active, R = RESET active POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 TMS320C30 Pin Functions (Continued) PIN TYPE† QTY‡ NAME DESCRIPTION CONDITIONS WHEN SIGNAL IS Z TYPE§ SERIAL PORT 0 SIGNALS CLKX0 1 I/O/Z Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0 transmitter. S R DX0 1 I/O/Z Data transmit output. Serial port 0 transmits serial data on DX0. S R S R FSX0 1 I/O/Z Frame synchronization pulse for transmit. The FSX0 pulse initiates the transmit data process over DX0. CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver. S R DR0 1 I/O/Z Data receive. Serial port 0 receives serial data on DR0. S R I/O/Z Frame synchronization pulse for receive. The FSR0 pulse initiates the receive data process over DR0. S R FSR0 1 SERIAL PORT 1 SIGNALS CLKX1 1 I/O/Z Serial port 1 transmit clock. CLKX1 is the serial shift clock for the serial port 1 transmitter. S R DX1 1 I/O/Z Data transmit output. Serial port 1 transmits serial data on DX1. S R S R FSX1 1 I/O/Z Frame synchronization pulse for transmit. The FSX1 pulse initiates the transmit data process over DX1. CLKR1 1 I/O/Z Serial port 1 receive clock. CLKR1 is the serial shift clock for the serial port 1 receiver. S R DR1 1 I/O/Z Data receive. Serial port 1 receives serial data on DR1. S R FSR1 1 I/O/Z Frame synchronization pulse for receive. The FSR1 pulse initiates the receive data process over DR1. S R I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0. S R S R TIMER 0 SIGNAL TCLK0 1 TIMER 1 SIGNAL TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1. SUPPLY AND OSCILLATOR SIGNALS GEL PPM VDD IODVDD 4 8 I 2 4 I ADVDD PDVDD 2 4 I 1 2 I DDVDD 2 4 I MDVDD VSS 1 2 I 5 V supply¶ 5 V supply¶ 4 8 I Ground DVSS 4 8 I Ground CVSS 2 4 I Ground 5 V supply¶ 5 V supply¶ 5 V supply¶ 5 V supply¶ IVSS 2 1 I Ground † I = input, O = output, Z = high-impedance state. All pins labeled NC have special functions and should not be connected by the user. ‡ Quantity is the same for GEL and PPM packages unless otherwise noted. § S = SHZ active, H = HOLD active, R = RESET active ¶ Recommended decoupling capacitor is 0.1 µF. 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 TMS320C30 Pin Functions (Continued) PIN NAME QTY‡ TYPE† DESCRIPTION CONDITIONS WHEN SIGNAL IS Z TYPE§ SUPPLY AND OSCILLATOR SIGNALS (CONTINUED) VBBP VSUBS 1 NC 1 I X1 1 O Output from the internal oscillator for the crystal. If a crystal is not used, X1 should be left unconnected. X2 / CLKIN 1 I Input to the internal oscillator from the crystal or a clock H1 1 O/Z External H1 clock. H1 has a period equal to twice CLKIN. S H3 1 O/Z External H3 clock. H3 has a period equal to twice CLKIN. RESERVED¶ S EMU0 – EMU2 3 I EMU3 1 O/Z I VBB pump oscillator output Substrate terminal. Tie to ground. Reserved. Use pullup resistors to 5 V. Reserved S Shutdown high impedance. When active, EMU4 / SHZ shuts down the TMS320C30 and places all pins in the high-impedance state. EMU4 / SHZ is used for board-level testing to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ corrupts TMS320C30 memory and register contents. Reset the device with SHZ high to restore it to a known operating condition. EMU4 / SHZ 1 EMU5, EMU6 2 NC Reserved RSV10 – RSV5 6 I/O Reserved. Use pullup resistors to 5 V. RSV4 – RSV0 5 1# I Reserved. Tie pins directly to 5 V. Locator NC Reserved † I = input, O = output, Z = high-impedance state. All pins labeled NC have special functions and should not be connected by the user. ‡ Quantity is the same for GEL and PPM packages unless otherwise noted. § S = SHZ active, H = HOLD active, R = RESET active ¶ Follow the connections specified for the reserved pins. Use 18-kΩ – 22-kΩ pullup resistors for best results. All 5-V supply pins must be connected to a common supply plane, and all ground pins must be connected to a common ground plane. # For the GEL package only. There is no locator in the PPM package. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 functional block diagram 32 24 24 ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ RAM Block 1 (1K × 32) RAM Block 0 (1K × 32) Cache (64 × 32) 32 24 ROM Block (4K × 32) 32 24 32 PDATA Bus PADDR Bus XRDY MSTRB IOSTRB XR / W XD31–XD0 XA12 –XA0 ÉÉ MUX DDATA Bus MUX RDY HOLD HOLDA STRB R/W D31– D0 A23 – A0 DADDR1 Bus DADDR2 Bus DMADATA Bus DMAADDR Bus 32 24 32 24 24 32 24 DMA Controller Serial Port 0 Serial-Port-Control Register Global-Control Register MUX DestinationAddress Register REG1 TransferCounter Register REG2 REG1 CPU1 REG2 32 32 40 40 32-Bit Barrel Shifter Multiplier ALU 40 40 40 32 40 ExtendedPrecision Registers (R7–R0) Peripheral Address Bus CPU1 CPU2 Controller RESET INT(3 – 0) IACK MC / MP XF(1,0) VDD IODVDD ADVDD PDVDD DDVDD MDVDD VSS DVSS CVSS IVSS VBBP VSUBS X1 X2 / CLKIN H1 H3 EMU(6 – 0) RSV(10 – 0) Receive/Transmit (R/X) Timer Register Source-Address Register Peripheral Data Bus IR PC Data-Transmit Register Data-Receive Register ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ Serial Port 1 Serial-Port-Control Register Receive/Transmit (R/X) Timer Register Data-Transmit Register 40 40 FSX1 DX1 CLKX1 FSR1 DR1 CLKR1 Data-Receive Register Timer 0 Global-Control Register DISP0, IR0, IR1 ARAU0 BK ARAU1 24 24 24 32 32 Auxiliary Registers (AR0 – AR7) 32 Other Registers (12) Timer-Period Register Timer 1 32 Global-Control Register 32 Timer-Period Register Timer-Counter Register Port Control Primary-Control Register Expansion-Control Register POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TCLK0 Timer-Counter Register 24 32 12 FSX0 DX0 CLKX0 FSR0 DR0 CLKR0 TCLK1 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 memory map Figure 1 depicts the memory map for the TMS320C30. Refer to the TMS320C3x User’s Guide (literature number SPRU031) for a detailed description of this memory mapping. Figure 2 shows the reset, interrupt, and trap vector/branches memory-map locations. Figure 3 shows the peripheral bus memory-mapped registers. 0h 03Fh 040h Reset, Interrupt, Trap Vectors, and Reserved Locations (64) (External STRB Active) 801FFFh 802000h 0BFh 0C0h Reset, Interrupt, Trap Vectors, and Reserved Locations (192) ROM (Internal) External STRB Active (8M Words – 64 Words) 7FFFFFh 800000h 0h Expansion-Bus MSTRB Active (8K Words) 0FFFh 1000h External STRB Active (8M Words – 4K Words) 7FFFFFh 800000h Expansion-Bus MSTRB Active (8K Words) 801FFFh 802000h Reserved (8K Words) Reserved (8K Words) 803FFFh 804000h 805FFFh 806000h Expansion-Bus IOSTRB Active (8K Words) 803FFFh 804000h Expansion-Bus IOSTRB Active (8K Words) 805FFFh 806000h Reserved (8K Words) 807FFFh 808000h 8097FFh 809800h 809BFFh 809C00h 809FFFh 80A000h Peripheral-Bus Memory-Mapped Registers (6K Words Internal) RAM Block 0 (1K Word Internal) RAM Block 1 (1K Word Internal) Reserved (8K Words) 807FFFh 808000h 8097FFh 809800h 809BFFh 809C00h 809FFFh 80A000h External STRB Active (8M Words – 40K Words) Peripheral-Bus Memory-Mapped Registers (6K Words Internal) RAM Block 0 (1K Word Internal) RAM Block 1 (1K Word Internal) External STRB Active (8M Words – 40K Words) 0FFFFFFh 0FFFFFFh (a) Microprocessor Mode (b) Microcomputer Mode Figure 1. TMS320C30 Memory Map POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 memory map (continued) 00h Reset 00h Reset 01h INT0 01h INT0 02h INT1 02h INT1 03h INT2 03h INT2 04h INT3 04h INT3 05h XINT0 05h XINT0 06h RINT0 06h RINT0 07h XINT1 07h XINT1 08h RINT1 08h RINT1 09h TINT0 09h TINT0 0Ah TINT1 0Ah TINT1 DINT 0Bh DINT 0Bh 0Ch 0Ch Reserved 1Fh 20h Reserved 1Fh TRAP 0 TRAP 0 20h . . . 3Bh 3Ch 3Fh . . . TRAP 27 TRAP 27 3Bh 3Ch Reserved Reserved BFh (a) Microprocessor Mode (a) Microcomputer Mode Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 memory map (continued) 808000h DMA Global Control 808004h DMA Source Address 808006h DMA Destination Address 808008h DMA Transfer Counter 808020h Timer 0 Global Control 808024h Timer 0 Counter 808028h Timer 0 Period 808030h Timer 1 Global Control 808034h Timer 1 Counter 808038h Timer 1 Period Register 808040h Serial Port 0 Global Control 808042h FSX/DX/CLKX Serial Port 0 Control 808043h FSR/DR/CLKR Serial Port 0 Control 808044h Serial Port 0 R/X Timer Control 808045h Serial Port 0 R/X Timer Counter 808046h Serial Port 0 R/X Timer Period 808048h Serial Port 0 Data Transmit 80804Ch Serial Port 0 Data Receive 808050h Serial Port 1 Global Control 808052h FSX/DX/CLKX Serial Port 1 Control 808053h FSR/DR/CLKR Serial Port 1 Control 808054h Serial Port 1 R/X Timer Control 808055h Serial Port 1 R/X Timer Counter 808056h Serial Port 1 R/X Timer Period 808058h Serial Port 1 Data Transmit 80805Ch Serial Port 1 Data Receive 808060h Expansion-Bus Control 808064h Primary-Bus Control †Shading denotes reserved address locations Figure 3. Peripheral Bus Memory-Mapped Registers† POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Continuous power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 W Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to VSS. 2. Actual operating power is less. This value is obtained under specially produced worst-case test conditions, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both primary and extension buses at the maximum rate possible. See normal (ICC) current specification in the electrical characteristics table and also read Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020). recommended operating conditions (see Note 3) VDD VSS Supply voltage (AVDD, etc.) NOM‡ MAX UNIT 4.75 5 5.25 V Supply voltage (CVSS, etc.) VIH High level input voltage High-level VIL IOH Low-level input voltage 0 All other pins CLKIN 2 2.6 – 0.3§ High-level output current IOL Low-level output current TC Operating case temperature ‡ All nominal values are at VDD = 5 V, TA (ambient air temperature)= 25°C. § These values are derived from characterization and not tested. NOTE 3: All input and output voltage levels are TTL-compatible. 16 MIN POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 0 V VDD + 0.3§ VDD + 0.3§ V 0.8 V – 300 µA 2 mA 85 °C TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 electrical characteristics over recommended ranges of supply voltage (unless otherwise noted) (see Note 3) TEST CONDITIONS† PARAMETER VOH VOL High-level output voltage IZ II High-impedance current Input current VDD = MAX VI = VSS to VDD IIP Input current Inputs with internal pullups (see Note 4) ICC Ci VDD = MIN, VDD = MIN, Low-level output voltage TA = 25°C,, VDD = MAX,, tc(CI) = MIN, See Note 5 Supply current Input capacitance IOH = MAX IOL = MAX MIN TYP‡ 2.4 3 MAX V 0.6§ V – 20 20 µA – 10 10 µA 20 µA 0.3 – 600 ’320C30 - 27 130 600 ’320C30 - 33 150 600 ’320C30 - 40 175 600 ’320C30 - 50 200 600 CLKIN 25 All other inputs UNIT 15 20¶ mA pF Co Output capacitance pF † For conditions shown as MIN / MAX, use the appropriate value specified in recommended operating conditions. ‡ All typical values are at VDD = 5 V, TA (ambient air temperature)= 25°C. § These values are derived from characterization but not tested. ¶ These values are derived by design but not tested. NOTES: 3. All input and output voltage levels are TTL-compatible. 4. Pins with internal pullup devices: INT0 – INT3, MC / MP, RSV0 – RSV10. Although RSV0 – RSV10 have internal pullup devices, external pullups should be used on each pin as identified in the pin functions tables. 5. Actual operating current is less than this maximum value. This value is obtained under specially produced worst-case test conditions, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both primary and expansion buses at the maximum rate possible. See Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics Output Under Test VLOAD CT IOH Where: IOL IOH VLOAD CT = = = = 2 mA (all outputs) 300 µA (all outputs) 2.15 V 80-pF typical load-circuit capacitance Figure 4. Test Load Circuit signal transition levels TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V. Output transition times are specified as follows (see Figure 5): D D For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no longer high is 2 V and the level at which the output is said to be low is 1 V. For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at which the output is said to be high is 2 V. 2.4 V 2V 1V 0.6 V Figure 5. TTL-Level Outputs Transition times for TTL-compatible inputs are specified as follows (see Figure 6): D D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 2 V and the level at which the input is said to be low is 0.8 V. For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 0.8 V and the level at which the input is said to be high is 2 V. 2V 90% 10% 0.8 V Figure 6. TTL-Level Inputs 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows, unless otherwise noted: A (L)A30 – (L)A0 or (L)Ax IOS IOSTRB ASYNCH Asynchronous reset signals in the high-impedance state (M)S (M)STRB, includes STRB and MSTRB CH CLKX0 and CLKX1 RDY RDY CI CLKIN RESET RESET CLKR CLKR0 and CLKR1 RW R/W CONTROL Control signals S (M)S, which includes MSTRB, STRB; and IOS, IOSTRB D D31 – D0 or Dx SCK CLKX/R, includes CLKX0, CLKX1, CLKR0, and CLKR1 DR DR0 and DR1 TCLK TCLK0 and TCLK1 DX DX0 and DX1 XA XA12 – XA0 or XAx FS FSX/R, includes FSX0, FSX1, FSR0, and FSR1 (X)A Includes A23 – A0 and XA12 – XA0 FSR FSR0 and RSR1 XD XD31 –XD0 or XDx FSX FSX0 and FSX1 (X)D Includes D31 – D0 and XD31 – XD0 GPIO General-purpose input/output (peripheral pins include CLKX0/1, CLKR01, DX0/1, DR0/1, FSX0/1, FSR0/1, TCLK0/1) XF XFx, includes XF0 and XF1 H H1 and H3 XF0 XF0 H1 H1 XF1 XF1 H3 H3 XFIO XFx switching from input to output HOLD HOLD XRDY XRDY HOLDA HOLDA (X)RDY (X)RDY, includes RDY and XRDY IACK IACK XRW XR/W INT INT3 – INT0 (X)RW (X)R/W, includes R/W and XR/W POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 X2/CLKIN, H1, and H3 timing The following table defines the timing parameters for the X2/CLKIN, H1, and H3 interface signals. The numbers shown in Figure 7 and Figure 8 correspond with those in the NO. column of the table below. Refer to the RESET timing in Figure 19 for CLKIN to H1 and H3 delay specification. timing parameters for X2/CLKIN, H1, H3 (see Figure 7 and Figure 8) ’C30-27 NO NO. 1 MIN tf(CI) tw(CIL) Fall time, CLKIN Pulse duration, CLKIN low tc(CI) = min 14 tw(CIH) tr(CI) Pulse duration, CLKIN high tc(CI) = min 14 tc(CI) tf(H) Cycle time, CLKIN Pulse duration, H1 and H3 low 8 tw(HL) tw(HH) 9 tr(H) Rise time, H1 and H3 2 3 4 5 6 7 9.1 ’C30-33 MAX 6† MIN MAX 5† 10 37 303 Fall time, H1 and H3 30 Delay time, from H1 low to H3 high or td(HL-HH) from H3 low to H1 high 10 tc(H) Cycle time, H1 and H3 † Specified by design but not tested ‡ P = tc(CI) P–6‡ P–7‡ MAX 5† 7 20 3 P–5‡ P–6‡ ns 5† ns 303 ns 3 ns P – 5‡ P – 6‡ 3 ns ns 7 303 UNIT ns ns 3 ns 0 6 0 5 0 4 0 4 ns 74 606 60 606 50 606 40 606 ns 4 1 X2/CLKIN 3 2 Figure 7. Timing for X2/CLKIN POST OFFICE BOX 1443 25 4 5 20 303 MIN 5† 3 5 MAX 5† 9 5† 4 P–6‡ P–7‡ MIN ’C30-50 9 10 6† Rise time, CLKIN Pulse duration, H1 and H3 high ’C30-40 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 X2/CLKIN, H1, and H3 timing (continued) 10 9 6 H1 8 7 9.1 9.1 H3 9 7 6 8 10 Figure 8. Timing for H1 and H3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 timing parameters for a memory [(M)STRB = 0] read/write (see Figure 9 and Figure 10) ’C30-27 NO NO. 11 ’C30-33 MIN 0† MAX 0† 0† 13 19 ’C30-40 MAX MAX 6‡ MIN 0† MAX 0† 0† 10 4 ns 0† 0† 6 0† 0† 4 ns 15 16 0† 0† 7 ns 13 ns 11 0† 0† 11 14 0† 0† 12 0† 9 ns 10 0† 9 0† 8 ns Delay time, H1 low to (M)STRB low td(H1H-RWL) td(H1H-XRWL) Delay time, H1 high to R/W low td(H1L-A) td(H1L-XA) Delay time, H1 low to A valid 0† 0† Delay time, H1 low to XA valid 0† Setup time, D before H1 low (read) 18 16 14 10 ns 15.2 tsu(D-H1L)R tsu(XD-H1L)R Setup time, XD before H1 low (read) 21 18 16 14 ns 16 th[H1L-(X)D]R Hold time, (X)D after H1 low (read) 0 0 0 0 ns 17.1 tsu(RDY-H1H) Setup time, RDY before H1 high 10 8 8 6 ns 17.2 tsu(XRDY-H1H) Setup time, XRDY before H1 high 11 9 9 8 ns 18 th[H1H-(X)RDY] Hold time, (X)RDY after H1 high 0 0 0 0 ns 19 td[H1H-(X)RWH]W Delay time, H1 high to (X)R/W high (write) 13 10 9 7 ns 20 tv[H1L-(X)D]W Valid time, (X)D after H1 low (write) 25 20 17 14 ns 21 th[H1H-(X)D]W Hold time, (X)D after H1 high (write) 22.1 td(H1H-A)W Delay time, H1 high to A valid on back-to-back write cycles (write) 23 18 15 12 ns 22.2 td(H1H-XA)W Delay time, H1 high to XA valid on back-to-back write cycles (write) 32 25 21 18 ns 10§ 8§ 7§ 6 ns 13.1 13.2 14.1 14.2 15.1 Delay time, H1 low to (M)STRB high Delay time, H1 high to XR/W low 26 td[A-(X)RDY] Delay time, (X)RDY from A valid † Specified by design but not tested ‡ For ’C30 PPM, td[H1L-(M)SL] (max)=7 ns § This value is characterized but not tested 13 UNIT MIN 0† td[H1L-(M)SL] td[H1L-(M)SH] 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MIN 0† ’C30-50 13 0† 10 10 0† 9 0† 0† ns TMS320C30 DIGITAL SIGNAL PROCESSOR The following table defines memory read/write timing parameters for (M)STRB. The numbers shown in Figure 9 and Figure 10 correspond with those in the NO. column of the table. SPRS032A – APRIL 1996 – REVISED JUNE 1997 22 memory read/write timing TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 memory read/write timing (continued) H3 H1 11 12 (M)STRB (see Note A) (X)R/W 14.1/14.2 13.1/13.2 (X)A 15.1/15.2 16 26 (X)D 17.1/17.2 18 (X)RDY NOTE A: (M)STRB remains low during back-to-back read operations. Figure 9. Timing for Memory [(M)STRB = 0] Read H3 H1 12 11 (M)STRB 19 13.1/13.2 (X)R/W 14.1/14.2 22.1/22.2 (X)A 20 21 (X)D 17.1/17.2 18 (X)RDY Figure 10. Timing for Memory [(M)STRB = 0] Write POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 memory read/write timing (continued) The following table defines memory read timing parameters for IOSTRB. The numbers shown in Figure 11 correspond with those in the NO. column of the table below. timing parameters for a memory (IOSTRB = 0) read (see Figure 11) ’C30-27 NO NO. ’C30-33 ’C30-40 ’C30-50 MIN MAX MIN MAX MIN MAX MIN MAX UNIT 11.1 td(H1H-IOSL) Delay time, H1 high to IOSTRB low 0† 13 0† 10 0† 9 0† 8 ns 12.1 td(H1H-IOSH) Delay time, H1 high to IOSTRB high 0† 13 0† 10 0† 9 0† 8 ns 13.1 td(H1L-XRWH) td(H1L-XA) Delay time, H1 low to XR/W high 0† 0† 13 0† 0† 10 0† 0† 9 0 0† 8 ns 14.3 8 ns 15.3 tsu(XD-H1H)R 16.1 17.3 thH1H-XD)R tsu(XRDY-H1H) 18.1 th(H1H-XRDY) Hold time, XRDY after H1 high Delay time, H1 low to XA valid Setup time, XD before H1 high (read) 13 10 9 19 15 13 11 ns Hold time, XD after H1 high (read) 0 0 0 0 ns Setup time, XRDY before H1 high 11 9 9 8 ns 23 td(H1L-XRWL) Delay time, H1 low to XR/W low † This value is characterized but not tested 0 0 0† 19 0 0† 15 0 0† 13 H3 H1 11.1 12.1 IOSTRB 13.1 23 XR/W 14.3 XA 15.3 16.1 XD 17.3 18.1 (X)RDY Figure 11. Timing for Memory (IOSTRB = 0) Read 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 0† ns 11 ns TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 memory read/write timing (continued) The following table defines memory write timing parameters for IOSTRB. The numbers shown in Figure 12 correspond with those in the NO. column of the table below. timing parameters for a memory (IOSTRB = 0) write (see Figure 12) ’C30-27 NO NO. 11.1 12.1 13.1 14.3 17.3 18.1 23 24 MIN 0† MAX 13 td(H1H-IOSL) td(H1H-IOSH) Delay time, H1 high to IOSTRB low td(H1L-XRWH) td(H1L-XA) Delay time, H1 low to XR/W high 0† 0† Delay time, H1 low to XA valid 0† tsu(XRDY-H1H) th(H1H-XRDY) Setup time, XRDY before H1 high td(H1L-XRWL) tv(H1H-XD)W Delay time, H1 high to IOSTRB high ’C30-33 ’C30-40 MIN 0† MAX 10 13 0† 0† 13 0† 13 ’C30-50 MIN 0† MAX 10 0† 0† 10 0† 9 10 UNIT MAX 9 MIN 0† 8 ns 9 0† 8 ns 9 0 0† 8 ns 8 ns 11 9 9 8 ns Hold time, XRDY after H1 high 0 0 0 0 ns Delay time, H1 low to XR/W low 0† 0† 0† 0† Valid time, (X)D after H1 high (write) 25 th(H1L-XD)W Hold time, (X)D after H1 low (write) † This value is characterized but not tested 19 15 38 0 13 30 0 25 0 0 11 ns 20 ns ns H3 H1 11.1 12.1 IOSTRB 13.1 23 (X)R/W 14.3 (X)A 25 24 (X)D 17.3 18.1 (X)RDY Figure 12. Timing for Memory (IOSTRB = 0) Write POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 XF0 and XF1 timing when executing LDFI or LDII The following table defines the timing parameters for XF0 and XF1 during execution of LDFI or LDII. The numbers shown in Figure 13 correspond with those in the NO. column of the table below. timing parameters for XF0 and XF1 when executing LDFI or LDII (see Figure 13) ’C30-27 NO NO. 1 MIN td(H3H-XF0L) tsu(XF1-H1L) Delay time, H3 high to XF0 low 2 3 th(H1L-XF1) Hold time, XF1 after H1 low MIN 19 Setup time, XF1 before H1 low Fetch LDFI or LDII MAX ’C30-33 Decode MAX ’C30-40 MIN 15 MAX 13 12 UNIT ns 9 9 ns 0 0 0 0 ns Read Execute (M)STRB (X)R/W (X)A (X)D (X)RDY 1 2 3 XF1 Pin Figure 13. Timing for XF0 and XF1 When Executing LDFI or LDII POST OFFICE BOX 1443 MAX 10 H1 26 MIN 13 H3 XF0 Pin ’C30-50 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 XF0 timing when executing STFI and STII The following table defines the timing parameters for the XF0 pin during execution of STFI or STII. The number shown in Figure 14 corresponds with the number in the NO. column of the table below. timing parameters for XF0 when executing STFI or STII (see Figure 14) ’C30-27 NO NO. 1 MIN td(H3H-XF0H) Delay time, H3 high to XF0 high ’C30-33 MAX MIN 19 MAX ’C30-40 MIN 15 MAX 13 ’C30-50 MIN MAX 12 UNIT ns XF0 is always set high at the beginning of the execute phase of the interlock store instruction. When no pipeline conflicts occur, the address of the store is also driven at the beginning of the execute phase of the interlock store instruction. However, if a pipeline conflict prevents the store from executing, the address of the store will not be driven until the store can execute. Fetch STFI or STII Decode Read Execute H3 H1 (M)STRB (X)R/W (X)A (X)D 1 (X)RDY XF0 Pin Figure 14. Timing for XF0 When Executing an STFI or STII POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 XF0 and XF1 timing when executing SIGI The following table defines the timing parameters for the XF0 and XF1 pins during execution of SIGI. The numbers shown in Figure 15 correspond with those in the NO. column of the table below. timing parameters for XF0 and XF1 when executing SIGI (see Figure 15) ’C30-27 NO NO. 1 2 3 4 MIN ’C30-33 MAX MIN MAX ’C30-40 MIN MAX MIN MAX UNIT td(H3H-XF0L) td(H3H-XF0H) Delay time, H3 high to XF0 low 19 15 13 12 ns Delay time, H3 high to XF0 high 19 15 13 12 ns tsu(XF1-H1L) th(H1L-XF1) Setup time, XF1 before H1 low Hold time, XF1 after H1 low Fetch SIGI Decode 13 10 9 9 ns 0 0 0 0 ns Read Execute H3 H1 1 3 XF0 4 XF1 Figure 15. Timing for XF0 and XF1 When Executing SIGI 28 ’C30-50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 2 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 loading when XFx is configured as an output The following table defines the timing parameter for loading the XF register when the XFx pin is configured as an output. The number shown in Figure 16 corresponds with the number in the NO. column of the table below. timing parameters for loading the XFx register when configured as an output pin (see Figure 16) ’C30-27 NO NO. 1 MIN tv(H3H-XF) Valid time, H3 high to XFx Fetch Load Instruction MAX ’C30-33 MIN 19 Decode Read ’C30-40 MAX MIN 15 ’C30-50 MAX MIN 13 MAX 12 UNIT ns Execute H3 H1 OUTXF Bit (see Note A) 1 or 0 1 XFx NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register. Figure 16. Timing for Loading XFx Register When Configured as an Output Pin POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 changing XFx from an output to an input The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin. The numbers shown in Figure 17 correspond with those in the NO. column of the table below. timing parameters of XFx changing from output to input mode (see Figure 17) ’C30-27 NO NO. 1 2 MIN th(H3H-XF) tsu(XF-H1L) Hold time, XFx after H3 high Setup time, XFx before H1 low 3 th(H1L-XF) Hold time, XFx after H1 low † For ’C30 PPM, tn(H3H-XF01) (max)=14 ns ‡ This value is characterized but not tested Execute Load of IOF ’C30-33 MAX 19‡ MIN MAX 15‡ ’C30-40 MIN MAX 13†‡ ’C30-50 MIN MAX 12‡ 10 9 9 ns 0 0 0 0 ns Synchronizer Delay Value on Pin Seen in IOF H3 H1 2 XFx 3 1 Output Data Sampled INXF Bit (see Note A) Data Seen NOTE A: I / OXFx represents bit 1 or 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register. Figure 17. Timing for Change of XFx From Output to Input Mode 30 POST OFFICE BOX 1443 ns 13 Buffers Go From Output to Output I / OXFx Bit (see Note A) UNIT • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 changing XFx from an input to an output The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin. The number shown in Figure 18 corresponds with the number in the NO. column of the table below. timing parameters of XFx changing from input to output mode (see Figure 18) ’C30-27 NO NO. 1 MIN td(H3H-XFIO) Delay time, H3 high to XFx switching from input to output MAX ’C30-33 MIN 25 MAX ’C30-40 MIN MAX 20 17 ’C30-50 MIN MAX 17 UNIT ns Execution of Load of IOF H3 H1 I / OXFx Bit (see Note A) 1 XFx NOTE A: I / OXFx represents either bit 1 or 5 of the IOF register. Figure 18. Timing for Change of XFx From Input to Output Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 reset timing RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 19 occurs; otherwise, an additional delay of one clock cycle is possible. The asynchronous reset signals include XF0/1, CLKX0/1, DX0/1, FSX0/1, CLKR0/1, DR0/1, FSR0/1, and TCLK0/1. The following table defines the timing parameters for the RESET signal. The numbers shown in Figure 19 correspond with those in the NO. column of the following table. Resetting the device initializes the primary- and expansion-bus control registers to seven software wait states and therefore results in slow external accesses until these registers are initialized. Note also that HOLD is an asynchronous input and can be asserted during reset. timing parameters for RESET for the TMS320C30 (see Figure 19) ’C30-27 NO NO. ’C30-33 ’C30-40 ’C30-50 MIN MAX MIN MAX MIN MAX MIN MAX UNIT tsu(RESET-CIL) Setup time, RESET before CLKIN low 28 P†‡ 10 P†‡ 10 P†‡ 10 P†‡ ns 2.1 td(CIH-H1H) Delay time, CLKIN high to H1 high§¶ 2 20 2 14 2 12 2 10 ns 2.2 td(CIH-H1L) Delay time, CLKIN high to H1 low§¶ 2 20 2 14 2 12 2 10 ns tsu(RESETH-H1L) Setup time, RESET high before H1 low and after ten H1 clock cycles 13 5.1 td(CIH-H3L) Delay time, CLKIN high to H3 low§¶ 2 20 2 14 2 12 2 10 ns 5.2 td(CIH-H3H) Delay time, CLKIN high to H3 high§¶ 2 20 2 14 2 12 2 10 ns 8 tdis[H1H-(X)D] Disable time, H1 high to (X)D (high impedance) 19† 15† 13† 12† ns 9 tdis[H3H-(X)A] Disable time, H3 high to (X)A (high impedance) 13† 10† 9† 8† ns 10 td(H3H-CONTROLH) Delay time, H3 high to control signals high 13† 10† 9† 8† ns 12 td(H1H-RWH) Delay time, H1 high to R/W high 13† 10† 9† 8† ns 13 td(H1H-IACKH) Delay time, H1 high to IACK high 13† 10† 9† 8† ns 14 tdis(RESETL-ASYNCH) Disable time, RESET low to asynchronous reset signals (high impedance) 31† 25† 21† 17† ns 1 3 10 † This value is characterized but not tested ‡ P = tc(CI) § See Figure 20 for temperature dependence for the 33-MHz and the 40-MHz TMS320C30. ¶ See Figure 21 for temperature dependence for the 50-MHz TMS320C30. 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 7 ns TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 reset timing (continued) CLKIN 1 RESET (see Notes E and F) 2.1 2.2 3 H1 5.1 H3 Ten H1 Clock Cycles 8 (X)D (see Notes A and G) 5.2 (X)A (see Notes B and G) 9 10 Control Signals (see Note C) 12 (X)R / W 13 IACK Asynchronous Reset Signals (see Note D) 14 NOTES: A. B. C. D. E. (X)D includes D31–D0 and XD31–XD0. (X)A includes A23–A0 and XA12–XA0. Interface signals include STRB, MSTRB, and IOSTRB. Asynchronous reset signals include XF0/1, CLKX0/1, DX0/1, FSX0/1, CLKR0/1, DR0/1, FSR0/1, and TCLK0/1. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle is possible. F. The R/W and XR/W outputs are placed in a high-impedance state during reset and can be provided with a resistive pullup, nominally 18–22 kΩ, if undesirable spurious writes could be caused when these outputs go low. G. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the reset vector is fetched twice, with no software wait states. Figure 19. Timing for RESET POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 reset timing (continued) Figure 20 and Figure 21 illustrate CLKIN-to-H1 and CLKIN-to-H3 timing as a function of case temperature. 22 TMS320C30-33 CLKIN to H1 and H3 (ns) 20 4.75 V ≤ VDD ≤ 5.25 V 18 16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Case Temperature (°C) 22 TMS320C30-40 CLKIN to H1 and H3 (ns) 20 4.75 V ≤ VDD ≤ 5.25 V 18 16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Case Temperature (°C) Figure 20. CLKIN to H1 and H3 as a Function of Temperature 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 CLKIN to H1 and H3 (ns) reset timing (continued) 20 18 TMS320C30-50 16 4.75 V ≤ VDD ≤ 5.25 V 14 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 Case Temperature (°C) Figure 21. CLKIN to H1 and H3 as a Function of Temperature POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 interrupt response timing The following table defines the timing parameters for the INT signals. The numbers shown in Figure 22 correspond with those in the NO. column of the table below. timing parameters for INT3–INT0 (see Figure 22) ’C30-27 NO NO. 1 2 MIN tsu(INT-H1L) Setup time, INT3–INT0 before H1 low 19 tw(INT) Pulse duration, interrupt to ensure only one interrupt P MAX ’C30-33 MIN MAX 15 2P†‡ P ’C30-40 MIN MAX 13 2P†‡ P ’C30-50 MIN MAX 10 2P†‡ P UNIT ns 2P†‡ ns † Characterized but not tested ‡ P = tc(H) The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The TMS320C30 interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1. Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA respond to detected interrupts on instruction-fetch boundaries only. For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held to: D D A minimum of one H1 falling edge No more than two H1 falling edges The TMS320C30 can accept an interrupt from the same source every two H1 clock cycles. If the specified timings are met, the exact sequence shown in Figure 22 occurs; otherwise, an additional delay of one clock cycle is possible. Reset or Interrupt Vector Read Fetch First Instruction of Service Routine H3 H1 1 INT3 – INT0 Pin 2 INT3 – INT0 Flag ADDR Vector Address First Instruction Address Data Figure 22. Timing for INT3 – INT0 Response 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 interrupt-acknowledge timing The IACK output goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle (H1 rising) of the read phase of the IACK instruction. The following table defines the timing parameters for the IACK signal. The numbers shown in Figure 23 correspond with those in the NO. column of the table below. timing parameters for IACK (see Note 6 and Figure 23) ’C30-27 NO NO. 1 2 MIN td(H1H-IACKL) td(H1H-IACKH) MAX ’C30-33 MIN MAX ’C30-40 MIN ’C30-50 MAX MIN MAX UNIT Delay time, H1 high to IACK low 13 10 9 7 ns Delay time, H1 high to IACK high 13 10 9 7 ns NOTE 6: IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle (H1 rising) of the read phase of the IACK instruction. Because of the pipeline conflicts, IACK remains low for one cycle even if the decode phase of the IACK instruction is extended. Fetch IACK Instruction Decode IACK Instruction IACK Data Read H3 H1 1 2 IACK ADDR Data Figure 23. Timing for IACK POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 37 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 serial-port timing parameters (see Figure 24 and Figure 25) ’320C30-27 NO NO. 1 MIN td(H1H-SCK) Delay time, H1 high to internal CLKX/R 19 CLKX/R ext tc(H)x2.6 tc(H)x2 2 tc(SCK) (SCK) Cycle time, time CLKX/R 3 tw(SCK) (SCK) Pulse duration, duration CLKX/R high/low 4 tr(SCK) tf(SCK) Rise time, CLKX/R [tc(SCK)/2]+5 10 Fall time, CLKX/R 10 5 CLKX/R int CLKX/R ext CLKX/R int 44 CLKX int 25 6 td(CH-DX) d(CH DX) Delay time, time CLKX to DX valid 7 tsu(DR-CLKRL) (DR CLKRL) Setup time, time DR before CLKR low 8 th(CLKRL-DR) h(CLKRL DR) Hold time, time DR from CLKR low 9 td(CH-FSX) d(CH FSX) Delay time, time CLKX to internal FSX high/low 10 tsu(FSR-CLKRL) (FSR CLKRL) time FSR0 or FSR1 before CLKR low Setup time, 11 th(SCKL-FS) h(SCKL FS) Hold time, time FSX/R input from CLKX/R low 12 tsu(FSX-CH) (FSX CH) Setup time, time external FSX before CLKX 13 td(CH-DX)V d(CH DX)V Delay y time,, CLKX to first DX bit,, FSX0 or FSX1 precedes CLKX high 14 td(FSX-DX)V Delay time, FSX0 or FSX1 to first DX bit, CLKX precedes FSX0 or FSX1 POST OFFICE BOX 1443 tc(H)+12 [tc(SCK)/2]–15 tc(H)x232 CLKX ext CLKR ext 13 CLKR int 31 CLKR ext 13 CLKR int 0 40 21 13 CLKR int 13 CLKX/R ext 13 CLKX/R int 0 CLKX ext CLKX int CLKX ext CLKX int • HOUSTON, TEXAS 77251–1443 –[tc(H)–8]† –[tc(H)–21]† ns ns ns ns ns ns ns CLKX ext CLKR ext UNIT ns CLKX int 15 td(CHH-DXZ) Delay time, CLKX high to DX high impedance following last data bit † This value is characterized but not tested 38 MAX ns ns ns [tc(SCK)/2]–10† tc(SCK)/2† ns 45† 26† ns 45† ns 25† ns TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 serial-port timing parameters (see Figure 24 and Figure 25) (continued) ’320C30-33 NO NO. 1 MIN td(H1H-SCK) Delay time, H1 high to internal CLKX/R 2 tc(SCK) (SCK) Cycle time, time CLKX/R 3 tw(SCK) (SCK) Pulse duration, duration CLKX/R high/low 4 tr(SCK) tf(SCK) Rise time, CLKX/R 5 MAX 15 CLKX/R ext CLKX/R int CLKX/R ext CLKX/R int tc(H)x2.6 tc(H)x2 tc(H)+12 [tc(SCK)/2]–15 Fall time, CLKX/R tc(H)x232 [tc(SCK)/2]+5 8 8 6 td(CH-DX) d(CH DX) Delay time, time CLKX to DX valid 7 tsu(DR-CLKRL) (DR CLKRL) Setup time, time DR before CLKR low 8 th(CLKRL-DR) h(CLKRL DR) Hold time time, DR from CLKR low 9 td(CH-FSX) d(CH FSX) Delay time time, CLKX to internal FSX high/low 10 tsu(FSR-CLKRL) (FSR CLKRL) time FSR before CLKR low Setup time, 11 th(SCKL-FS) h(SCKL FS) Hold time, time FSX/R input from CLKX/R low 12 tsu(FSX-CH) (FSX CH) Setup time, time external FSX before CLKX 13 td(CH-DX)V d(CH DX)V Delay y time,, CLKX to first DX bit,, FSX precedes CLKX high 14 td(FSX-DX)V 15 td(CHH-DXZ) CLKX ext 35 CLKX int 20 CLKR ext 10 CLKR int 25 CLKR ext 10 CLKR int 0 32 17 CLKR int 10 CLKX/R ext 10 CLKX/R int 0 CLKX ext CLKX int –[tc(H)–8]† [tc(H)–21]† ns ns ns ns ns ns CLKX int 10 ns ns CLKX ext CLKR ext UNIT ns ns ns [tc(SCK)/2]–10† tc(SCK)/2† ns 36† 21† ns Delay time, FSX to first DX bit, CLKX precedes FSX 36† ns Delay time, CLKX high to DX high impedance following last data bit 20† ns CLKX ext CLKX int † This value is characterized but not tested POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 39 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 serial-port timing parameters (see Figure 24 and Figure 25) (continued) ’320C30-40 NO NO. 1 MIN td(H1H-SCK) Delay time, H1 high to internal CLKX/R 2 tc(SCK) (SCK) Cycle time, time CLKX/R 3 tw(SCK) (SCK) Pulse duration, duration CLKX/R high/low 4 tr(SCK) tf(SCK) Rise time, CLKX/R 5 13 CLKX/R ext CLKX/R int CLKX/R ext CLKX/R int tc(H)x2.6 tc(H)x2 tc(H)+10 [tc(SCK)/2]–5 Fall time, CLKX/R tc(H)x232 [tc(SCK)/2]+5 7 7 6 td(CH-DX) d(CH DX) Delay time, time CLKX to DX valid 7 tsu(DR-CLKRL) (DR CLKRL) Setup time, time DR before CLKR low 8 th(CLKRL-DR) h(CLKRL DR) Hold time, time DR from CLKR low 9 td(CH-FSX) d(CH FSX) Delay time, time CLKX to internal FSX high/low 10 tsu(FSR-CLKRL) (FSR CLKRL) time FSR before CLKR low Setup time, 11 th(SCKL-FS) h(SCKL FS) Hold time, time FSX/R input from CLKX/R low 12 tsu(FSX-CH) (FSX CH) Setup time, time external FSX before CLKX 13 td(CH-DX)V Delay time, CLKX to first DX bit, FSX precedes CLKX high 14 td(FSX-DX)V 15 td(CHH-DXZ) CLKX ext 30 CLKX int 17 CLKR ext 9 CLKR int 21 CLKR ext 9 CLKR int 0 27 15 9 CLKR int 9 CLKX/R ext 9 CLKX/R int 0 CLKX ext CLKX int –[tc(H)–8]† [tc(H)–21]† ns ns ns ns ns ns ns CLKX int CLKR ext UNIT ns CLKX ext ns ns ns [tc(SCK)/2]–10† tc(SCK)/2† ns 30† 18† ns Delay time, FSX to first DX bit, CLKX precedes FSX 30† ns Delay time, CLKX high to DX high impedance following last data bit 17† ns CLKX ext CLKX int † This value is characterized but not tested 40 MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 serial-port timing parameters (see Figure 24 and Figure 25) (continued) ’320C30-50 NO NO. 1 MIN td(H1H-SCK) Delay time, H1 high to internal CLKX/R 2 tc(SCK) Cycle time, CLKX/R 3 tw(SCK) (SCK) Pulse duration, duration CLKX/R high/low 4 tr(SCK) tf(SCK) Rise time, CLKX/R 5 6 td(CH-DX) d(CH DX) Delay time, time CLKX to DX valid 7 tsu(DR-CLKRL) (DR CLKRL) time DR before CLKR low Setup time, 8 th(CLKRL-DR) h(CLKRL DR) Hold time time, DR from CLKR low 9 td(CH-FSX) d(CH FSX) Delay time time, CLKX to internal FSX high/low 10 tsu(FSR-CLKRL) (FSR CLKRL) Setup time, time FSR before CLKR low 11 th(SCKL-FS) h(SCKL FS) Hold time, time FSX/R input from CLKX/R low 12 tsu(FSX-CH) (FSX CH) time external FSX before CLKX Setup time, 13 td(CH-DX)V d(CH DX)V Delay y time,, CLKX to first DX bit,, FSX precedes CLKX high 14 td(FSX-DX)V 15 td(CHH-DXZ) MAX 10 CLKX/R ext CLKX/R int tc(H) × 2.6 tc(H) × 2 CLKX/R ext tc(H)+10 [tc(SCK)/2]–5 CLKX/R int Fall time, CLKX/R tc(H) × 232 [tc(SCK)/2]+5 6 6 CLKX ext 24 CLKX int 16 CLKR ext 9 CLKR int 17 CLKR ext 7 CLKR int 0 22 15 7 7 CLKX/R ext 7 CLKX/R int 0 CLKX ext CLKX int –[tc(H)–8]† [tc(H)–21]† ns ns ns ns ns ns CLKX ext CLKR ext ns ns CLKX int CLKR int UNIT ns ns ns [tc(SCK)/2]–10† tc(SCK)/2† ns 24† 14† ns Delay time, FSX to first DX bit, CLKX precedes FSX 24† ns Delay time, CLKX high to DX high impedance following last data bit 14† ns CLKX ext CLKX int † This value is characterized but not tested POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 data-rate timing modes Unless otherwise indicated, the data-rate timings shown in Figure 24 and Figure 25 are valid for all serial-port modes, including handshake. See serial-port timing parameter tables. 2 1 H1 1 3 3 CLKX/R 5 4 13 8 Bit n-1 DX 15 6 Bit n-2 Bit 0 7 DR Bit n-1 Bit n-2 FSR 10 9 9 FSX(INT) 11 FSX(EXT) 11 12 NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend on the length of the serial port word, where n = 8, 16, 24, or 32 bits, respectively. Figure 24. Timing for Fixed Data-Rate Mode CLKX/R 9 FSX(INT) 14 12 FSX(EXT) 6 15 13 Bit n-1 DX Bit n-2 Bit n-3 Bit 0 11 FSR 10 Bit n-1 DR Bit n-2 Bit n-3 7 8 NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed data-rate mode. Figure 25. Timing for Variable Data-Rate Mode 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 HOLD timing HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 26 occurs; otherwise, an additional delay of one clock cycle is possible. The “timing parameters for HOLD / HOLDA” table defines the timing parameters for the HOLD and HOLDA signals. The numbers shown in Figure 26 correspond with those in the NO. column of the table. The NOHOLD bit of the primary bus control register overrides the HOLD signal. When this bit is set, the device comes out of hold and prevents future hold cycles. Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus allowing the processor to continue until a second write is encountered. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 HOLD timing (continued) timing parameters for HOLD/HOLDA (see Figure 26) NO NO. ’C30-27 ’C30-33 ’C30-40 ’C30-50 MIN MIN MIN MIN MAX MAX MAX MAX UNIT 1 tsu(HOLD-H1L) Setup time, HOLD before H1 low 19 3 tv(H1L-HOLDA) Valid time, HOLDA after H1 low 0† 4 tw(HOLD‡) Pulse duration, HOLD low 2tc(H) 2tc(H) 2tc(H) 2tc(H) ns 6 tw(HOLDA) Pulse duration, HOLDA low tc(H)–5† tc(H)–5† tc(H)–5† tc(H) – 5† ns 7 td(H1L-SH)HOLD Delay time, H1 low to (M)S and IOS high for a HOLD 0§ 13 0§ 10 0§ 9 0§ 7 ns 8 tdis(H1L-S)Z Disable time, H1 low to (M)S and IOS in the high-impedance state 0§ 13† 0§ 10† 0§ 9† 0§ 8† ns 9 ten(H1L-S) Enable time, H1 low to (M)S and IOS (active) 0§ 13 0§ 10 0§ 9 0§ 7 ns 10 tdis[H1L-(X)RW]Z Disable time, H1 low to (X)R/W in the high-impedance state 0† 13† 0† 10† 0† 9† 0† 8† ns 11 ten[H1L-(X)RW] Enable time, H1 low to (X)R/W (active) 0† 13 0† 10 0† 9 0† 7 ns 12 tdis[H1L-(X)A] Disable time, H1 low to (X)A in the high-impedance state 0§ 13† 0§ 10† 0§ 10† 0§ 8† ns 13 ten[H1L-(X)A] Enable time, H1 low to (X)A (valid) 0§ 19 0§ 15 0§ 13 0§ 12 ns tdis[H1H-(X)D]Z Disable time, H1 high to (X)D in the high-impedance state 0§ 13† 0§ 10† 0§ 9† 0§ 8† ns 16 15 14 0† 13 10 0† 10 9 0† ns 7 ns † This value is characterized but not tested ‡ HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle is possible. § Not tested 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 HOLD timing (continued) H3 H1 1 1 4 HOLD 3 HOLDA (see Note A) 7 3 6 8 (M)STRB and IOSTRB 10 9 11 (X)R/W 12 13 (X)A 16 (X)D Write Data NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high. Figure 26. Timing for HOLD/HOLDA POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 45 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 general-purpose I/O timing Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The contents of the internal-control registers associated with each peripheral define the modes for these pins. peripheral pin I/O timing The following table defines peripheral pin general-purpose I/O timing parameters. The numbers shown in Figure 27 correspond with those in the NO. column of the table below. timing parameters for peripheral pin general-purpose I/O (see Note 7 and Figure 27) ’C30-27 NO NO. MIN 1 tsu(GPIO-H1L) Setup time, general-purpose input before H1 low 2 th(H1L-GPIO) Hold time, general-purpose input after H1 low 3 td(H1H-GPIO) Delay time, general-purpose output after H1 high ’C30-33 MAX MIN ’C30-40 MAX MIN ’C30-50 MAX MIN MAX UNIT 15 12 10 9 ns 0 0 0 0 ns 19 15 13 10 ns NOTE 7: Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The modes of these pins are defined by the contents of internal control registers associated with each peripheral. H3 H1 2 1 3 3 Peripheral Pin Figure 27. Timing for Peripheral Pin General-Purpose I/O 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 changing the peripheral pin I/O modes The following tables show the timing parameters for changing the peripheral pin from a general-purpose output pin to a general-purpose input pin and the reverse. The numbers shown in Figure 28 and Figure 29 correspond to those shown in the NO. column of the following tables. timing parameters for peripheral pin changing from general-purpose output to input mode (see Note 7 and Figure 28) ’C30-27 NO NO. 1 2 MIN th(H1H-GPIO) tsu(GPIO-H1L) Hold time, peripheral pin after H1 high ’C30-33 MAX MIN 19 Setup time, peripheral pin before H1 low 13 MAX ’C30-40 MIN 15 10 ’C30-50 MAX MIN 13 9 MAX 10 9 UNIT ns ns 3 th(H1L-GPIO) Hold time, peripheral pin after H1 low 0 0 0 0 ns NOTE 7: Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The modes of these pins are defined by the contents of internal control registers associated with each peripheral. Execution of Store of PeripheralControl Register Buffers Go From Output to Input Synchronizer Delay Value on Pin Seen in PeripheralControl Register H3 H1 2 IO Control Bit 3 1 Peripheral Pin Output Data Bit Data Sampled Data Seen Figure 28. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 47 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 timing parameters for peripheral pin changing from general-purpose input to output mode (see Note 7 and Figure 29) ’C30-27 NO NO. 1 MIN td(H1H-GPIO) Delay time, H1 high to peripheral pin switching from input to output MAX ’C30-33 MIN 19 MAX ’C30-40 MIN MAX 15 13 ’C30-50 MIN MAX 10 UNIT ns NOTE 7: Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The modes of these pins are defined by the contents of internal-control registers associated with each peripheral. Execution of Store of Peripheral-Control Register H3 H1 IO Control Bit 1 Peripheral Pin Figure 29. Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timer pin (TCLK0 and TCLK1) timing Valid logic-level periods and polarity are specified by the contents of the internal control registers. The following tables define the timing parameters for the timer pin. The numbers shown in Figure 30 correspond with those in the NO. column of the tables below. timing parameters for timer pin (TCLK0 and TCLK1) (see Figure 30)† ’C30-27† NO NO. MIN ’C30-33† MAX MIN MAX UNIT 1 tsu(TCLK-H1L) Setup time, TCLK ext before H1 low TCLK ext 15 12 ns 2 th(H1L-TCLK) Hold time, TCLK ext after H1 low TCLK ext 0 0 ns 3 td(H1H-TCLK) Delay time, H1 high to TCLK int valid TCLK int 4 tc(TCLK) (TCLK) Cycle time time, TCLK 5 tw(TCLK) (TCLK) Pulse duration, TCLK high/low TCLK ext TCLK int TCLK ext TCLK int 13 10 tc(H)×2.6 tc(H)×2 tc(H)×232‡ tc(H)×2.6 tc(H)×2 tc(H)×232‡ tc(H)+12 [tc(TCLK)/2]–15 [tc(TCLK)/2]+5 tc(H)+12 [tc(TCLK)/2]–15 [tc(TCLK)/2]+5 ’C30-40† NO NO. MIN 1 Setup time, TCLK tsu(TCLK-H1L) ext before H1 low 2 th(H1L-TCLK) 3 4 ’C30-50† MAX MIN ns ns ns UNIT MAX TCLK ext 10 8 ns Hold time, TCLK ext after H1 low TCLK ext 0 0 ns td(H1H-TCLK) Delay time, H1 high to TCLK int valid TCLK int tc(TCLK) (TCLK) Cycle time, time TCLK TCLK ext TCLK int 9 tc(H)×2.6 tc(H)×2 tc(H)×232‡ 9 tc(H)×2.6 tc(H)×2 tc(H)×232‡ ns ns tc(H)+10 tc(H)+10 ns [tc(TCLK)/2] – 5 [tc(TCLK)/2]+5 [tc(TCLK)/2] – 5 [tc(TCLK)/2]+5 † Timing parameters 1 and 2 are applicable for a synchronous input clock. Timing parameters 4 and 5 are applicable for an asynchronous input clock. ‡ Assured by design but not tested 5 tw(TCLK) (TCLK) Pulse duration, TCLK high/low TCLK ext TCLK int POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 49 TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 timer pin (TCLK0 and TCLK1) timing (continued) H3 H1 2 3 3 1 TCLK 5 4 Figure 30. Timing for Timer Pin SHZ pin timing The following table defines the timing parameter for the SHZ pin. The number shown in Figure 31 corresponds with that in the NO. column of the table below. timing parameters for SHZ pin (see Figure 31) ’C30 NO NO. 1 tdis(SHZ) Disable time, SHZ low to all outputs, I/O pins disabled (high impedance) † Characterized but not tested ‡ P = tc(CI) MIN 0† H3 H1 SHZ (see Note A) 1 All I/O Pins NOTE A: Enabling SHZ destroys TMS320C30 register and memory contents. Assert SHZ = 1 and reset the TMS320C30 to restore it to a known condition. Figure 31. Timing for SHZ 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MAX 2P†‡ UNIT ns PACKAGE OPTION ADDENDUM www.ti.com 31-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty 1 TMS320C30GEL NRND CPGA GE 181 TMS320C30GEL27 OBSOLETE CPGA GB 181 TMS320C30GEL40 NRND CPGA GE 181 TMS320C30GEL50 NRND CPGA GE 181 TMS320C30GELSD NRND CPGA GE 181 21 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TBD AU N / A for Pkg Type TBD Call TI 1 TBD AU N / A for Pkg Type 21 TBD AU N / A for Pkg Type TBD AU N / A for Pkg Type Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF TMS320C30 : • Catalog: SM320C30 Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 31-Mar-2012 • Military: SMJ320C30 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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