TMUX7348F, TMUX7349F
SCDS400B – MARCH 2022 – REVISED JULY 2023
TMUX734xF ±60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers With Adjustable
Fault Threshold, Latch-Up Immunity, and 1.8-V Logic
1 Features
3 Description
•
The TMUX7348F and TMUX7349F are modern
complementary metal-oxide semiconductor (CMOS)
analog multiplexers in 8:1 (single ended) and 4:1
(differential) configurations. The devices work well
with dual supplies (±5 V to ±22 V), a single supply (8
V to 44 V), or asymmetric supplies (such as VDD = 12
V, VSS = –5 V). The overvoltage protection is available
in powered and powered-off conditions, making the
TMUX7348F and TMUX7349F devices suitable for
applications where power supply sequencing cannot
be precisely controlled.
Wide supply range:
– Dual supply: ±5 V to ±22 V
– Single supply: 8 V to 44 V
Integrated fault protection:
– Overvoltage protection, source to supplies or
source to drain: ±85 V
– Overvoltage protection: ±60 V
– Power-off protection: ±60 V
– Adjustable overvoltage triggering thresholds
• VFP: 3 V to VDD, VFN: 0 V to VSS
– Interrupt flags to indicate overall and specific
fault channel information
– Non-fault channels continue to operate with low
leakage currents
– Output clamped to the fault supply in
overvoltage condition
Latch-up immunity by device construction
Logic capable: 1.8-V
Fail-safe logic: up to 44 V independent of supply
Break-before-make switching
Industry-standard TSSOP and smaller WQFN
package
•
•
•
•
•
•
2 Applications
•
•
•
•
•
•
•
Factory automation and control
Programmable logic controllers (PLC)
Analog input modules
Semiconductor test equipment
Battery test equipment
Servo drive control module
Data acquisition systems (DAQ)
VDD VSS
VFN VFP
VDD VSS
SW
VFN VFP
SW
S1
S1A
SW
...
S2
S4A
D
DA
SW
SW
...
S1B
...
SW
DB
A2
Fault Detecon/
Switch Driver/
Logic Decoder
EN
TMUX7348F
FF
SF
A0
A1
EN
Device Information
PART NUMBER(1)
TMUX7348F
TMUX7349F
A0
A1
The low capacitance, low charge injection, and
integrated fault protection enables the TMUX7348F
and TMUX7349F devices to be used in front end
data acquisition applications where high performance
and high robustness are both critical. The devices are
available in standard TSSOP package and smaller
WQFN package (ideal if PCB space is limited).
SW
S4B
S8
The device blocks fault voltages up to +60 V and –60
V relative to ground in both powered and powered-off
conditions. When no power supplies are present, the
switch channels remain in the OFF state regardless
of switch input conditions and logic control status.
Under normal operation conditions, if the analog input
signal level on any Sx pin exceeds positive fault
supply (VFP) or negative fault supply (VFN) by a
threshold voltage (VT), then the channel turns OFF
and the Sx pin becomes high impedance. When the
fault channel is selected, the drain pin (D or Dx) is
pulled to the fault supply voltage (VFP or VFN) that
was exceeded. The devices provide two active-low
interrupt flags (FF and SF) to provide details of the
fault. The FF flag indicates if any of the source inputs
are experiencing a fault condition, while the SF flag is
used to decode which specific inputs are experiencing
a fault condition.
Fault Detec on/
Switch Driver/
Logic Decoder
TMUX7349F
Functional Block Diagram
CONFIGURATION
1 Channel 8:1
2 Channel 4:1
PACKAGE(2)
PACKAGE SIZE(3)
PW (TSSOP, 20)
6.5 mm × 6.4 mm
RTJ (WQFN, 20)
4 mm × 4 mm
FF
SF
(1)
(2)
(3)
See Device Comparison table.
For all available packages, see the orderable addendum at
the end of the data sheet.
The package size (length × width) is a nominal value and
includes pins, where applicable.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TMUX7348F, TMUX7349F
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SCDS400B – MARCH 2022 – REVISED JULY 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Thermal Information....................................................7
7.4 Recommended Operating Conditions.........................7
7.5 Electrical Characteristics (Global)...............................8
7.6 ±15 V Dual Supply: Electrical Characteristics.............9
7.7 ±20 V Dual Supply: Electrical Characteristics...........12
7.8 12 V Single Supply: Electrical Characteristics.......... 15
7.9 36 V Single Supply: Electrical Characteristics.......... 18
7.10 Typical Characteristics............................................ 21
8 Parameter Measurement Information.......................... 28
8.1 On-Resistance.......................................................... 28
8.2 Off-Leakage Current................................................. 28
8.3 On-Leakage Current................................................. 29
8.4 Input and Output Leakage Current Under
Overvoltage Fault........................................................ 29
8.5 Break-Before-Make Delay.........................................30
8.6 Enable Delay Time....................................................31
8.7 Transition Time......................................................... 31
8.8 Fault Response Time................................................ 32
8.9 Fault Recovery Time................................................. 32
8.10 Fault Flag Response Time...................................... 33
8.11 Fault Flag Recovery Time....................................... 33
8.12 Charge Injection......................................................34
8.13 Off Isolation.............................................................34
8.14 Crosstalk................................................................. 35
8.15 Bandwidth............................................................... 36
8.16 THD + Noise........................................................... 36
9 Detailed Description......................................................37
9.1 Overview................................................................... 37
9.2 Functional Block Diagram......................................... 37
9.3 Feature Description...................................................38
9.4 Device Functional Modes..........................................41
10 Application and Implementation................................ 44
10.1 Application Information........................................... 44
10.2 Typical Application.................................................. 44
10.3 Power Supply Recommendations...........................46
10.4 Layout..................................................................... 46
11 Device and Documentation Support..........................49
11.1 Documentation Support.......................................... 49
11.2 Receiving Notification of Documentation Updates.. 49
11.3 Support Resources................................................. 49
11.4 Trademarks............................................................. 49
11.5 Electrostatic Discharge Caution.............................. 49
11.6 Glossary.................................................................. 49
12 Mechanical, Packaging, and Orderable
Information.................................................................... 49
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2022) to Revision B (July 2023)
Page
• Updated the Device Information table to include configuration and package size............................................. 1
• Changed the status of the TSSOP (20) package for the TMUX734xF device from: Preview to: Active ........... 1
Changes from Revision * (April 2022) to Revision A (November 2022)
Page
• Changed the status of the WQFN (20) package for the TMUX734xF device from: Preview to: Active .............1
2
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SCDS400B – MARCH 2022 – REVISED JULY 2023
5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX7348F
+60 V/ –60 V tolerant, fault-protected, latch-up immune, single-ended 8:1 multiplexers with adjustable fault threshold
TMUX7349F
+60 V/ –60 V tolerant, fault-protected, latch-up immune, dual 4:1 multiplexers with adjustable fault threshold
4
17
VDD
3
13
S6
S3
4
12
S7
S4
5
11
S8
Pad
S8
VFN
9
12
VFP
10
11
FF
10
13
VFP
8
9
S7
D
SF
S2
S6
FF
14
Thermal
8
7
S5
S5
7
15
VDD
14
SF
6
15
2
VFN
S4
16
1
S1
6
S3
5
VSS
D
S2
GND
GND
S1
16
A2
18
A2
19
3
A1
2
17
EN
VSS
A0
A1
18
20
19
1
EN
A0
20
6 Pin Configuration and Functions
Not to scale
Not to scale
Figure 6-1. PW Package, 20-Pin TSSOP (Top View)
Figure 6-2. RTJ Package, 20-Pin WQFN (Top View)
Table 6-1. Pin Functions: TMUX7348F
PIN
NAME
TYPE(1)
DESCRIPTION
TSSOP
WQFN
A0
1
19
I
Logic control input address 0 (A0). The pin has a 4-MΩ internal pull-down resistor. This pin can
also be used together with the specific fault pin (SF) to indicate which input is under fault. For more
details, see Section 9.4.3.
A1
20
18
I
Logic control input address 1 (A1). The pin has a 4-MΩ internal pull-down resistor. This pin can
also be used together with the specific fault pin (SF) to indicate which input is under fault. For more
details, see Section 9.4.3.
A2
19
17
I
Logic control input address 2 (A2). The pin has a 4-MΩ internal pull-down resistor. This pin can
also be used together with the specific fault pin (SF) to indicate which input is under fault. For more
details, see Section 9.4.3.
D
8
6
I/O
EN
2
20
I
Active high logic enable (EN) pin. The pin has a 4-MΩ internal pull-down resistor. The device is
disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax
logic inputs determine individual switch states. For more details, see Section 9.4.3.
FF
11
9
O
General fault flag. This pin is an open drain output and is asserted low when overvoltage condition is
detected on any of the source (Sx) input pins. Connect this pin to an external supply (1.8 V to 5.5 V)
through a 1-kΩ pull-up resistor.
GND
18
16
P
Ground (0 V) reference.
S1
4
2
I/O
Overvoltage protected source pin 1. Can be an input or output.
S2
5
3
I/O
Overvoltage protected source pin 2. Can be an input or output.
S3
6
4
I/O
Overvoltage protected source pin 3. Can be an input or output.
S4
7
5
I/O
Overvoltage protected source pin 4. Can be an input or output.
S5
16
14
I/O
Overvoltage protected source pin 5. Can be an input or output.
S6
15
13
I/O
Overvoltage protected source pin 6. Can be an input or output.
S7
14
12
I/O
Overvoltage protected source pin 7. Can be an input or output.
S8
13
11
I/O
Overvoltage protected source pin 8. Can be an input or output.
SF
10
8
O
Specific fault flag. Table 9-1 shows how this pin is an open drain output and is asserted low when
overvoltage condition is detected on a specific pin, depending on the state of A0, A1, and A2.
Connect this pin to an external supply (1.8 V to 5.5 V) through a 1-kΩ pull-up resistor.
Drain pin. Can be an input or output. The drain pin is not overvoltage protected and shall remain
within the recommended operating range.
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SCDS400B – MARCH 2022 – REVISED JULY 2023
Table 6-1. Pin Functions: TMUX7348F (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
TSSOP
WQFN
VDD
17
15
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VFN
9
7
P
Negative fault voltage supply that determines the overvoltage protection triggering threshold on the
negative side. Connect to VSS if the triggering threshold will be the same as the device's negative
supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between
VFN and GND.
VFP
12
10
P
Positive fault voltage supply that determines the overvoltage protection triggering threshold on the
positive side. Connect to VDD if the triggering threshold will be the same as the device's positive
supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between
VFP and GND.
VSS
3
1
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
—
Thermal pad. The thermal pad is not connected internally. It is recommended that the pad be tied to
GND or VSS for best performance.
Thermal Pad
EN
A0
A1
GND
VDD
19
18
17
16
I = input, O = output, I/O = input and output, P = power
20
(1)
A0
1
20
A1
EN
2
19
GND
VSS
3
18
VDD
S1A
4
17
S1B
VSS
1
15
S1B
S2B
S1A
2
14
S2B
S2A
5
16
Thermal
S3A
6
15
S3B
S2A
3
13
S3B
S4A
7
14
S4B
S3A
4
12
S4B
DA
8
13
DB
S4A
5
11
DB
VFN
9
12
VFP
10
11
FF
6
7
8
9
10
DA
SF
FF
VFP
SF
VFN
Pad
Not to scale
Not to scale
Figure 6-3. PW Package, 20-Pin TSSOP (Top View)
Figure 6-4. RTJ Package, 20-Pin WQFN (Top View)
Table 6-2. Pin Functions: TMUX7349F
PIN
TYPE(1)
DESCRIPTION
19
I
Logic control input address 0 (A0). The pin has a 4-MΩ internal pull-down resistor. This pin can also
be used together with the specific fault pin (SF) to indicate which input is under fault. For more details,
see Section 9.4.3.
20
18
I
Logic control input address 1 (A1). The pin has a 4-MΩ internal pull-down resistor. This pin can also
be used together with the specific fault pin (SF) to indicate which input is under fault. For more details,
see Section 9.4.3.
DA
8
6
I/O
Drain terminal A. Can be an input or output. The drain pin is not overvoltage protected and shall
remain within the recommended operating range.
DB
13
11
I/O
Drain terminal B. Can be an input or output. The drain pin is not overvoltage protected and shall
remain within the recommended operating range.
EN
2
20
I
Active high logic enable (EN) pin. The pin has a 4-MΩ internal pull-down resistor. The device is
disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax
logic inputs determine individual switch states. This pin can also be used together with the specific
fault pin (SF) to indicate which input is under fault. For more details, see Section 9.4.3.
FF
11
9
O
General fault flag. This pin is an open drain output and is asserted low when overvoltage condition is
detected on any of the source (Sx) input pins. Connect this pin to an external supply (1.8 V to 5.5 V)
through a 1-kΩ pull-up resistor.
GND
19
17
P
Ground (0 V) reference
NAME
4
TSSOP
WQFN
A0
1
A1
S1A
4
2
I/O
Overvoltage protected source pin 1A. Can be an input or output.
S1B
17
15
I/O
Overvoltage protected source pin 1B. Can be an input or output.
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SCDS400B – MARCH 2022 – REVISED JULY 2023
Table 6-2. Pin Functions: TMUX7349F (continued)
PIN
NAME
TSSOP
WQFN
TYPE(1)
DESCRIPTION
S2A
5
3
I/O
Overvoltage protected source pin 2A. Can be an input or output.
S2B
16
14
I/O
Overvoltage protected source pin 2B. Can be an input or output.
S3A
6
4
I/O
Overvoltage protected source pin 3A. Can be an input or output.
S3B
15
13
I/O
Overvoltage protected source pin 3B. Can be an input or output.
S4A
7
5
I/O
Overvoltage protected source pin 4A. Can be an input or output.
S4B
14
12
I/O
Overvoltage protected source pin 4B. Can be an input or output.
SF
10
8
O
Specific fault flag. Table 9-2 provides how this pin is an open drain output and is asserted low when
overvoltage condition is detected on a specific pin, depending on the state of A0, A1, and EN. Connect
this pin to an external supply (1.8 V to 5.5 V) through a 1-kΩ pull-up resistor.
VDD
18
16
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VFN
9
7
P
Negative fault voltage supply that determines the overvoltage protection triggering threshold on the
negative side. Connect to VSS if the triggering threshold will be the same as the device's negative
supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between
VFN and GND.
VFP
12
10
P
Positive fault voltage supply that determines the overvoltage protection triggering threshold on the
positive side. Connect to VDD if the triggering threshold will be the same as the device's positive
supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between
VFP and GND.
VSS
3
1
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
—
Thermal pad. The thermal pad is not connected internally. It is recommended to tie the pad to GND or
VSS for best performance.
Thermal Pad
(1)
I = input, O = output, I/O = input and output, P = power
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VDD to VSS
VDD to GND
48
V
48
V
–48
0.3
V
–0.3
VDD + 0.3
V
VSS – 0.3
0.3
V
–65
65
V
Supply voltage
–0.3
VFP to GND
Positive fault clamping voltage
VFN to GND
Negative fault clamping voltage
VS to GND
Source input pin (Sx) voltage to GND
VS to VDD
Source input pin (Sx) voltage to VDD
–90
VS to VSS
Source input pin (Sx) voltage to VSS
VD
Drain pin (D or Dx) voltage
VEN or VAx
Logic control input pin voltage (EN, A0, A1, A2)(2)
VSS to GND
voltage(2)
VxF
Logic output pin (SF, FF)
IEN or IAx
Logic control input pin current (EN, A0, A1, A2)(2)
IxF
Logic output pin (SF, FF) current(2)
IS or ID (CONT)
Source or drain continuous current (Sx or D)
Tstg
TA
TJ
Junction temperature
Ptot (4)
Total power dissipation (QFN)
Ptot (5)
Total power dissipation (TSSOP)
(1)
(2)
(3)
(4)
(5)
UNIT
V
90
V
VFN–0.7
VFP+0.7
V
GND –0.7
48
V
GND –0.7
6
V
–30
30
mA
–10
10
mA
IDC ± 10 %(3)
IDC ± 10 %(3)
mA
Storage temperature
–65
150
°C
Ambient temperature
–55
150
°C
150
°C
1900
mW
800
mW
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
Stresses have to be kept at or below both voltage and current ratings at all time.
Refer to Recommended Operating Conditions for IDC ratings.
For QFN package: Ptot derates linearly above TA = 70°C by 28.5 mW/°C
For TSSOP package: Ptot derates linearly above TA = 70°C by 12.0 mW/°C
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
6
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±3500
Charged device model (CDM), per JEDEC specification JESD22C101 or ANSI/ESDA/JEDEC JS-002(2)
±750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible if necessary precautions are taken.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible if necessary precautions are taken.
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7.3 Thermal Information
TMUX7348F/ TMUX7349F
THERMAL
METRIC(1)
PW (TSSOP)
RTJ (WQFN)
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
84.3
35.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.7
28.3
°C/W
RθJB
Junction-to-board thermal resistance
37.3
13.5
°C/W
ΨJT
Junction-to-top characterization parameter
1.0
0.3
°C/W
ΨJB
Junction-to-board characterization parameter
36.7
13.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
4.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD – VSS (1)
Power supply voltage differential
8
VDD
Positive power supply voltage
VFP
Positive fault clamping voltage
VFN
Negative fault clamping voltage
VS
Source pin (Sx) voltage (non-fault condition)
VS to GND
Source pin (Sx) voltage (fault condition)
VS to VDD (2)
Source pin (Sx) voltage to VDD or VD (fault condition)
Source pin (Sx) voltage
to VDD or VD (fault
condition)
VS to VSS (2)
Source pin (Sx) voltage to VSS or VD (fault condition)
Source pin (Sx) voltage
to VSS or VD (fault
condition)
VD
Drain pin (D, Dx) voltage
VEN or VAx
Logic control input pin voltage (EN, A0, A1, A2)
VxF
Logic output pin (SF, FF) voltage
TA
Ambient temperature
IDC (3)
Continuous current through switch
(3)
MAX
UNIT
44
V
5
44
V
3
VDD
V
VSS
0
V
VFN
VFP
V
–60
60
V
–85
V
85
V
VFN
VFP
V
0
44
V
0
5.5
V
–40
125
°C
TA = 25°C
9
TA = 85°C
6.5
TA = 125°C
(1)
(2)
NOM
mA
5
VDD and VSS can be any value as long as 8 V ≤ (VDD – VSS) ≤ 44 V.
Under a fault condition, the potential difference between source pin (Sx) and supply pins (VDD and VSS.) or source pin (Sx) and drain
pins (D, Dx) may not exceed 85 V.
Fault supplies are tied to the primary supplies (VFP= VDD, VFN = VSS)
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7.5 Electrical Characteristics (Global)
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
Threshold voltage for fault
detector
VT
25°C
0.7
V
LOGIC INPUT/ OUTPUT
VIH
High-level input voltage
EN, Ax pins
–40°C to +125°C
1.3
VIL
Low-level input voltage
EN, Ax pins
–40°C to +125°C
0
VOL(FLAG)
Low-level output voltage
FF and SF pins, IO = 5 mA
–40°C to +125°C
Rising edge, single supply
–40°C to +125°C
5.1
Falling edge, single supply
–40°C to +125°C
5
Single supply
–40°C to +125°C
44
V
0.8
V
0.35
V
6
6.4
V
5.8
6.3
V
POWER SUPPLY
8
VUVLO
Undervoltage lockout (UVLO)
threshold voltage (VDD – VSS)
VHYS
VDD Undervoltage
lockout (UVLO) hysteresis
RD(OVP)
Drain resistance to supply rail during overvoltage event on selected source pin 25°C
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0.2
V
40
kΩ
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: TMUX7348F TMUX7349F
TMUX7348F, TMUX7349F
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
180
250
UNIT
ANALOG SWITCH
25°C
RON
On-resistance
VS = –10 V to +10 V,
IS = –1 mA
–40°C to +85°C
330
–40°C to +125°C
390
25°C
ΔRON
On-resistance mismatch between VS = –10 V to +10 V,
channels
IS = –1 mA
2.5
–40°C to +85°C
On-resistance flatness
1.5
3.5
VS = –10 V to +10 V,
IS = –1 mA
–40°C to +85°C
4
–40°C to +125°C
4
RON_DRIFT
On-resistance drift
VS = 0 V, IS = –1 mA
–40°C to +125°C
–1
Source off leakage current(1)
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
25°C
IS(OFF)
–40°C to +85°C
–1
1
–40°C to +125°C
–4
4
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
25°C
–1
–40°C to +85°C
–3
ID(OFF)
IS(ON)
ID(ON)
Drain off leakage current(1)
Output on leakage current(2)
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
Ω
13
25°C
RFLAT
8
12
–40°C to +125°C
Ω
1
–40°C to +125°C
–14
25°C
–1.5
0.1
0.1
Ω
Ω/°C
1
nA
1
3
nA
14
0.3
1.5
–40°C to +85°C
–5
5
–40°C to +125°C
–22
22
nA
FAULT CONDITION
IS(FA)
Input leakage current
durring overvoltage
VS = ± 60 V, GND = 0 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V
–40°C to +125°C
±110
µA
IS(FA) Grounded
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
–40°C to +125°C
±135
µA
IS(FA) Floating
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
–40°C to +125°C
±135
µA
ID(FA)
Output leakage current
during overvoltage
VS = ± 60 V, GND = 0 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
–15.5 V ≤ VD ≤ 16.5 V
ID(FA) Grounded
ID(FA) Floating
25°C
–50
–40°C to +85°C
–70
70
–40°C to +125°C
–90
90
25°C
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
–50
±10
±1
50
50
–40°C to +85°C
–100
100
–40°C to +125°C
–500
500
25°C
±3
–40°C to +85°C
±5
–40°C to +125°C
±8
nA
nA
µA
LOGIC INPUT/ OUTPUT
IIH
High-level input current
VEN = VAx = VDD
IIL
Low-level input current
VEN = VAx = 0 V
25°C
–2
–40°C to +125°C
–2
25°C
–1.1
–40°C to +125°C
–1.2
± 0.6
2
2
± 0.6
1.1
1.2
µA
µA
SWITCHING CHARACTERISTICS
25°C
tON (EN)
Enable turn-on time
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
165
265
–40°C to +85°C
285
–40°C to +125°C
300
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ns
9
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.6 ±15 V Dual Supply: Electrical Characteristics (continued)
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
25°C
tOFF (EN)
Enable turn-off time
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
Transition time
MAX
350
400
–40°C to +85°C
400
–40°C to +125°C
420
25°C
tTRAN
TYP
170
UNIT
ns
225
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
245
–40°C to +125°C
260
ns
tRESPONSE
Fault response time
VFP = 15 V, VFN = –15 V,
RL = 4 kΩ, CL= 12 pF
25°C
300
ns
tRECOVERY
Fault recovery time
VFP = 15 V, VFN = –15 V,
RL = 4 kΩ, CL= 12 pF
25°C
1.4
µs
tRESPONSE(FLAG)
Fault flag response time
VFP = 15 V, VFN = –15 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
25°C
110
ns
tRECOVERY(FLAG) Fault flag recovery time
VFP = 15 V, VFN = –15 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
25°C
0.9
µs
tBBM
Break-before-make time delay
VS = 10 V, RL = 4 kΩ, CL= 12 pF
–40°C to +125°C
120
ns
QINJ
Charge injection
VS = 0 V, CL = 1 nF
25°C
–15
pC
OISO
Off-isolation
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
25°C
–82
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200
mVRMS, VBIAS = 0 V, f = 1 MHz
25°C
Intra-channel crosstalk
XTALK
Inter-channel crosstalk
(TMUX7349F)
–95
–3 dB bandwidth (TMUX7348F)
–3 dB bandwidth (TMUX7349F
WQFN Package)
BW
–3 dB bandwidth (TMUX7349F
TSSOP Package)
50
–103
dB
150
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
25°C
280
MHz
240
ILOSS
Insertion loss
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
25°C
–9
dB
THD+N
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10 kΩ, VS = 15 VPP, VBIAS
25°C
= 0 V, f = 20 Hz to 20 kHz
0.0014
%
CS(OFF)
Input off-capacitance
f = 1 MHz, VS = 0 V
25°C
3.5
pF
Output off-capacitance
(TMUX7348F)
f = 1 MHz, VS = 0 V
25°C
28
pF
Output off-capacitance
(TMUX7349F)
f = 1 MHz, VS = 0 V
25°C
15
pF
Input/Output on-capacitance
(TMUX7348F)
f = 1 MHz, VS = 0 V
25°C
30
pF
Input/Output on-capacitance
(TMUX7349F)
f = 1 MHz, VS = 0 V
25°C
17
pF
CD(OFF)
CS(ON)
CD(ON)
10
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TMUX7348F, TMUX7349F
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.6 ±15 V Dual Supply: Electrical Characteristics (continued)
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
0.24
0.5
UNIT
POWER SUPPLY
25°C
IDD
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
VDD supply current
–40°C to +85°C
0.5
–40°C to +125°C
0.5
25°C
0.14
mA
0.4
VSS supply current
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
–40°C to +85°C
0.4
–40°C to +125°C
0.4
IGND
GND current
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
0.075
mA
IFP
VFP supply current
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
10
µA
IFN
VFN supply current
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
10
µA
0.25
VDD supply current under fault
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
IDD(FA)
ISS
1
–40°C to +85°C
1
–40°C to +125°C
1
25°C
0.15
mA
mA
0.5
VSS supply current under fault
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND(FA)
GND current under fault
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
0.15
mA
IFP(FA)
VFP supply current under fault
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
9
µA
IFN(FA)
VFN supply current under fault
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
9
µA
25°C
0.15
IDD(DISABLE)
VDD supply current (disable mode)
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
ISS(FA)
–40°C to +85°C
0.5
–40°C to +125°C
0.5
(1)
(2)
VSS supply current (disable mode)
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
0.5
–40°C to +85°C
0.5
–40°C to +125°C
0.5
25°C
ISS(DISABLE)
0.1
mA
mA
0.4
–40°C to +85°C
0.4
–40°C to +125°C
0.4
mA
When VS is positive,VD is negative. And when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.7 ±20 V Dual Supply: Electrical Characteristics
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
180
250
UNIT
ANALOG SWITCH
25°C
RON
On-resistance
VS = –15 V to +15 V,
IS = –1 mA
–40°C to +85°C
330
–40°C to +125°C
390
25°C
On-resistance mismatch between VS = –15 V to +15 V,
channels
IS = –1 mA
ΔRON
2.5
–40°C to +85°C
On-resistance flatness
VS = –15 V to +15 V,
IS = –1 mA
8
12
–40°C to +125°C
12
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
1.5
–40°C to +85°C
4
–40°C to +125°C
4
On-resistance drift
VS = 0 V, IS = –1 mA
–40°C to +125°C
25°C
–1
Source off leakage current(1)
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
VD = –15 V / + 15 V
–40°C to +85°C
–1
–40°C to +125°C
–4
25°C
–1
Drain off leakage current(1)
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
VD = –15 V / + 15 V
–40°C to +85°C
–3
3
–40°C to +125°C
–14
14
25°C
–1.5
Output on leakage current(2)
VDD = 22 V, VSS = –22 V
Switch state is on
VS = VD = ±15 V
1
0.1
Ω
3.5
VS = –13.5 V to +13.5 V,
IS = –1 mA
On-resistance flatness
RON_DRIFT
10
–40°C to +85°C
25°C
RFLAT
Ω
13
25°C
RFLAT
8
12
–40°C to +125°C
Ω
Ω
Ω/°C
1
1
nA
4
0.1
0.3
1
nA
1.5
–40°C to +85°C
–5
5
–40°C to +125°C
–22
22
nA
FAULT CONDITION
IS(FA)
Input leakage current
durring overvoltage
VS = ± 60 V, GND = 0 V,
VDD = VFP = 22 V, VSS = VFN = –22 V
–40°C to +125°C
±95
µA
IS(FA) Grounded
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
–40°C to +125°C
±135
µA
IS(FA) Floating
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
–40°C to +125°C
±135
µA
ID(FA)
Output leakage current
during overvoltage
VS = ± 60 V, GND = 0 V,
VDD = VFP = 22 V, VSS = VFN = –22 V
–21 V ≤ VD ≤ 22 V
ID(FA) Grounded
ID(FA) Floating
25°C
–50
–40°C to +85°C
–70
70
–40°C to +125°C
–90
90
25°C
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
–50
±10
±1
50
50
–40°C to +85°C
–100
100
–40°C to +125°C
–500
500
25°C
±3
–40°C to +85°C
±5
–40°C to +125°C
±8
nA
nA
µA
LOGIC INPUT/ OUTPUT
IIH
High-level input current
VEN = VAx = VDD
IIL
Low-level input current
VEN = VAx = 0 V
12
25°C
–2.2
–40°C to +125°C
–2.2
25°C
–1.1
–40°C to +125°C
–1.2
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± 0.6
2.2
2.2
± 0.6
1.1
1.2
µA
µA
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Product Folder Links: TMUX7348F TMUX7349F
TMUX7348F, TMUX7349F
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.7 ±20 V Dual Supply: Electrical Characteristics (continued)
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
175
300
UNIT
SWITCHING CHARACTERISTICS
25°C
tON (EN)
Enable turn-on time
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
325
–40°C to +125°C
350
25°C
tOFF (EN)
Enable turn-off time
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
350
–40°C to +85°C
Transition time
ns
420
25°C
tTRAN
400
400
–40°C to +125°C
ns
170
245
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
270
–40°C to +125°C
285
ns
tRESPONSE
Fault response time
VFP = 20 V, VFN = –20 V,
RL = 4 kΩ, CL= 12 pF
25°C
300
ns
tRECOVERY
Fault recovery time
VFP = 20 V, VFN = –20 V,
RL = 4 kΩ, CL= 12 pF
25°C
1.3
µs
tRESPONSE(FLAG)
Fault flag response time
VFP = 20 V, VFN = –20 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
25°C
110
ns
tRECOVERY(FLAG) Fault flag recovery time
VFP = 20 V, VFN = –20 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
25°C
0.9
µs
tBBM
Break-before-make time delay
VS = 10 V, RL = 4 kΩ, CL= 12 pF
–40°C to +125°C
120
ns
QINJ
Charge injection
VS = 0 V, CL = 1 nF
25°C
–17
pC
OISO
Off-isolation
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
25°C
–85
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
25°C
Intra-channel crosstalk
XTALK
Inter-channel crosstalk
(TMUX7349F)
–95
–3 dB bandwidth (TMUX7348F)
BW
–3 dB bandwidth (TMUX7349F
WQFN Package)
–3 dB bandwidth (TMUX7349F
TSSOP Package)
50
dB
–103
150
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
25°C
285
MHz
245
ILOSS
Insertion loss
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
25°C
–9
dB
THD+N
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10 kΩ, VS = 20 VPP, VBIAS
25°C
= 0 V, f = 20 Hz to 20 kHz
0.0014
%
CS(OFF)
Input off-capacitance
f = 1 MHz, VS = 0 V
25°C
3.5
pF
Output off-capacitance
(TMUX7348F)
f = 1 MHz, VS = 0 V
25°C
28
Output off-capacitance
(TMUX7349F)
f = 1 MHz, VS = 0 V
25°C
14
Input/Output on-capacitance
(TMUX7348F)
f = 1 MHz, VS = 0 V
25°C
30
Input/Output on-capacitance
(TMUX7349F)
f = 1 MHz, VS = 0 V
25°C
16
25°C
0.24
CD(OFF)
CS(ON)
CD(ON)
pF
pF
POWER SUPPLY
IDD
VDD supply current
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
0.5
–40°C to +125°C
0.5
25°C
ISS
IGND
VSS supply current
GND current
0.5
–40°C to +85°C
0.14
0.4
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
–40°C to +85°C
0.4
–40°C to +125°C
0.4
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
0.075
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mA
mA
mA
13
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.7 ±20 V Dual Supply: Electrical Characteristics (continued)
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
IFP
VFP supply current
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
10
µA
IFN
VFN supply current
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
10
µA
0.25
VDD supply current under fault
VS = ± 60 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
IDD(FA)
ISS(FA)
VSS supply current under fault
VS = ± 60 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
1
–40°C to +85°C
1
–40°C to +125°C
1
25°C
0.15
mA
0.5
–40°C to +85°C
0.5
–40°C to +125°C
0.5
mA
IGND(FA)
GND current under fault
VS = ± 60 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
0.15
mA
IFP(FA)
VFP supply current under fault
VS = ± 60 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
9
µA
IFN(FA)
VFN supply current under fault
VS = ± 60 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
9
µA
25°C
0.15
IDD(DISABLE)
V = VFP = 22 V, VSS = VFN = –22 V,
VDD supply current (disable mode) DD
VAx = 0 V, 5 V, or VDD, VEN = 0 V
0.5
mA
–40°C to +85°C
0.5
mA
–40°C to +125°C
0.5
mA
0.4
mA
–40°C to +85°C
0.4
mA
–40°C to +125°C
0.4
mA
25°C
ISS(DISABLE)
(1)
(2)
14
VSS supply current (disable mode)
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
0.1
When VS is positive,VD is negative. And when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.8 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
180
250
UNIT
ANALOG SWITCH
25°C
RON
On-resistance
VS = 0 V to 7.8 V,
IS = –1 mA
–40°C to +85°C
330
–40°C to +125°C
390
25°C
ΔRON
On-resistance mismatch between VS = 0 V to 7.8 V,
channels
IS = –1 mA
2.5
–40°C to +85°C
On-resistance flatness
VS = 0 V to 7.8 V,
IS = –1 mA
7
RON_DRIFT
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
30
–40°C to +85°C
45
–40°C to +125°C
75
25°C
RFLAT
1.5
–40°C to +85°C
8
–40°C to +125°C
8
On-resistance drift
VS = 6 V, IS = –1 mA
–40°C to +125°C
25°C
–1
Source off leakage current(1)
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
VD = 1 V / 10 V
–40°C to +85°C
–1
–40°C to +125°C
–4
25°C
–1
Drain off leakage current(1)
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
VD = 1 V / 10 V
–40°C to +85°C
–3
3
–40°C to +125°C
–14
14
25°C
–1.5
Output on leakage current(2)
VDD = 13.2 V, VSS = 0 V
Switch state is on
VS = VD = 10 V or 1 V
1
0.1
Ω
7
VS = 1 V to 7.8 V,
IS = –1 mA
On-resistance flatness
Ω
13
25°C
RFLAT
8
12
–40°C to +125°C
Ω
Ω
Ω/°C
1
1
nA
4
0.1
0.3
1
nA
1.5
–40°C to +85°C
–5
5
–40°C to +125°C
–22
22
nA
FAULT CONDITION
IS(FA)
Input leakage current
durring overvoltage
VS = ± 60 V, GND = 0 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V
–40°C to +125°C
±145
µA
IS(FA) Grounded
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
–40°C to +125°C
±135
µA
IS(FA) Floating
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
–40°C to +125°C
±135
µA
ID(FA)
Output leakage current
during overvoltage
VS = ± 60 V, GND = 0 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V
1 V ≤ VD ≤ 13.2 V
ID(FA) Grounded
ID(FA) Floating
25°C
–50
–40°C to +85°C
–70
70
–40°C to +125°C
–90
90
25°C
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
–50
±10
±1
50
50
–40°C to +85°C
–100
100
–40°C to +125°C
–500
500
25°C
±3
–40°C to +85°C
±5
–40°C to +125°C
±8
nA
nA
µA
LOGIC INPUT/ OUTPUT
IIH
IIL
High-level input current
Low-level input current
VEN = VAx = VDD
VEN = VAx = 0 V
25°C
–2
–40°C to +125°C
–2
25°C
–1.1
–40°C to +125°C
–1.2
± 0.6
± 0.6
2
µA
2
µA
1.1
1.2
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µA
15
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.8 12 V Single Supply: Electrical Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
160
265
UNIT
SWITCHING CHARACTERISTICS
25°C
tON (EN)
Enable turn-on time
VS = 8 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
285
–40°C to +125°C
300
25°C
tOFF (EN)
Enable turn-off time
VS = 8 V,
RL = 4 kΩ, CL= 12 pF
420
–40°C to +85°C
Transition time
ns
500
25°C
tTRAN
485
485
–40°C to +125°C
ns
160
215
VS = 8 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
230
–40°C to +125°C
240
ns
tRESPONSE
Fault response time
VFP = 12 V, VFN = 0 V,
RL = 4 kΩ, CL= 12 pF
25°C
220
ns
tRECOVERY
Fault recovery time
VFP = 12 V, VFN = 0 V,
RL = 4 kΩ, CL= 12 pF
25°C
0.69
µs
tRESPONSE(FLAG)
Fault flag response time
VFP = 12 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
25°C
110
ns
tRECOVERY(FLAG) Fault flag recovery time
VFP = 12 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
25°C
0.65
µs
tBBM
Break-before-make time delay
VS = 8 V, RL = 4 kΩ, CL= 12 pF
–40°C to +125°C
90
ns
QINJ
Charge injection
VS = 6 V, CL = 1 nF
25°C
–11
pC
OISO
Off-isolation
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
25°C
–76
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
25°C
Intra-channel crosstalk
XTALK
Inter-channel crosstalk
(TMUX7349F)
–93
BW
–3 dB bandwidth (TMUX7349F
TSSOP Package)
dB
–103
–3 dB bandwidth (TMUX7348F)
–3 dB bandwidth (TMUX7349F
WQFN Package)
30
130
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V
250
25°C
MHz
218
ILOSS
Insertion loss
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
25°C
–9
dB
THD+N
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10 kΩ, VS = 6 VPP, VBIAS =
25°C
6 V, f = 20 Hz to 20 kHz
0.0022
%
CS(OFF)
Input off-capacitance
f = 1 MHz, VS = 6 V
25°C
4
pF
Output off-capacitance
(TMUX7348F)
f = 1 MHz, VS = 6 V
25°C
31
Output off-capacitance
(TMUX7349F)
f = 1 MHz, VS = 6 V
25°C
16
Input/Output on-capacitance
(TMUX7348F)
f = 1 MHz, VS = 6 V
25°C
34
Input/Output on-capacitance
(TMUX7349F)
f = 1 MHz, VS = 6 V
25°C
20
25°C
0.24
CD(OFF)
CS(ON)
CD(ON)
pF
pF
POWER SUPPLY
IDD
VDD supply current
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
0.5
–40°C to +125°C
0.5
25°C
ISS
IGND
16
VSS supply current
GND current
0.5
–40°C to +85°C
0.14
0.4
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
–40°C to +85°C
0.4
–40°C to +125°C
0.4
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
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mA
mA
mA
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.8 12 V Single Supply: Electrical Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
IFP
VFP supply current
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
10
µA
IFN
VFN supply current
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
10
µA
0.25
VDD supply current under fault
VS = ± 60 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
IDD(FA)
ISS(FA)
VSS supply current under fault
VS = ± 60 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
1
–40°C to +85°C
1
–40°C to +125°C
1
25°C
0.15
mA
0.5
–40°C to +85°C
0.5
–40°C to +125°C
0.5
mA
IGND(FA)
GND current under fault
VS = ± 60 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
0.17
mA
IFP(FA)
VFP supply current under fault
VS = ± 60 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
9
µA
IFN(FA)
VFN supply current under fault
VS = ± 60 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
7.5
µA
25°C
0.15
IDD(DISABLE)
V = VFP = 13.2 V, VSS = VFN = 0 V,
VDD supply current (disable mode) DD
VAx = 0 V, 5 V, or VDD, VEN = 0 V
–40°C to +85°C
0.5
–40°C to +125°C
0.5
25°C
ISS(DISABLE)
(1)
(2)
VSS supply current (disable mode)
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
0.5
0.1
mA
0.4
–40°C to +85°C
0.4
–40°C to +125°C
0.4
mA
When VS is 10 V, VD is 1 V. Or when VS is 1 V, VD is 10 V.
When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.9 36 V Single Supply: Electrical Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
180
250
UNIT
ANALOG SWITCH
25°C
RON
On-resistance
VS = 0 V to 28 V,
IS = –1 mA
–40°C to +85°C
330
–40°C to +125°C
390
25°C
On-resistance mismatch between VS = 0 V to 28 V,
channels
IS = –1 mA
ΔRON
2.5
–40°C to +85°C
On-resistance flatness
VS = 0 V to 30 V,
IS = –1 mA
8
–40°C to +85°C
90
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
1.5
3
VS = 1 V to 28 V,
IS = –1 mA
–40°C to +85°C
On-resistance drift
VS = 18 V, IS = –1 mA
–40°C to +125°C
25°C
–1
Source off leakage current(1)
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
VD = 1 V / 30 V
–40°C to +85°C
–1
–40°C to +125°C
–4
25°C
–1
Output on leakage current(2)
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
VD = 1 V / 30 V
–40°C to +85°C
–3
3
–40°C to +125°C
–14
14
25°C
–1.5
On-resistance flatness
RON_DRIFT
65
75
–40°C to +125°C
25°C
RFLAT
Output on leakage current(1)
VDD = 39.6 V, VSS = 0 V
Switch state is on
VS = VD = 30 V or 1 V
Ω
13
25°C
RFLAT
8
12
–40°C to +125°C
Ω
Ω
4
–40°C to +125°C
4
1
0.1
Ω/°C
1
1
nA
4
0.1
0.3
1
nA
1.5
–40°C to +85°C
–5
5
–40°C to +125°C
–22
22
nA
FAULT CONDITION
IS(FA)
Input leakage current
durring overvoltage
VS = 60 / –40 V, GND = 0 V
VDD = VFP = 39.6 V, VSS = VFN = 0 V
–40°C to +125°C
±110
µA
IS(FA) Grounded
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V
VDD = VSS = VFP = VFN= 0 V
–40°C to +125°C
±135
µA
IS(FA) Floating
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V
VDD = VSS = VFP = VFN= floating
–40°C to +125°C
±135
µA
ID(FA)
Output leakage current
during overvoltage
VS = 60 / –40 V, GND = 0 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V
1 V ≤ VD ≤ 39.6 V
ID(FA) Grounded
ID(FA) Floating
25°C
–50
–40°C to +85°C
–70
70
–40°C to +125°C
–90
90
25°C
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
–50
±10
±1
50
50
–40°C to +85°C
–100
100
–40°C to +125°C
–500
500
25°C
±3
–40°C to +85°C
±5
–40°C to +125°C
±8
nA
nA
µA
LOGIC INPUT/ OUTPUT
IIH
High-level input current
VEN = VAx = VDD
IIL
Low-level input current
VEN = VAx = 0 V
18
25°C
–3.2
–40°C to +125°C
–3.2
25°C
–1.1
–40°C to +125°C
–1.2
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± 0.6
3.2
3.2
± 0.6
1.1
1.2
µA
µA
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TMUX7348F, TMUX7349F
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.9 36 V Single Supply: Electrical Characteristics (continued)
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
185
390
UNIT
SWITCHING CHARACTERISTICS
25°C
tON (EN)
Enable turn-on time
VS = 18 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
460
–40°C to +125°C
530
25°C
tOFF (EN)
Enable turn-off time
VS = 18 V,
RL = 4 kΩ, CL= 12 pF
380
–40°C to +85°C
Transition time
ns
450
25°C
tTRAN
450
450
–40°C to +125°C
ns
185
230
VS = 18 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
245
–40°C to +125°C
255
ns
tRESPONSE
Fault response time
VFP = 36 V, VFN = 0 V,
RL = 4 kΩ, CL= 12 pF
25°C
210
ns
tRECOVERY
Fault recovery time
VFP = 36 V, VFN = 0 V,
RL = 4 kΩ, CL= 12 pF
25°C
0.67
µs
tRESPONSE(FLAG)
Fault flag response time
VFP = 36 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
25°C
110
ns
tRECOVERY(FLAG) Fault flag recovery time
VFP = 36 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
25°C
0.65
µs
tBBM
Break-before-make time delay
VS = 18 V, RL = 4 kΩ, CL= 12 pF
–40°C to +125°C
100
ns
QINJ
Charge injection
VS = 18 V, CL = 1 nF
25°C
–16
pC
OISO
Off-isolation
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
25°C
–78
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
25°C
Intra-channel crosstalk
XTALK
Inter-channel crosstalk
(TMUX7349F)
–95
–3 dB bandwidth (TMUX7348F)
BW
–3 dB bandwidth (TMUX7349F
WQFN Package)
–3 dB bandwidth (TMUX7349F
TSSOP Package)
50
dB
–103
130
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V
25°C
255
MHz
220
ILOSS
Insertion loss
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
25°C
–9
dB
THD+N
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10 kΩ, VS = 18 VPP, VBIAS
25°C
= 18 V, f = 20 Hz to 20 kHz
0.0014
%
CS(OFF)
Input off-capacitance
f = 1 MHz, VS = 18 V
25°C
4
pF
Output off-capacitance
(TMUX7348F)
f = 1 MHz, VS = 18 V
25°C
31
Output off-capacitance
(TMUX7349F)
f = 1 MHz, VS = 18 V
25°C
16
Input/Output on-capacitance
(TMUX7348F)
f = 1 MHz, VS = 18 V
25°C
34
Input/Output on-capacitance
(TMUX7349F)
f = 1 MHz, VS = 18 V
25°C
19
25°C
0.24
CD(OFF)
CS(ON)
CD(ON)
pF
pF
POWER SUPPLY
IDD
VDD supply current
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
0.5
–40°C to +125°C
0.5
25°C
ISS
IGND
VSS supply current
GND current
0.5
–40°C to +85°C
0.14
0.4
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
–40°C to +85°C
0.4
–40°C to +125°C
0.4
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
0.075
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.9 36 V Single Supply: Electrical Characteristics (continued)
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
IFP
VFP supply current
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
10
µA
IFN
VFN supply current
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
10
µA
0.25
VDD supply current under fault
VS = 60 / –40 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
IDD(FA)
ISS(FA)
VSS supply current under fault
VS = 60 / –40 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
1
–40°C to +85°C
1
–40°C to +125°C
1
25°C
0.15
mA
0.5
–40°C to +85°C
0.5
–40°C to +125°C
0.5
mA
IGND(FA)
GND current under fault
VS = 60 / –40 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
0.12
mA
IFP(FA)
VFP supply current under fault
VS = 60 / –40 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
9
µA
IFN(FA)
VFN supply current under fault
VS = 60 / –40 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
7.5
µA
25°C
0.15
IDD(DISABLE)
V = VFP = 39.6 V, VSS = VFN = 0 V,
VDD supply current (disable mode) DD
VAx = 0 V, 5 V, or VDD, VEN = 0 V
–40°C to +85°C
0.5
–40°C to +125°C
0.5
25°C
ISS(DISABLE)
(1)
(2)
20
VSS supply current (disable mode)
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
0.5
0.1
mA
0.4
–40°C to +85°C
0.4
–40°C to +125°C
0.4
mA
When VS is 30 V, VD is 1 V. Or when VS is 1 V, VD is 30 V.
When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.10 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
420
1800
On Resistance ()
1400
1200
VDD
VDD
VDD
VDD
VDD
VDD
=
=
=
=
=
=
13.5 V, VSS = -13.5 V
15 V, VSS = -15 V
16.5 V, VSS = -16.5 V
18 V, VSS = -18 V
20 V, VSS = -20 V
22 V, VSS = -22 V
340
1000
800
600
300
200
140
-14 -10 -6
-2
2
6
10
14
VS or VD - Source or Drain Voltage (V)
18
100
-22
22
-18
-14 -10 -6
-2
2
6
10
14
VS or VD - Source or Drain Voltage (V)
Dual Supply Voltages
240
350
=
=
=
=
=
=
13.5 V, VSS = -13.5 V
15 V, VSS = -15 V
16.5 V, VSS = -16.5 V
18 V, VSS = -18 V
20 V, VSS = -20 V
22 V, VSS = -22 V
TA = 125C
300
On Resistance ()
210
VDD
VDD
VDD
VDD
VDD
VDD
200
190
180
TA = 85C
250
TA = 25C
200
150
TA = -40C
170
160
-10
-6
-2
2
6
VS or VD - Source or Drain Voltage (V)
100
-18
10
-14
-10
-6
-2
2
6
10
VS or VD - Source or Drain Voltage (V)
14
Figure 7-3. On-Resistance vs Source or Drain Voltage
Figure 7-4. On-Resistance vs Source or Drain Voltage
350
1800
TA = 125C
V DD
V DD
V DD
V DD
V DD
V DD
1600
300
)
1400
TA = 25C
= 7.2 V, V SS = 0 V
= 8 V, V SS = 0 V
= 8.8 V, V SS = 0 V
= 10.8 V, V SS = 0 V
= 12 V, V SS = 0 V
= 13.2 V, V SS = 0 V
1000
800
600
400
150
100
-18
1200
TA = 85C
On Resistance (
200
18
±15 V Supply Flattest RON Region
Flattest RON region for all supply voltages shown
250
22
Dual Supply Flat RON Region
Figure 7-2. On-Resistance vs Source or Drain Voltage
220
On Resistance ()
18
Figure 7-1. On-Resistance vs Source or Drain Voltage
230
On Resistance ()
13.5 V, VSS = -13.5 V
15 V, VSS = -15 V
16.5 V, VSS = -16.5 V
18 V, VSS = -18 V
20 V, VSS = -20 V
22 V, VSS = -22 V
220
180
-18
=
=
=
=
=
=
260
400
0
-22
VDD
VDD
VDD
VDD
VDD
VDD
380
On Resistance ()
1600
TA = -40C
200
0
-14
-10
-6
-2
2
6
10
VS or VD - Source or Drain Voltage (V)
14
18
0
2
4
6
8
10
V S or V D - Source or Drain Voltage (V)
13.2
Single Supply Voltages
±20 V Supply Flattest RON Region
Figure 7-5. On-Resistance vs Source or Drain Voltage
12
Figure 7-6. On-Resistance vs Source or Drain Voltage
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
350
480
TA = 125C
420
360
On Resistance ()
On Resistance (
)
300
300
240
180
V DD = 8 V, V SS = 0 V
V DD = 8.8 V, V SS = 0 V
V DD = 10.8 V, V SS = 0 V
120
2
4
6
8
10
V S or V D - Source or Drain Voltage (V)
12
TA = 85C
TA = 25C
200
150
V DD = 12 V, V SS = 0 V
V DD = 13.2 V, V SS = 0 V
60
0
250
13.2
Single Supply Flat RON Region
TA = -40C
100
1
2
3
4
5
6
7
VS or VD - Source or Drain Voltage (V)
8
9
12 V Supply Flattest RON Region
Figure 7-7. On-Resistance vs Source or Drain Voltage
Figure 7-8. On-Resistance vs Source or Drain Voltage
Single Supply Voltages
Single Supply Flat RON Region
Figure 7-9. On-Resistance vs Source or Drain Voltage
Figure 7-10. On-Resistance vs Source or Drain Voltage
350
TA = 125C
On Resistance ()
300
TA = 85C
250
TA = 25C
200
150
TA = -40C
100
1
5
9
13
17
21
25
29
VS or VD - Source or Drain Voltage (V)
33
36 V Supply Flattest RON Region
Figure 7-11. On-Resistance vs Source or Drain Voltage
22
44 V Supply Flattest RON Region
Figure 7-12. On-Resistance vs Source or Drain Voltage
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.10 Typical Characteristics (continued)
Leakage Current (nA)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
12
11
10
9
8
7
6
5
4
3
2
1
0
-1
IDOFF VS = -10 V, VD = 10 V
IDOFF VS = 10 V, VD = -10 V
IDON VS = -10 V, VD = -10 V
IDON VS = 10 V, VD = 10 V
ISOFF VS = -10 V, VD = 10 V
ISOFF VS = 10 V, VD = -10 V
0
25
50
75
Temperature (C)
VDD = 12 V, VSS = 0 V
25
Leakage Current (nA)
Leakage Current (nA)
Figure 7-14. Leakage Current vs Temperature
IDOFF VS = 1 V, VD = 30 V
IDOFF VS = 30 V, VD = 1 V
IDON VS = 1 V, VD = 1 V
IDON VS = 30 V, VD = 30 V
ISOFF VS = 1 V, VD = 30 V
ISOFF VS = 30 V, VD = 1 V
0
50
75
Temperature (C)
100
12
11
10
9
8
7
6
5
4
3
2
1
0
-1
IDOFF VS = -15 V, VD = 15 V
IDOFF VS = 15 V, VD = -15 V
IDON VS = -15 V, VD = -15 V
IDON VS = 15 V, VD = 15 V
ISOFF VS = -15 V, VD = 15 V
ISOFF VS = 15 V, VD = -15 V
0
125
25
50
75
Temperature (C)
VDD = 36 V, VSS = 0 V
Leakage Current (nA)
Leakage Current (nA)
1
125
Figure 7-16. Leakage Current vs Temperature
200
100
IDOFF VS = 1 V, VD = 30 V
IDOFF VS = 30 V, VD = 1 V
IDON VS = 1 V, VD = 1 V
IDON VS = 30 V, VD = 30 V
ISOFF VS = 1 V, VD = 30 V
ISOFF VS = 30 V, VD = 1 V
10
100
VDD = 20 V, VSS = −20 V
Figure 7-15. Leakage Current vs Temperature
200
100
125
VDD = 15 V, VSS = −15 V
Figure 7-13. Leakage Current vs Temperature
12
11
10
9
8
7
6
5
4
3
2
1
0
-1
100
0.1
0.01
0.0005
IDOFF VS = -15 V, VD = 15 V
IDOFF VS = 15 V, VD = -15 V
IDON VS = -15 V, VD = -15 V
IDON VS = 15 V, VD = 15 V
ISOFF VS = -15 V, VD = 15 V
ISOFF VS = 15 V, VD = -15 V
10
1
0.1
0.01
0.0005
0
25
50
75
Temperature (C)
100
125
0
25
VDD = 36 V, VSS = 0 V
Figure 7-17. Leakage Current vs Temperature
50
75
Temperature (C)
100
125
VDD = 20 V, VSS = −20 V
Figure 7-18. Leakage Current vs Temperature
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
16
16
Leakage Current (nA)
12
=
=
=
=
-60 V, VD = 15
-30 V, VD = 15
60 V, VD = -14
30 V, VD = -14
V
V
V
V
12
10
8
6
4
2
4
2
0
100
V
V
V
V
6
-2
50
75
Temperature (C)
-60 V, VD = 20
-30 V, VD = 20
60 V, VD = -19
30 V, VD = -19
8
0
25
=
=
=
=
10
-2
0
VS
VS
VS
VS
14
Leakage Current (nA)
VS
VS
VS
VS
14
125
0
25
50
75
Temperature (C)
VDD = 15 V, VSS = −15 V
100
125
VDD = 20 V, VSS = −20 V
Figure 7-19. ID(FA) Overvoltage Leakage Current vs Temperature
Figure 7-20. ID(FA) Overvoltage Leakage Current vs Temperature
16
VS
VS
VS
VS
Leakage Current (nA)
14
12
=
=
=
=
-40 V, VD = 36 V
-30 V, VD = 36 V
60 V, VD = 1 V
30 V, VD = 1 V
10
8
6
4
2
0
-2
0
25
50
75
Temperature (C)
VDD = 12 V, VSS = 0 V
125
VDD = 36 V, VSS = 0 V
Figure 7-21. ID(FA) Overvoltage Leakage Current vs Temperature
Figure 7-22. ID(FA) Overvoltage Leakage Current vs Temperature
120
0.1
90
0.05
0.03
0.02
60
30
VDD = 15 V, VSS = -15 V
VDD = 20 V, VSS = -20 V
VDD = 36 V, VSS = 0 V
VDD = 44 V, VSS = 0 V
0.01
THD+N (%)
Leakage Current (A)
100
0
-30
-60
0.005
0.003
0.002
0.001
-90
0.0005
0.0003
0.0002
-120
VS = -60 V
VS = -30 V
-150
-180
0
25
VS = 30 V
VS = 60 V
0.0001
50
75
Temperature (C)
100
125
0
4k
8k
12k
Frequency (Hz)
16k
20k
VDD = 15 V, VSS = −15 V
Figure 7-23. IS(FA) Overvoltage Leakage Current vs Temperature
24
Figure 7-24. THD+N vs Frequency
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.10 Typical Characteristics (continued)
2
2
-2
-2
-6
-6
Charge Injection (pC)
Charge Injection (pC)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
-10
-14
-18
-22
-10
-14
-18
-22
VDD
VDD
VDD
VDD
-26
-26
-30
-20
VDD = 15 V, VSS = -15 V
VDD = 20 V, VSS = -20 V
-16
-12
-30
-8
-4
0
4
8
VS - Source Voltage (V)
12
16
20
Figure 7-25. Charge Injection vs Source Voltage – Dual Supply
-34
0
4
=
=
=
=
8
8 V, VSS = 0 V
12 V, VSS = 0 V
36 V, VSS = 0 V
44 V, VSS = 0 V
12
16
20
24
28
32
VS - Source Voltage (V)
36
40
44
Figure 7-26. Charge Injection vs Source Voltage – Single Supply
210
VDD:
VDD:
VDD:
VDD:
200
190
15
15
20
20
V,
V,
V,
V,
VSS:
VSS:
VSS:
VSS:
-15
-15
-20
-20
V,
V,
V,
V,
Falling Edge
Rising Edge
Falling Edge
Rising Edge
Time (ns)
180
170
160
150
140
130
120
-40
-15
10
35
60
Temperature (C)
85
110 125
Figure 7-28. Transition Times vs Temperature
Figure 7-27. Transition Times vs Temperature
350
450
330
420
310
390
290
360
T OFF 15 V
T ON 15 V
T OFF 20 V
T ON 20 V
250
230
330
Time (ns)
Time (ns)
270
270
210
240
190
210
170
180
150
150
130
-40
-15
10
35
60
Temperature ( C)
85
110
125
Figure 7-29. Turn-On and Turn-Off Times vs Temperature
T OFF +8 V
T ON +8 V
T OFF +12 V
300
120
-40
-15
10
35
60
Temperature ( C)
T ON +12 V
T OFF +36 V
T ON +36 V
85
110
125
Figure 7-30. Turn-On and Turn-Off Times vs Temperature
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
0
Off-Isolation
CrossTalk: Adjacent Channel
CrossTalk: Nonadjacent Channel
-20
Gain (dB)
-40
-60
-80
-100
-120
10k
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 7-32. On Response vs Frequency
Figure 7-31. Off Isolation and Crosstalk vs Frequency
120
120
Capacitance (pF)
100
80
60
40
CDOFF TMUX7348F
CON TMUX7348F
CSOFF
CDOFF TMUX7349F
CON TMUX7349F
100
Capacitance (pF)
CDOFF TMUX7348F
CON TMUX7348F
CSOFF
CDOFF TMUX7349F
CON TMUX7349F
20
80
60
40
20
0
-15
0
-12
-9
-6
-3
0
3
6
9
VS or VD - Source or Drain Voltage (V)
12
15
0
2
4
6
8
10
VS or VD - Source or Drain Voltage (V)
VDD = 15 V, VSS = −15 V
VDD = 12 V, VSS = 0 V
Figure 7-33. Capacitance vs Source or Drain Voltage
Figure 7-34. Capacitance vs Source or Drain Voltage
0.9
0.4
VT Falling
VT Rising
0.36
0.8
0.32
Drain Voltage (V p-p)
Threshold Voltage (V)
12
0.7
0.6
V DD = +10 V
V SS = -10 V
V S = 10 V
0.28
0.24
0.2
0.16
0.12
0.5
0.08
0.4
-40
-15
10
35
60
Temperature (C)
85
110 125
Figure 7-35. Threshold Voltage vs Temperature
26
0.04
100k
1M
Frequency (Hz)
10M
50M
Figure 7-36. Large Signal Voltage Off Isolation vs Frequency
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SCDS400B – MARCH 2022 – REVISED JULY 2023
7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
25
22.5
SOURCE
50 V/s Fault Ramp
20
17.5
VFP
12.5
Volts (V)
Volts (V)
15
10
7.5
FF/SF
5
DRAIN
2.5
0
-2.5
-5
0
0.3
0.6
0.9
1.2 1.5 1.8
Time (s)
2.1
2.4
2.7
3
Volts (V)
Figure 7-37. Drain Output Response – Positive Overvoltage
10
7.5
5
2.5
0
-2.5
-5
-7.5
-10
-12.5
-15
-17.5
-20
-22.5
-25
10
7.5
5
2.5
0
-2.5
-5
-7.5
-10
-12.5
-15
-17.5
-20
-22.5
-25
FF/SF
DRAIN
VFN
50 V/s Fault Ramp
0
0.3
0.6
0.9
SOURCE
1.2 1.5 1.8
Time (s)
2.1
2.4
2.7
3
Figure 7-38. Drain Output Response – Negative Overvoltage
FF/SF
DRAIN
VFN
50 V/s Fault Ramp
0
0.3
0.6
0.9
SOURCE
1.2 1.5 1.8
Time (s)
2.1
2.4
2.7
3
Figure 7-39. Drain Output Recovery – Positive Overvoltage
Figure 7-40. Drain Output Recovery – Negative Overvoltage
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SCDS400B – MARCH 2022 – REVISED JULY 2023
8 Parameter Measurement Information
8.1 On-Resistance
The on-resistance of the TMUX7348F and TMUX7349F is the ohmic resistance across the source (Sx) and
drain (Dx) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is
used to denote on-resistance. Figure 8-1 shows the measurement setup used to measure RON. ΔRON represents
the difference between the RON of any two channels, while RON_FLAT denotes the flatness that is defined as
the difference between the maximum and minimum value of on-resistance measured over the specified analog
signal range.
V
VDD
VSS
410 =
VDD
Sx
VS
8
+5
VSS
IS
SW
Dx
GND
Figure 8-1. On-Resistance Measurement Setup
8.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current IS(OFF): the leakage current flowing into or out of the source pin when the switch
is off.
2. Drain off-leakage current ID(OFF): the leakage current flowing into or out of the drain pin when the switch is
off.
Figure 8-2 shows the setup used to measure both off-leakage currents.
VDD
Is (OFF)
VSS
VFP
VDD
VFN
VSS
VFP
S1
SW
S1
SW
S2
SW
S2
SW
VFN
A
ID (OFF)
VS
SW
D
...
...
...
S8
...
...
...
GND
D
A
VD
SW
S8
VD
GND
VS
GND
GND
GND
GND
IS(OFF)
ID(OFF)
Figure 8-2. Off-Leakage Measurement Setup
28
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SCDS400B – MARCH 2022 – REVISED JULY 2023
8.3 On-Leakage Current
Source on-leakage current (IS(ON)) and drain on-leakage current (ID(ON)) denote the channel leakage currents
when the switch is in the on state. IS(ON) is measured with the drain floating, while ID(ON) is measured with the
source floating. Figure 8-3 shows the circuit used for measuring the on-leakage currents.
VDD VSS
IS(ON)
VFP VFN
VDD VSS
SW
S1
VFP VFN
SW
S1
N.C.
A
SW
S2
SW
S2
ID(ON)
N.C.
...
SW
S8
SW
S8
VS
D
...
...
D
...
...
GND
...
VS
A
VD
GND
VS
GND
GND
GND
GND
IS(ON)
ID(ON)
Figure 8-3. On-Leakage Measurement Setup
8.4 Input and Output Leakage Current Under Overvoltage Fault
If the voltage for any of the source pins rises above the fault supplies (VFP or VFN), the overvoltage protection
feature of the TMUX7348F and TMUX7349F is triggered to turn off the switch under fault, keeping the
fault channel in high-impedance state. IS(FA) and ID(FA) denotes the input and output leakage current under
overvoltage fault conditions, respectively. For ID(FA), the device is disabled to measure leakage current on the
drain pin without being impacted by the 40 kΩ impedance to the fault supply. When the overvoltage fault occurs,
the supply (or supplies) can either be in normal operating condition (Figure 8-4) or abnormal operating condition
(Figure 8-5). During abnormal operating condition, the supply (or supplies) can either be unpowered (VDD=
VSS = VFN = VFP = 0 V) or floating (VDD= VSS = VFN = VFP = no connection), and remains within the leakage
performance specifications.
VDD
IS (FA)
S1
VSS
VFP
VFN
SW
A
VS
S2
SW
ID (FA)
S8
D
...
...
...
GND
N.C.
A
SW
N.C.
VD
GND
GND
IS(FA) / ID(FA)
( |VS| > |VFP + VT| or |VFN - VT| )
Figure 8-4. Measurement Setup for Input and Output Leakage Current under Overvoltage Fault with
Normal Supplies
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N.C.
GND
VDD
VSS
IS (FA)
VFP
VDD
VFN
SW
S1
VFN
SW
A
N.C.
SW
S2
ID (FA)
N.C.
VS
...
GND
S8
SW
A
SW
S8
GND
N.C.
ID (FA)
D
...
A
SW
S2
...
D
...
...
...
GND
VFP
S1
A
VS
VSS
IS (FA)
GND
N.C.
GND
GND
Floating
(VDD = VSS = VFP = VFN = N.C.)
Unpowered
(VDD = VSS = VFP = VFN = 0 V)
Figure 8-5. Measurement Setup for Input and Output Leakage Current Under Overvoltage Fault with
Unpowered or Floating Supplies
8.5 Break-Before-Make Delay
The break-before-make delay is a safety feature of the TMUX7348F and TMUX7349F. The ON switches first
break the connection before the OFF switches make connection. The time delay between the break and the
make is known as break-before-make delay. Figure 8-6 shows the setup used to measure break-before-make
delay, denoted by the symbol tBBM.
VDD
VSS
0.1 µF
VDD VSS
GND
0.1 µF
VFP VFN
SW
S1
GND
3V
D
...
tf < 20 ns
...
tr < 20 ns
VA
SW
S2
S7
SW
RL
S8
SW
GND
0V
GND
VD
CL
GND
0.8 VD
Output
tBBM 2
tBBM 1
0V
A0
VS
A1
tBBM = min ( tBBM 1, tBBM 2)
EN
Decoder
A2
GND
VEN
VA
GND
GND
GND
Figure 8-6. Break-Before-Make Delay Measurement Setup
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8.6 Enable Delay Time
tON(EN) time is defined as the time taken by the output of the TMUX7348F and TMUX7349F to rise to a 90% final
value after the EN signal has risen to a 50% final value. tOFF(EN) is defined as the time taken by the output of the
TMUX7348F and TMUX7349F to fall to a 10% initial value after the EN signal has fallen to a 50% initial value.
Figure 8-7 shows the setup used to measure the enable delay time.
VDD
VSS
0.1 µF
VDD VSS
GND
VFP VFN
0.1 µF
SW
S1
GND
SW
S2
3V
VS
50%
tf < 20 ns
GND
0V
D
...
50%
...
tr < 20 ns
VEN
VD
RL
SW
S8
0.9 VD
GND
tOFF(EN)
tON(EN)
Output
CL
GND
GND
A0
0.1 VD
EN
A1
Decoder
A2
VEN
GND
GND
GND
Figure 8-7. Enable Delay Measurement Setup
8.7 Transition Time
Transition time is defined as the time taken by the output of the device to rise (to 90% of the transition) or fall (to
10% of the transition) after the address signal (Ax) has fallen or risen to 50% of the transition. Figure 8-8 shows
the setup used to measure transition time, denoted by the symbol tTRAN.
VDD
VSS
0.1 µF
VDD VSS
GND
0.1 µF
VFP VFN
SW
S1
GND
3V
tr < 20 ns
VA
50%
50%
tf < 20 ns
...
VD
0V
0.9 VD
tTRAN 1
D
...
VS
0V
Output
SW
S2
GND
RL
SW
S8
tTRAN 2
GND
0.1 VD
CL
GND
GND
A0
tTRAN = max ( tTRAN 1, tTRAN 2)
EN
A1
Decoder
A2
VEN
VA
GND
GND
GND
Figure 8-8. Transition Time Measurement Setup
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8.8 Fault Response Time
Fault response time (tRESPONSE) measures the delay between the source voltage exceeding the fault supply
voltage (VFP or VFN) by 0.5 V and the drain voltage failing to 50% of the maximum output voltage. Figure 8-9
shows the setup used to measure tRESPONSE.
VSS
VFP
0.1 µF
0V
Max positive fault
VFP + 0.5 V
VS
60 V/µs
ramp
VDD
GND
VS
VFN - 0.5 V
0V
60 V/µs
ramp
VFN
0.1 µF
VFP VFN
VDD VSS
GND
Max negative fault
GND
SW
Sx
0V
SW
Output × 50%
VS
...
Output
Output × 50% (VD)
...
VFN
0V
GND
0.1 µF
tRESPONSE (FN)
tRESPONSE (FP)
VFP
Output
(VD)
0.1 µF
GND
...
tRESPONSE = max ( tRESPONSE(FP), tRESPONSE(FN))
Output
D/ DX
All other
source
pins
RL
SW
GND
CL
GND
GND
Figure 8-9. Fault Response Time Measurement Setup
8.9 Fault Recovery Time
Fault recovery time (tRECOVERY) measures the delay between the source voltage falling from overvoltage
condition to below fault supply voltage (VFP or VFN) plus 0.5 V and the drain voltage rising from 0 V to 50%
of the final output voltage. Figure 8-10 shows the setup used to measure tRECOVERY.
VSS
VFP
0.1 µF
0V
VFP + 0.5 V
VDD
GND
VFN - 0.5 V
VS
0.1 µF
0.1 µF
VFP VFN
VDD VSS
0V
GND
tRECOVERY (FN)
GND
SW
Sx
tRECOVERY (FP)
0V
SW
Output × 50%
Output
(VD)
VS
GND
...
0V
...
Output × 50%
GND
0.1 µF
VS
Output
(VD)
VFN
...
tRECOVERY = max ( tRECOVERY(FP), tRECOVERY(FN))
Output
D/ DX
All other
source
pins
SW
RL
GND
CL
GND
GND
Figure 8-10. Fault Recovery Time Measurement Setup
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8.10 Fault Flag Response Time
Fault flag response time (tRESPONSE(FLAG)) measures the delay between the source voltage exceeding the fault
supply voltage (VFP or V FN) by 0.5 V and the general fault flag (FF) pin or specific fault flag (SF) pin to go below
10% of its original value. Figure 8-11 shows the setup used to measure tRESPONSE(FLAG).
VSS
VFP
0.1 µF
0.1 µF
VDD
GND
VFN
GND
0.1 µF
0.1 µF
0V
VS
VFP VFN
VDD VSS
VFP + 0.5 V
GND
VS
VFN - 0.5 V
GND
SW
Sx
0V
SW
tRESPONSE(FLAG)_FN
5V
VS
...
tRESPONSE(FLAG)_FP
5V
Output (VXF)
0V
GND
0.5 V
0V
...
0.5 V
...
Output (VXF)
Output
D/ DX
All other
source
pins
RL
SW
CL
GND
tRESPONSE(FLAG) = max ( tRESPONSE(FLAG)_FP, tRESPONSE(FLAG)_FN)
5V
RPU
GND
GND
xF
CL_xF
GND
Figure 8-11. Fault Flag Response Time Measurement Setup
8.11 Fault Flag Recovery Time
Fault flag recovery time (tRECOVERY(FLAG)) measures the delay between the source voltage falling from
overvoltage condition to below fault supply voltage (VFP or VFN) plus 0.5 V and the general fault flag (FF)
pin or the specific fault flag (SF) pin to rise above 3 V with 5 V external pull-up. Figure 8-12 shows the setup
used to measure tRECOVERY(FLAG).
VSS
VFP
0.1 µF
0.1 µF
VDD
GND
0V
VFP + 0.5 V
GND
SW
...
VS
5V
Output (VXF)
3V
GND
...
3V
GND
SW
Sx
tRECOVERY(FLAG)_FN
5V
0V
Output
D/ DX
All other
source
pins
...
0V
0.1 µF
VFP VFN
VDD VSS
VS
Output (VXF)
GND
0.1 µF
VFN - 0.5 V
0V
tRECOVERY(FLAG)_FP
VFN
RL
SW
tRECOVERY(FLAG) = max ( tRECOVERY(FLAG)_FP, tRECOVERY(FLAG)_FN)
GND
CL
5V
GND
RPU
GND
xF
CL_xF
GND
Figure 8-12. Fault Flag Recovery Time Measurement Setup
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8.12 Charge Injection
Charge injection is a measure of the glitch impulse transferred from the logic input to the analog output during
switching, and is denoted by the symbol QINJ. Figure 8-13 shows the setup used to measure charge injection
from the source to drain.
VDD
VSS
0.1 µF
VDD VSS
GND
0.1 µF
VFP VFN
SW
S1
GND
SW
S2
...
3V
D
...
VS
GND
tr < 20 ns
VEN
CL
SW
S8
tf < 20 ns
Output
GND
0V
GND
A0
Output
QINJ = CL ×
VS
VOUT
VOUT
EN
A1
Decoder
A2
VEN
GND
GND
GND
Figure 8-13. Charge-Injection Measurement Setup
8.13 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to
the source pin (Sx) of an off-channel. Figure 8-14 and Equation 1 shows the setup used to measure, and the
equation used to calculate off isolation.
VDD
VSS
0.1 µF
Network Analyzer
VS
GND
0.1 µF
VDD VSS
SX
VFP VFN
SW
GND
SW
50
50
Other
Sx Pins
SW
50
VSIG
VOUT
D/ DX
50
VAX
VEN
Ax, EN
GND
Figure 8-14. Off Isolation Measurement Setup
V
Off Isolation = 20 × Log OUT
V
S
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8.14 Crosstalk
There are two types of crosstalk that can be defined for the devices:
1. Intra-channel crosstalk (XTALK(INTRA)): Figure 8-15 shows the voltage at the source pin (Sx) of an off-switch
input when a signal is applied at the source pin of an on-switch input in the same channel.
2. Inter-channel crosstalk (XTALK(INTER)): Figure 8-16 shows the voltage at the source pin (Sx) of an on-switch
input, when a signal is applied at the source pin of an on-switch input in a different channel. Inter-channel
crosstalk applies only to the TMUX7349F device.
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
VFP VFN
VDD VSS
GND
S1/S1X
GND
SW
D/ DX
VOUT
S2/S2X
SW
RS
RL
50
Other
Sx/ Dx
SW
Pins
VS
50
Ax, EN
GND
VAX
VEN
Intra - channel Crosstalk = 20 x Log
VOUT
VS
Figure 8-15. Intra-Channel Crosstalk Measurement Setup
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
VFP VFN
VDD VSS
GND
SxA
GND
SW
DA
Other
SW
SxA Pins
RS
50
RL
VOUT
SxB
SW
DB
VS
50
Other
SxB Pins SW
50
RL
Ax, EN
VAX
VEN
Inter – channel Crosstalk = 20 x Log
GND
VOUT
VS
Figure 8-16. Inter-Channel Crosstalk Measurement Setup
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8.15 Bandwidth
Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to
the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D or Dx) of the TMUX7348F
and TMUX7349F. Figure 8-17 shows the setup used to measure bandwidth of the switch.
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
VFP VFN
VDD VSS
GND
GND
SW
SX
SW
50
Other
Sx/ Dx
Pins
RS
SW
50
VOUT
D/ DX
VS
50
Ax, EN
VAX
VEN
Bandwidth = 20 x Log
GND
VOUT
VS
Figure 8-17. Bandwidth Measurement Setup
8.16 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined
as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency
at the multiplexer output. The on-resistance of the TMUX7348F and TMUX7349F varies with the amplitude
of the input signal and results in distortion when the drain pin is connected to a low-impedance load. Total
harmonic distortion plus noise is denoted as THD+N. Figure 8-18 shows the setup used to measure THD+N of
the devices.
VDD
VSS
0.1 µF
0.1 µF
VDD VSS
GND
Audio Precision
SX
VFP VFN
SW
GND
SW
N.C.
Other
Sx/ Dx
Pins
RS
SW
N.C.
VOUT
D/ DX
VS
RL
Ax, EN
VAX
VEN
GND
Figure 8-18. THD+N Measurement Setup
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9 Detailed Description
9.1 Overview
The TMUX7348F and TMUX7349F are a modern complementary metal-oxide semiconductor (CMOS) analog
multiplexers in 8:1 (single ended) and 4:1 (differential) configurations. The devices work well with dual supplies
(±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD = 15 V, VSS = –5 V). The
devices have an overvoltage protection feature on the source pins under powered and powered-off conditions,
allowing them to be used in harsh industrial environments.
9.2 Functional Block Diagram
VDD VSS
VFN VFP
VDD VSS
SW
VFN VFP
SW
S1
S1A
SW
...
S2
S4A
D
DA
SW
SW
...
S1B
...
SW
DB
SW
S4B
S8
A0
A1
A2
Fault Detecon/
Switch Driver/
Logic Decoder
EN
TMUX7348F
FF
SF
A0
A1
EN
Fault Detec on/
Switch Driver/
Logic Decoder
FF
SF
TMUX7349F
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9.3 Feature Description
9.3.1 Flat ON- Resistance
The TMUX7348F and TMUX7349F are designed with a special switch architecture to produce ultra-flat onresistance (RON) across most of the switch input operation region. The flat RON response allows the device to
be used in precision sensor applications since the RON is controlled regardless of the signals sampled. The
architecture is implemented without a charge pump so no unwanted noise is produced from the device to affect
sampling accuracy.
9.3.2 Protection Features
The TMUX7348F and TMUX7349F offer a number of protection features to enable robust system
implementations.
9.3.2.1 Input Voltage Tolerance
The maximum voltage that can be applied to any source input pin is +60 V or −60 V, regardless of the supply
voltage. This allows the device to handle typical voltage fault conditions in industrial applications. Take caution:
the device is rated to handle a maximum stress of 85 V across different pins, such as the following:
1. Between source pins and supply rails:
For example, if the device is powered by VDD supply of 20 V, then the maximum negative signal level on any
source pin is –60 V to maintain the 60 V maximum rating on any source pin. If the device is powered by VDD
supply of 40 V, then the maximum negative signal level on any source pin is reduced to –45 V to maintain
the 85 V maximum rating across the source pin and the supply.
2. Between source pins and one or more of the drain pins:
For example, if channel S1(A) is ON and the voltage on S1(A) pin is 40 V. In this case, the drain voltage
is also 40 V. The maximum negative voltage on any of the other source pins is –45 V to maintain the 85 V
maximum rating across the source pin and the drain pin.
9.3.2.2 Powered-Off Protection
When the supplies of TMUX7348F and TMUX7349F are removed (VDD/ VSS = 0 V or floating), the source
(Sx) pins of the device remain in the high impedance (Hi-Z) state, and the source (Sx) and drain (Dx) pins
of the device remain within the leakage performance mentioned in the Electrical Characteristics. Powered-off
protection minimizes system complexity by removing the need to control the power supply sequencing of the
system. The feature prevents errant voltages on the input source pins from reaching the rest of the system
and maintains isolation when the system is powering up. Without powered-off protection, the signal on the input
source pins can back-power the supply rails through the internal ESD diodes and potentially cause damage
to the system. For more information on powered-off protection, refer to the Eliminate Power Sequencing with
Powered-Off Protection Signal Switches application brief.
The switch remains OFF regardless of whether the VDD and VSS supplies are 0 V or floating. A GND reference
must always be present for proper operation. Source and drain voltage levels of up to ±60 V are blocked in the
powered-off condition.
9.3.2.3 Fail-Safe Logic
Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting
the device from potential damage. The switch is specified to be in the OFF state, regardless of the state of the
logic signals. The logic inputs are protected against positive faults of up to +44 V in the powered-off condition,
but do not offer protection against the negative overvoltage condition.
Fail-safe logic also allows the TMUX7348F and TMUX7349F devices to interface with a voltage greater than V DD
during normal operation to add maximum flexibility in system design. For example, with a V DD of = 15 V, the logic
control pins could be connected to +24 V for a logic high signal which allows different types of signals, such as
analog feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the
logic inputs can be interfaced as high as 44 V.
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9.3.2.4 Overvoltage Protection and Detection
The TMUX7348F and TMUX7349F detect overvoltage inputs by comparing the voltage on a source pin (Sx) with
the fault supplies (VFP and V FN). A signal is considered overvoltage if it exceeds the fault supply voltages by the
threshold voltage (VT).
When an overvoltage is detected, the switch automatically turns OFF regardless of the logic controls. The
source pin becomes high impedance and allows only a small leakage current to flow through the switch and
the overvoltage does not appear on the drain. When the overvoltage channel is selected by the logic control,
the drain pin (D or Dx) is pulled to the supply that was exceeded. For example, if the source voltage exceeds
VFP, then the drain output is pulled to VFP. If the source voltage exceeds VFN, then the drain output is pulled to
VFN. The pull-up impedance is approximately 40 kΩ, and as a result, the drain current is limited to roughly 1 mA
during a shorted load (to GND) condition.
Figure 9-1 shows a detailed view of how the pullup or down controls the output state of the drain pin under a
fault scenario.
VDD
Ax
Logic &
Fault
Detection
VSS
VFP
40 kΩ
Sx
Dx
ESD
Protection
GND
40 kΩ
VFN
Figure 9-1. Detailed Functional Diagram
VFP and VFN are required fault supplies that set the level at which the overvoltage protection is engaged. VFP can
be supplied from 3 V to VDD, while the VFN can be supplied from VSS to 0 V. If the fault supplies are not available
in the system, then the VFP pin must be connected to VDD, while the VFN pin must be connected to VSS. In this
case, overvoltage protection then engages at the primary supply voltages VDD and VSS.
9.3.2.5 Adjacent Channel Operation During Fault
When the logic pins are set to a channel under a fault, the overvoltage detection will trigger, the switch will open,
and the drain pin will be pulled up or down as described in Section 9.3.2.4. During such an event, all other
channels not under a fault can continue to operate as normal. For example, if S1 voltage exceeds VFP, and the
logic pins are set to S1, the drain output is pulled to VFP. Then if the logic pins are changed to set S4, which
is not in overvoltage or undervoltage, the drain will disconnect from the pullup to VFP and the S4 switch will be
enabled and connected to the drain, operating as normal. If the logic pins are switched back to S1, the S4 switch
will be disabled, the drain pin will be pulled up to VFP again, and the switch from S1 to drain will not be enabled
until the overvoltage fault is removed.
9.3.2.6 ESD Protection
All pins on the TMUX7348F and TMUX7349F support HBM ESD protection level up to ±3.5 kV, which helps the
device from getting ESD damages during the manufacturing process.
The drain pins (D or Dx) have internal ESD protection diodes to the fault supplies VFP and VFN. Therefore, the
voltage at the drain pins must not exceed the fault supply voltages to prevent excessive diode current. The
source pins have specialized ESD protection that allows the signal voltage to reach ±60 V regardless of the
supply voltage level. Exceeding ±60 V on any source input may damage the ESD protection circuitry on the
device and cause the device to malfunction if the damage is excessive.
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9.3.2.7 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
The TMUX7348F and TMUX7349F devices are constructed on silicon on insulator (SOI) based process where
an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic
structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch
up events due to overvoltage or current injections. The latch-up immunity feature allows the TMUX7348F and
TMUX7349F to be used in harsh environments. For more information on latch-up immunity refer to the Using
Latch-Up Immune Multiplexers to Help Improve System Reliability application report.
9.3.2.8 EMC Protection
The TMUX7348F and TMUX7349F are not intended for standalone electromagnetic compatibility (EMC)
protection in industrial applications. There are three common high voltage transient specifications that govern
industrial high voltage transient specifications: IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and IEC61000-4-5
(surge immunity). A transient voltage suppressor (TVS), along with some low-value series current limiting
resistors, are required to prevent source input voltages from going above the rated ±60 V limits.
When selecting a TVS protection device, it is critical to ensure that the maximum working voltage is greater than
both the normal operating range of the input source pins to be protected and any known system common-mode
overvoltage that may be present due to incorrect wiring, loss of power, or short circuit. Figure 9-2 shows an
example of the proper design window when selecting a TVS device.
Region 1 denotes the normal operation region of TMUX7348F and TMUX7349F where the input source voltages
stay below the fault supplies VFP and VFN. Region 2 represents the range of possible persistent DC (or long
duration AC overvoltage fault) presented on the source input pins. Region 3 represents the margin between
any known DC overvoltage level and the absolute maximum rating of the TMUX7348F and TMUX7349F. The
TVS breakdown voltage must be selected to be less than the absolute maximum rating of the TMUX7348F and
TMUX7349F, but greater than any known possible persistent DC or long duration AC overvoltage fault to avoid
triggering the TVS inadvertently. Region 4 represents the margin system designers must impose when selecting
the TVS protection device to prevent accidental triggering of ESD cells of the TMUX7348F and TMUX7349F
devices.
Internal ESD
Trigger Voltage
4
3
Overvoltage
Protection Window
TVS
Breakdown
Voltage
Device Absolute
Max Rating
System
Overvoltage
2
Fault Voltage
Supply VFP
0V
1
Normal Operation
Fault Voltage
Supply VFN
2
Overvoltage
Protection Window
3
TVS
Breakdown
Voltage
System
Overvoltage
Device Absolute
Max Rating
4
Internal ESD
Trigger Voltage
Figure 9-2. System Operation Regions and Proper Region of Selecting a TVS Protection Device
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9.3.3 Overvoltage Fault Flags
The voltages on the source input pins of the TMUX7348F and TMUX7349F are continuously monitored, and
the status of whether an overvoltage condition occurs is indicated by an active low general fault flag (FF). The
voltage on the FF pin indicates if any of the source input pins are experiencing an overvoltage condition. If any
source pin voltage exceeds the fault supply voltages by a VT, the FF output is pulled-down to below VOL.
The specific fault (SF) output pins, on the other hand, can be used to decode which inputs are experiencing an
overvoltage condition. As provided in Table 9-1 and Table 9-2, the SF pin is pulled-down to below VOL when an
overvoltage condition is detected on a specific source input pin, depending on the state of the A0, A1, A2, and
EN logic pins.
Both the FF pin and SF pin are open-drain output and external pull-up resistors of 1 kΩ are recommended. The
pull-up voltage can be in the range of 1.8 V to 5.5 V, depending on the controller voltage the device interfaces
with.
9.3.4 Bidirectional and Rail-to-Rail Operation
The TMUX7348F and TMUX7349F conducts equally well from source (Sx) to drain (D or Dx) or from drain (D
or Dx) to source (Sx). Each signal path has very similar characteristics in both directions. It is important to note,
however, that the overvoltage protection is implemented only on the source (Sx) side. The voltage on the drain is
only allowed to swing between VFP and VFN and no overvoltage protection is available on the drain side.
The primary supplies (VDD and VSS) define the on-resistance profile of the switch channel, whereas the fault
voltage supplies (VFP and VFN) define the signal range that can be passed through from source to drain of the
device. It is good practice to use voltages on VFP and VFN that are lower than VDD and VSS to take advantage
of the flat on-resistance region of the device for better input-to-output linearity. The flatest on-resistance region
extends from VSS to roughly 3 V below VDD. Once the signal is within 3 V of VDD the on-resistance will
exponentially increase and may impact desired signal transmission.
9.3.5 1.8 V Logic Compatible Inputs
The TMUX7348F and TMUX7349F devices have 1.8 V logic compatible control for all logic control inputs. 1.8
V logic level inputs allows the TMUX7348F and TMUX7349F to interface with processors that have lower logic
I/O rails and eliminates the need for an external translator, which saves both space and BOM cost. For more
information on 1.8 V logic implementations refer to Simplifying Design with 1.8 V Logic Muxes and Switches.
9.3.6 Integrated Pull-Down Resistor on Logic Pins
The TMUX7348F and TMUX7349F have internal weak pull-down resistors to GND so that the logic pins are not
left floating. The value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1 µA at higher
voltages. This feature integrates up to four external components and reduces system size and cost.
9.4 Device Functional Modes
The TMUX7348F and TMUX7349F offer two modes of operation (Normal mode and Fault mode) depending on
whether any of the input pins experience an overvoltage condition.
9.4.1 Normal Mode
In Normal mode operation, signals of up to VFP and VFN can be passed through the switch from source (Sx) to
drain (D or Dx) or from drain (D or Dx) to source (Sx). As provided in Table 9-1 and Table 9-2, the address (Ax)
pins and the enable (EN) pin determine which switch path to turn on. The following conditions must be satisfied
for the switch to stay in the ON condition:
•
•
•
•
The difference between the primary supples (VDD – VSS) must be higher or equal to 8 V. With a minimum VDD
of 5 V.
VFP must be between 3 V and VDD, and VFN must be between VSS and 0 V.
The input signals on the source (Sx) or the drain (D or Dx) must be be between VFP+ VT and VFN – VT.
The logic control (Ax and EN) must have selected the switch.
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9.4.2 Fault Mode
The TMUX7348F and TMUX7349F enters into Fault mode when any of the input signals on the source (Sx) pins
exceed VFP or VFN by a threshold voltage VT. Under the overvoltage condition, the switch input experiencing the
fault automatically turns OFF regardless of the logic status, and the source pin becomes high impedance with a
negligible amount of leakage current flowing through the switch. When the fault channel is selected by the logic
control, the drain pin (D or Dx) is pulled to the fault supply that was exceeded through a 40 kΩ internal resistor.
In the Fault mode, the general fault flag (FF) is asserted low. Table 9-1 and Table 9-2 provides how the specific
flag (SF) is asserted low when a specific input path is selected.
The overvoltage protection is provided only for the source (Sx) input pins. The drain (D or Dx) pin, if used as
signal input, must stay in between VFP and VFN at all time since no overvoltage protection is implemented on the
drain pin.
42
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9.4.3 Truth Tables
Table 9-1 shows the truth tables for the TMUX7348F under normal and fault conditions.
Table 9-1. TMUX7348F Truth Table
Fault Condition
Normal Condition
EN
A2
A1
A0
State of Specific Flag (SF) when fault occurs on
On Switch
S1
S2
S3
S4
S5
S6
S7
S8
0
0
0
0
None
0
1
1
1
1
1
1
1
0
0
0
1
None
1
0
1
1
1
1
1
1
0
0
1
0
None
1
1
0
1
1
1
1
1
0
0
1
1
None
1
1
1
0
1
1
1
1
0
1
0
0
None
1
1
1
1
0
1
1
1
0
1
0
1
None
1
1
1
1
1
0
1
1
0
1
1
0
None
1
1
1
1
1
1
0
1
0
1
1
1
None
1
1
1
1
1
1
1
0
1
0
0
0
S1
0
1
1
1
1
1
1
1
1
0
0
1
S2
1
0
1
1
1
1
1
1
1
0
1
0
S3
1
1
0
1
1
1
1
1
1
0
1
1
S4
1
1
1
0
1
1
1
1
1
1
0
0
S5
1
1
1
1
0
1
1
1
1
1
0
1
S6
1
1
1
1
1
0
1
1
1
1
1
0
S7
1
1
1
1
1
1
0
1
1
1
1
1
S8
1
1
1
1
1
1
1
0
Table 9-2 shows the truth tables for the TMUX7349F under normal and fault conditions.
Table 9-2. TMUX7349F Truth Table
EN
A1
A0
Fault Condition
Normal Condition
State of Specific Flag (SF) when fault occurs on
On Switch
S1A
S2A
S3A
S4A
S1B
S2B
S3B
S4B
0
0
0
None
0
1
1
1
1
1
1
1
0
0
1
None
1
0
1
1
1
1
1
1
0
1
0
None
1
1
0
1
1
1
1
1
0
1
1
None
1
1
1
0
1
1
1
1
1
0
0
S1x
1
1
1
1
0
1
1
1
1
0
1
S2x
1
1
1
1
1
0
1
1
1
1
0
S3x
1
1
1
1
1
1
0
1
1
1
1
S4x
1
1
1
1
1
1
1
0
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TMUX7348F and TMUX7349F are part of the fault protected switches and multiplexers family of devices.
The ability to protect downstream components from overvoltage events up to ±60 V makes these switches and
multiplexers suitable for harsh environments.
10.2 Typical Application
In analog input programmable logic controllers (PLC) a multiplexer is often used to switch multiple sensors
to a single ADC. By using a multiplexer, the number of components in the system can be reduced to save
system cost and size. In a PLC module a ±10 V input signal range is common for interfacing with external field
transmitters and sensors; however, there are a number of fault cases that may occur that can be damaging
to many of the integrated circuits. Such fault conditions may include, but are not limited to, human error from
wiring connections incorrectly, component failure or wire shorts, electromagnetic interference (EMI) or transient
disturbances, and so forth.
Supply
Power Module
GND
VDD
Bridge Sensor
VSS
VFP
VFN
PLC Analog
Input Module
TMUX7348F
S1
5V
S2
Thermocouple
REF5025
S3
...
Current Sensing
Fault
Protected
Mux Inputs
D
S4
S5
Gain / Filter
Network
ADS125H01
ISO77xx
Signal
Processing
S6
S7
Photo
LED Detector
S8
V
Opcal Sensor
GND
A0
A1
A2
1.8 V Logic
Signals
Sensors
Figure 10-1. Typical Application
44
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10.2.1 Design Requirements
Table 10-1. Design Parameters
PARAMETER
VALUE
Positive supply (VDD) mux
+15 V
Negative supply (VSS) mux
−15 V
Positive fault voltage supply (VFP) mux and ADC
+10 V
Negative fault voltage supply (VFN) mux and ADC
−10 V
Power board supply voltage
24 V
Input or output signal range non-faulted
−10 V to 10 V
Overvoltage protection levels
−60 V to 60 V
Control logic thresholds
1.8 V compatible, up to 44 V
Temperature range
−40°C to +125°C
10.2.2 Detailed Design Procedure
The previous image shows the case where an incorrect wiring condition occurred and one of the input
connectors shorted to the power board supply voltage. If the board supply voltage is higher than the fault voltage
supply of the multiplexer, then the TMUX7348F or TMUX7349F will disconnect the source input from passing
the signal to protect the downstream ADC. The drain pin of the mux will be pulled up to the fault voltage supply
voltage VFP through a 40 kΩ resistor to allow the ADC to determine a fault condition has occurred.
10.2.3 Application Curves
The previous example shows how the fault protection of the TMUX7348F or TMUX7349F is utilized to protect
downstream components from damage due to wiring the connections incorrectly from the power module. Figure
10-2 shows an example of positive overvoltage fault response with a fast fault ramp rate of 58 V/µs. Figure
10-3 shows the extremely flat on-resistance across source voltage while operating within a common signal
range of ±10 V. These features make the TMUX7348F or TMUX7349F an ideal solution for factory automation
applications that can face various fault conditions but also require excellent linearity and low distortion.
240
25
22.5
SOURCE
50 V/s Fault Ramp
230
20
17.5
220
On Resistance ()
VFP
Volts (V)
15
12.5
10
7.5
FF/SF
5
DRAIN
2.5
210
VDD
VDD
VDD
VDD
VDD
VDD
=
=
=
=
=
=
13.5 V, VSS = -13.5 V
15 V, VSS = -15 V
16.5 V, VSS = -16.5 V
18 V, VSS = -18 V
20 V, VSS = -20 V
22 V, VSS = -22 V
200
190
180
0
170
-2.5
-5
0
0.3
0.6
0.9
1.2 1.5 1.8
Time (s)
2.1
2.4
2.7
Figure 10-2. Positive Overvoltage Response
3
160
-10
-6
-2
2
6
VS or VD - Source or Drain Voltage (V)
10
Figure 10-3. RON Flatness in Non-Fault Region
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10.3 Power Supply Recommendations
The TMUX7348F and TMUX7349F operate across a wide supply range of ±5 V to ±22 V (8 V to 44 V in
single-supply mode). They also perform well with asymmetrical supplies such as VDD = 12 V and VSS= –5 V. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 µF to 10 µF at both the VDD
and VSS pins to ground. Always ensure the ground (GND) connection is established before supplies are ramped.
The fault supplies (VFP and VFN) provide the current required to operate the fault protection, and thus, must be
low impedance supplies. They can be derived from the primary supplies by using a resistor divider and buffer
or be an independent supply rail. The fault supplies must not exceed the primary supplies as it might cause
unexpected behavior of the switch. Use a supply decoupling capacitor ranging from 0.1 µF to 10 µF at both the
VFP and VFN pins to ground for improved supply noise immunity.
The positive supply (VDD) must be ramped before the positive fault rail (VFP) for proper power sequencing of
the TMUX7348F and TMUX7349F. Similarly, the negative supply (VSS) must be ramped before the negative fault
voltage rail (VFN).
10.4 Layout
10.4.1 Layout Guidelines
The following images illustrate examples of a PCB layout with the TMUX7348F and TMUX7349F. Some key
considerations are as follows:
•
•
•
•
•
For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and VSS to
GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as
possible. Make sure that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
Multiple decoupling capacitors can be used if there is a lot of noise in the system. For example, a 0.1-µF
and 1-µF can be placed on the supply pins. If multiple capacitors are used, then placing the lowest value
capacitor closest to the supply pin is recommended.
Keep the input lines as short as possible.
Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
10.4.2 Layout Example
Wide (low inductance)
trace for power
C
A0
A1
EN
A2
VSS
GND
S1
VDD
S2
C
Via to ground plane
C
S5
TMUX7348F
S3
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
S6
S4
S7
D
S8
VFN
VFP
SF
FF
1 k
C
Wide (low inductance)
trace for power
1k
Via to signal plane
Wide (low inductance)
trace for power
Figure 10-4. TMUX7348FPW Layout Example
46
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Wide (low inductance)
trace for power
C
A0
A1
EN
GND
VSS
VDD
S1A
S1B
S2A
S2B
TMUX7349F
S3A
Wide (low inductance)
trace for power
C
S4B
DA
DB
VFN
VFP
SF
FF
1 k
Wide (low inductance)
trace for power
S3B
S4A
Via to ground plane
C
C
Wide (low inductance)
trace for power
1k
Via to signal plane
Wide (low inductance)
trace for power
GND
A1
A2
A0
C
C
C
Wide (low inductance)
trace for power
S6
Via to ground plane
S3
S7
Via to signal plane
S4
S8
C
1 kΩ
C
C
VFP
S2
FF
S5
SF
VDD
S1
D
VSS
VFN
C
Wide (low inductance)
trace for power
EN
Figure 10-5. TMUX7349FPW Layout Example
Wide (low inductance)
trace for power
1 kΩ
C
Wide (low inductance)
trace for power
Figure 10-6. TMUX7348FQFN Layout Example
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VDD
A1
GND
A0
EN
C
C
C
S1B
VSS
S4B
Via to signal plane
S4A
DB
1 kΩ
C
C
VFP
S3A
FF
Via to ground plane
SF
S3B
DA
S2B
S2A
VFN
S1A
C
C
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
1 kΩ
C
Wide (low inductance)
trace for power
Figure 10-7. TMUX7349FQFN Layout Example
48
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
•
•
•
•
•
•
Texas Instruments, Eliminate Power Sequencing with Powered-Off Protection Signal Switches application
brief
Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
Texas Instruments, Improving Analog Input Modules Reliability Using Fault Protected Multiplexers application
report
Texas Instruments, Multiplexers and Signal Switches Glossary application report
Texas Instruments, Protection Against Overvoltage Events, Miswiring, and Common Mode Voltages
application report
Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application
report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TMUX7348FPWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TM7348F
Samples
TMUX7348FRTJR
ACTIVE
QFN
RTJ
20
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMUX
7348F
Samples
TMUX7349FPWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TM7349F
Samples
TMUX7349FRTJR
ACTIVE
QFN
RTJ
20
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMUX
7349F
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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