Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
TPS3808Gxx-Q1 Low-Quiescent-Current Programmable-Delay Supervisory Circuit
1 Features
3 Description
•
•
The TPS3808Gxx-Q1 microprocessor supervisory
circuits monitor system voltages from 0.4 V to 5 V,
asserting an open-drain RESET signal when the
SENSE voltage drops below a preset threshold or
when the manual reset (MR) pin drops to a logic low.
The RESET output remains low for the useradjustable delay time after the SENSE voltage and
MR return above their thresholds.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
Power-On Reset Generator With Adjustable Delay
Time: 1.25 ms to 10 s
Very Low Quiescent Current: 2.4 μA Typical
High Threshold Accuracy: 0.5% Typical
Fixed Threshold Voltages for Standard Voltage
Rails From 1.2 V to 5 V and Adjustable Voltage
Down to 0.4 V Are Available
Manual Reset (MR) Input
Open-Drain RESET Output
Temperature Range: –40°C to +125°C
Small SOT-23 Package and WSON Package
(TPS3808G01QDRVRQ1 only)
The TPS3808Gxx-Q1 device uses a precision
reference to achieve 0.5% threshold accuracy for VIT
≤ 3.3 V. The reset delay time can be set to 20 ms by
disconnecting the CT pin, 300 ms by connecting the
CT pin to VDD using a resistor, or can be useradjusted from 1.25 ms to 10 s by connecting the CT
pin to an external capacitor. The TPS3808Gxx-Q1
has a very low typical quiescent current of 2.4 μA, so
it is well suited for battery-powered applications. The
device is available in a small SOT-23 package (one
option available in WSON) and is fully specified over
a temperature range of –40°C to +125°C (TJ).
2 Applications
•
•
•
•
DSP or Microcontroller Applications
FPGA and ASIC Applications
Automotive Vision
Automotive Radar
For more information about TI's voltage supervisor
portfolio, visit the Supervisor and Reset IC Overview
Page page.
Device Information(1)
PART NUMBER
TPS3808Gxx-Q1
PACKAGE
BODY SIZE (NOM)
SOT-23 (6)
2.90 mm × 1.60 mm
WSON (6)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
1.2 V
3.3 V
SENSE
VDD
TPS3808G12
RESET
CT
GND
SENSE VDD
TPS3808G33
MR
CT
RESET
GND
VI/O
VCORE
DSP
GPIO
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagrams ....................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11
9
Applications and Implementation ...................... 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (June 2015) to Revision J
Page
•
Added column for WSON pins .............................................................................................................................................. 3
•
Changed unit for last row of td row in Timing Requirements from "ms" to "s" and "TYP" to "NOM" in middle unit column... 6
Changes from Revision H (June 2012) to Revision I
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision G (November, 2010) to Revision H
•
2
Page
Changed ISENSE from µA to nA................................................................................................................................................ 5
Submit Documentation Feedback
Copyright © 2007–2017, Texas Instruments Incorporated
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
www.ti.com
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
5 Device Comparison Table
ORDERABLE PART NUMBER
NOMINAL SUPPLY VOLTAGE
THRESHOLD VOLTAGE (VIT)
Adjustable
0.405 V
TPS3808G01QDRVRQ1
TPS3808G01QDBVRQ1
TPS3808G12QDBVRQ1
1.2 V
1.12 V
TPS3808G125QDBVRQ1
1.25 V
1.16 V
TPS3808G15QDBVRQ1
1.5 V
1.4 V
TPS3808G18QDBVRQ1
1.8 V
1.67 V
TPS3808G30QDBVRQ1
3V
2.79 V
TPS3808G33QDBVRQ1
3.3 V
3.07 V
TPS3808G50QDBVRQ1
5V
4.65 V
6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
RESET
1
6
DRV Package
6-Pin WSON With Thermal Pad
Top View
VDD
SENSE
CT
VDD
GND
2
5
SENSE
MR
3
4
CT
1
6
2
5
3
4
RESET
GND
MR
Pin Functions
PIN
NAME
SOT-23
WSON
I/O
DESCRIPTION
Reset period programming pin. Connecting this pin to VDD through a 40-kΩ
to 200-kΩ resistor or leaving it open results in fixed delay times (see Electrical
Characteristics). Connecting this pin to a ground referenced capacitor ≥ 100
pF gives user-programmable delay time. See the Selecting the Reset Delay
Time for more information.
CT
4
3
I
GND
2
5
—
MR
3
4
I
Manual reset. Driving this pin low asserts RESET. MR is internally tied to VDD
by a 90-kΩ pullup resistor.
Ground
RESET
1
6
O
Reset. This is an open-drain output that is driven to a low impedance state
when RESET is asserted (either the SENSE input is lower than the threshold
voltage (VIT) or the MR pin is set to a logic low). RESET remains low
(asserted) for the reset period after both SENSE is above VIT and MR is set to
a logic high. A pullup resistor from 10 kΩ to 1 MΩ must be used on this pin
and allows the reset pin to attain voltages higher than VDD.
SENSE
5
2
I
Voltage sense. This pin is connected to the voltage to be monitored. If the
voltage at this terminal drops below the threshold voltage (VIT), RESET is
asserted.
VDD
6
1
I
Supply voltage. It is good analog design practice to place a 0.1-μF ceramic
capacitor close to this pin.
Thermal Pad
—
Pad
—
Copyright © 2007–2017, Texas Instruments Incorporated
Thermal pad; connect to ground plan to enhance thermal performance of the
package.
Submit Documentation Feedback
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
3
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD
Input voltage
–0.3
7
V
VCT
CT voltage
–0.3
(VDD + 0.3)
V
VMR,
VRESET,
VSENSE
MR, RESET, SENSE voltage
–0.3
7
V
IRESET
RESET pin current
5
mA
TJ
Operating junction temperature (2)
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electric Characteristics is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Due to the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
UNIT
TPS3808G125QDBVRQ1 IN SOT-23 PACKAGE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per AEC Q100-002 (1)
±2000
Charged device model (CDM), per AEC Q100-011
±1000
Machine Model (MM)
V
±50
TPS3808GXX-Q1 IN SOT-23 PACKAGE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per AEC Q100-002 (1)
±2000
Charged device model (CDM), per AEC Q100-011
±500
V
TPS3808G01QDRVRQ1 IN SON PACKAGE
V(ESD)
(1)
Electrostatic
discharge
Human body model (HBM), per AEC Q100-002 (1)
±2000
Charged device model (CDM), per AEC Q100-011
±500
Machine Model (MM)
±50
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD input supply
NOM
MAX
UNIT
1.8
6.5
V
VSENSE SENSE pin voltage
0
VDD
V
MR Manual reset pin voltage
0
VDD
V
4
Submit Documentation Feedback
Copyright © 2007–2017, Texas Instruments Incorporated
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
www.ti.com
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
7.4 Thermal Information
TPS3808Gxx-Q1
THERMAL METRIC (1)
DBV (SOT-23)
DRV (WSON)
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
180.9
178.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
117.8
95.6
°C/W
RθJB
Junction-to-board thermal resistance
27.8
135
°C/W
ψJT
Junction-to-top characterization parameter
18.9
6.3
°C/W
ψJB
Junction-to-board characterization parameter
27.3
136.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
7.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
1.8 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to +125°C) (unless
otherwise noted), typical values at TJ = 25°C
PARAMETER
VDD
TEST CONDITIONS
Input supply range
IDD
Supply current (into VDD pin)
VOL
Low-level output voltage
Power-up reset voltage (1)
5
VDD = 6.5 V, RESET not asserted,
MR, RESET, CT open
2.7
6
0.3
1.8 V ≤ VDD ≤ 6.5 V, IOL = 1 mA
0.4
VOL (max) = 0.2 V, I
RESET
= 15 μA
3.3 V < VIT ≤ 5 V
–40°C < TJ < 85°C
0.8
–2%
±1%
2%
–1.5%
±0.5%
1.5%
–2%
±1%
2%
–1.25%
±0.5%
1.25%
–1.5%
±0.5%
1.5%
1.5
3
TPS3808G01-Q1
R MR
MR internal pullup resistance
ISENSE Input current at SENSE pin
IOH
RESET leakage current
CIN
Input capacitance, any pin
VIL
MR logic low input
VIH
MR logic high input
(1)
–40°C < TJ < 85°C
VSENSE = VIT
70
TPS3808G01-Q1
UNIT
V
μA
1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA
3.3 V < VIT ≤ 5 V
Hysteresis on VIT pin
6.5
2.4
VIT ≤ 3.3 V
VHYS
MAX
VDD = 3.3 V, RESET not asserted,
MR, RESET, CT open
VIT ≤ 3.3 V
Negative-going input
threshold accuracy
TYP
1.8
TPS3808G01-Q1
VIT
MIN
1
2
1
2.5
90
25
1.7
V RESET = 6.5 V, RESET not asserted
VIN = 0 V to VDD
5
Other pins
VIN = 0 V to 6.5 V
5
%VIT
nA
μA
300
CT pin
V
kΩ
–25
VSENSE = 6.5 V
V
nA
pF
0
0.3 VDD
V
0.7 VDD
VDD
V
Power-up reset voltage is the lowest supply voltage (VDD) at which RESET becomes active (trise(VDD) ≥ 15 μs/V).
Copyright © 2007–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
5
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
www.ti.com
7.6 Timing Requirements
CT = Open
td
RESET delay
time
CT = VDD
CT = 100 pF
See Figure 1
CT = 180 nF
tpHL
tw
MIN
NOM
MAX
12
20
28
180
300
420
0.75
1.25
1.75
0.7
1.2
1.7
UNIT
ms
s
Propagation
delay
MR to RESET
VIH = 0.7 VDD, VIL = 0.3 VDD
150
ns
High-level to
low-level
RESET delay
SENSE to
RESET
VIH = 1.05 VIT, VIL = 0.95 VIT
20
μs
SENSE
VIH = 1.05 VIT, VIL = 0.95 VIT
20
MR
VIH = 0.7 VDD, VIL = 0.3 VDD
0.001
Maximum
transient
duration
μs
VDD
0.8V
0.0V
RESET
tD = Reset Delay
tD
tD
tD
= Undefined State
SENSE
VIT + VHYS
VIT
MR
0.7VDD
0.3VDD
Time
Figure 1. MR and SENSE Reset Timing Diagram
6
Submit Documentation Feedback
Copyright © 2007–2017, Texas Instruments Incorporated
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
www.ti.com
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
7.7 Typical Characteristics
10
1.0
8
0.8
6
0.6
Normalized VIT (%)
Normalized RESET Timeout Period (%)
At TJ = 25°C, VDD = 3.3 V, RLRESET = 100 kΩ, and CLRESET = 50 pF (unless otherwise noted)
4
2
0
−2
−4
0.4
0.2
0
−0.2
−0.4
−6
−0.6
−8
−0.8
−1.0
−10
−50
−30
−10
10
30
50
70
90
110
−50
130
−30
−10
10
50
70
90
110
130
Figure 3. Normalized Sense Threshold Voltage (VIT) vs
Temperature
Figure 2. Normalized RESET Time-out Period vs
Temperature (CT = Open, CT = VDD, CT = Any)
0.8
VOL Low−Level RESET Voltage (V)
4.5
VOL Low−Level RESET Voltage (V)
30
Temperature (°C)
Temperature (°C)
4.0
3.5
3.0
2.5
2.0
VDD = 1.8 V
1.5
1.0
0.5
0.7
0.6
0.5
0.4
VDD = 3.3 V
0.3
0.2
0.1
VDD = 6.5 V
0
0
0
0.5
1.0
1.5
2.0
2.5
RESET Current (mA)
3.0
3.5
4.0
Figure 4. Low-Level RESET Voltage vs RESET Current
Copyright © 2007–2017, Texas Instruments Incorporated
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
RESET Current (mA)
Figure 5. Low-Level RESET Voltage vs RESET Current
Submit Documentation Feedback
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
7
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
www.ti.com
8 Detailed Description
8.1 Overview
The TPS3808Gxx-Q1 devices are low-current supervisory circuits used to monitor system voltages ranging from
0.4 V to 5 V. The devices assert an active low, open-drain RESET signal when the SENSE voltage drops below
a preset threshold or when the manual reset (MR) pin is asserted to a logic low. The RESET output remains low
for the user-adjustable delay time after the SENSE voltage and MR return above their thresholds. The devices
are also designed to be immune to short negative transients on the SENSE pin. The reset delay time can be
configured by using the CT pin. The delay can be configured to 20 ms by leaving the CT pin floating, it can be
configured to 300 ms by connecting the CT pin to VDD using a resistor, or can be configured from 1.25 ms to 10 s
by connecting the CT pin to an external capacitor.
8.2 Functional Block Diagrams
VDD
VDD
90k
RESET
MR
Reset
Logic
Timer
SENSE
−
CT
+
0.4 V
VREF
GND
Figure 6. Adjustable-Voltage Version
VDD
VDD
90k
RESET
MR
SENSE
Reset
Logic
Timer
R1
−
CT
+
R2
0.4 V
VREF
R1 + R2 = 4 MW
GND
Figure 7. Fixed-Voltage Version
8
Submit Documentation Feedback
Copyright © 2007–2017, Texas Instruments Incorporated
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
www.ti.com
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
8.3 Feature Description
8.3.1 Immunity to SENSE Pin Voltage Transients
The TPS3808Gxx-Q1 is relatively immune to short negative transients on the SENSE pin. Sensitivity to
transients is dependent on threshold overdrive, as shown in the Maximum Transient Duration at Sense vs Sense
Threshold Overdrive Voltage graph (Figure 9). This graph shows the duration that the transient is below VIT
compared to the magnitude of the voltage drop below VIT, or overdrive voltage. The overdrive voltage is
expressed as a percentage of the VIT threshold value. Any combination of transient duration and overdrive
voltage that lies above the curve results in RESET being asserted low. Any transient that lies below the curve is
ignored by the device.
VDD
VIT
Overdrive
Voltage
Transient
Duration
Figure 8. Threshold Overdrive Voltage
Transient Duration below VIT (ms)
100
RESET OCCURS
ABOVE THE CURVE
10
1
0
5
10
15
20
25
30
35
40
45
50
Overdrive (%VIT)
Figure 9. Maximum Transient Duration at Sense vs Sense Threshold Overdrive Voltage
8.3.2 SENSE Input
The SENSE input provides a terminal at which any system voltage can be monitored. If the voltage on this pin
drops below VIT, RESET is asserted low. The comparator has a built-in hysteresis to ensure smooth RESET
assertions and deassertions. It is good analog design practice to put a 1-nF to 10-nF bypass capacitor on the
SENSE input to reduce sensitivity to transients and layout parasitics.
Copyright © 2007–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
9
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
www.ti.com
Feature Description (continued)
The TPS3808G01-Q1 can be used to monitor any voltage rail down to 0.405 V using the circuit shown in
Figure 10.
VIN
VOUT
VDD
VIT′= (1 +
R1
R1
)0.405
R2
TPS3808G01
SENSE
RESET
R2
1nF
GND
Figure 10. Using the TPS3808G01-Q1 to Monitor a User-Defined Threshold Voltage
8.3.3 Manual Reset (MR) Input
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 VDD) on
MR causes RESET to assert low. After MR returns to a logic high and SENSE is above its reset threshold,
RESET is deasserted high after the user-defined reset delay expires. MR is internally tied to VDD using a 90-kΩ
resistor, so this pin can be left unconnected if MR is not used.
See Figure 11 for how MR can be used to monitor multiple system voltages. If the logic signal driving MR does
not go fully to VDD, there will be some additional current draw into VDD as a result of the internal pullup resistor on
MR. To minimize current draw, a logic-level FET can be used as shown in Figure 12.
1.2V
3.3V
SENSE
V DD
SENSE V DD
TPS3808G12
TPS3808G33
RESET
V CORE
DSP
MR
RESET
CT
V I/O
CT
GND
GND
GPIO
GND
Figure 11. Using MR to Monitor Multiple System Voltages
3.3V
V DD SENSE
90kW
CT
TP S38 08xx x
G ND
Figure 12. Using an External MOSFET to Minimize IDD When MR Signal Does Not Go to VDD
10
Submit Documentation Feedback
Copyright © 2007–2017, Texas Instruments Incorporated
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
www.ti.com
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
Feature Description (continued)
8.3.4 Selecting the Reset Delay Time
The TPS3808Gxx-Q1 device has three options for setting the RESET delay time as shown in Figure 13.
Figure 13 (a) shows the configuration for a fixed 300-ms typical delay time by tying CT to VDD; a resistor from
40 kΩ to 200 kΩ must be used. Supply current is not affected by the choice of resistor. Figure 13 (b) shows a
fixed 20-ms delay time by leaving the CT pin open. Figure 13 (c) shows a ground referenced capacitor connected
to CT for a user-defined program time from 1.25 ms to 10 s.
3.3V
3.3V
50kW
3.3V
SENSE VDD
SENSE VDD
SENSE VDD
TPS3808G33
TPS3808G33
TPS3808G33
CT
CT
RESET
RESET
CT
RESET
CT
300ms Delay
Delay (s) = CT (nF) + 0.5 x 10−3 (s)
20ms Delay
175
(c)
(b)
(a)
Figure 13. Configuration Used to Set the RESET Delay Time
The capacitor CT should be ≥100 pF nominal value for the TPS3808Gxx-Q1 to recognize the capacitor is
present. Use Equation 1 to calculate the capacitor value for a given delay time.
CT (nF) = é tD (s) - 0.5 ´ 10-3 (s)ù ´ 175
ë
û
(1)
The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the
external capacitor to 1.23 V. When RESET asserts low, the capacitor is discharged. When the RESET conditions
are cleared, the internal current source is enabled and begins to charge the external capacitor. When the voltage
on this capacitor reaches 1.23 V, RESET deasserts. A low-leakage type capacitor such as a ceramic should be
used and that stray capacitance around this pin may cause errors in the reset delay time.
8.4 Device Functional Modes
Whenever MR pin is set to a logic high and the SENSE input pin is higher than VIT, the open-drain RESET signal
is deasserted high. If MR pin is set to a logic low or the SENSE input pin falls lower than VIT, then RESET is
asserted low. Table 1 is a truth table that describes these operating modes.
Table 1. Truth Table
MR
SENSE > VIT
RESET
L
0
L
L
1
L
H
0
L
H
1
H
Copyright © 2007–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
11
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
www.ti.com
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS3808Gxx-Q1 microprocessor supervisory product family is designed to assert a RESET signal when
either the SENSE pin voltage drops below VIT or the manual reset (MR) is driven low. The RESET output
remains asserted for a user-adjustable time after both the manual reset (MR) and SENSE voltages return above
the respective thresholds. A broad range of voltage threshold and reset delay time adjustments are available,
allowing these devices to be used in a variety of applications. Reset threshold voltages can be factory-set from
0.82 V to 3.3 V or from 4.4 V to 5 V, while the TPS3808G01-Q1 can be set to any voltage above 0.405 V using
an external resistor divider. Two preset delay times are also user-selectable: connecting the CT pin to VDD results
in a 300-ms reset delay, while leaving the CT pin open yields a 20-ms reset delay. Additionally, connecting a
capacitor between CT and GND allows the designer to select any reset delay period from 1.25 ms to 10 s.
9.2 Typical Application
3.3V
VDD
VDD
50 lQ
TPS3808G33-Q1
___
MR
_____
RESET
SENSE
CT
CT
Processor
RESET
GND
GND
Figure 14. TPS3808G33-Q1 Typical Application
3.3V
VDD
VDD
50 lQ
R1
TPS3808G01-Q1
SENSE
CT
1 nF
R2
CT
___
MR
_____
RESET
Processor
RESET
GND
GND
Figure 15. TPS3808G01-Q1 Typical Application
12
Submit Documentation Feedback
Copyright © 2007–2017, Texas Instruments Incorporated
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
www.ti.com
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
Typical Application (continued)
9.2.1 Design Requirements
The TPS3808Gxx-Q1 device must monitor a 3.3-V input voltage, and drive an active-low reset to the processor
when the input voltage drops below the recommended operating voltage of the processor.
9.2.2 Detailed Design Procedure
To monitor the 3.3-V input voltage, TPS3808G33-Q1 is used and the 3.3-V supply is connected directly to the
SENSE pin. The open-drain RESET output is connected to VDD through a 50-kΩ resistor. To select the output
delay on the RESET pin, connect the CT pin to VDD, left floating, or connect through a capacitor to GND. For
more details on selecting this delay, see Selecting the Reset Delay Time.
When using TPS3808G01-Q1, select R1 and R2 resistor values to select the threshold voltage based on the
following equation: VIT = (1 + R1 / R2) × 0.405.
9.2.3 Application Curves
100
4.0
3.5
IDD (mA)
RESET Timeout (sec)
125ºC
3.0
85ºC
2.5
2.0
25ºC
1.5
1.0
10
−40°C, 25°C, 125°C
1
0.1
0.01
−40ºC
0.5
0
0
1
2
3
4
5
6
VDD (V)
Figure 16. Supply Current vs Supply Voltage
Copyright © 2007–2017, Texas Instruments Incorporated
7
0.001
0.0001
0.001
0.01
0.1
1
10
CT (mF)
Figure 17. RESET Time-out Period vs CT
Submit Documentation Feedback
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
13
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
www.ti.com
10 Power Supply Recommendations
The TPS3808Gxx-Q1 devices are designed to operate from an input supply from 1.8 V to 6.5 V. TI recommends
placing a 0.1-µF capacitor near the VDD pin.
11 Layout
11.1 Layout Guidelines
TI recommends placing the 0.1-µF decoupling capacitor close to the VDD pin. The VDD trace should be able to
carry 6 µA without a significant drop in voltage.
11.2 Layout Example
Input Supply
CVDD
Reset Output
Manual Reset
Signal
1
6
2
5
CT
3
4
Figure 18. Recommended Layout
14
Submit Documentation Feedback
Copyright © 2007–2017, Texas Instruments Incorporated
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1
TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
www.ti.com
SBVS085J – JANUARY 2007 – REVISED JUNE 2017
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS3808G01-Q1
Click here
Click here
Click here
Click here
Click here
TPS3808G12-Q1
Click here
Click here
Click here
Click here
Click here
TPS3808G125-Q1
Click here
Click here
Click here
Click here
Click here
TPS3808G15-Q1
Click here
Click here
Click here
Click here
Click here
TPS3808G18-Q1
Click here
Click here
Click here
Click here
Click here
TPS3808G30-Q1
Click here
Click here
Click here
Click here
Click here
TPS3808G33-Q1
Click here
Click here
Click here
Click here
Click here
TPS3808G50-Q1
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2007–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1
TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3808G01QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
BAZ
TPS3808G01QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PSJQ
TPS3808G125QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
QWZ
TPS3808G12QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CEM
TPS3808G15QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OFV
TPS3808G18QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OBZ
TPS3808G30QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G33QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G50QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CEL
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
