Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS3852
SBVS302 – NOVEMBER 2016
TPS3852 Precision Voltage Supervisor with Programmable Window Watchdog Timer
1 Features
3 Description
•
•
•
•
•
The TPS3852 is a precision voltage supervisor with
an integrated window watchdog timer. The TPS3852
includes a precision undervoltage supervisor with an
undervoltage threshold (VITN) that achieves 0.8%
accuracy over the specified temperature range of
–40°C to +125°C. In addition, the TPS3852 includes
accurate hysteresis making the device ideal for use
with tight tolerance systems. The supervisor RESET
delay features a 15% accuracy, high-precision delay
timer.
1
•
•
•
•
•
VDD Input Voltage Range: 1.6 V to 6.5 V
0.8% Voltage Threshold Accuracy
Low Supply Current: IDD = 10 µA (typical)
User-Programmable Watchdog Timeout
Factory Programmed Precision Watchdog and
Reset Timers:
– ±15% Accurate WDT and RST Delays
Open-Drain Outputs
Manual Reset Input (MR)
Precision Undervoltage Monitoring
– Supports Common Rails from 1.8 V to 5 V
– 4% and 7% Thresholds Available
– 0.5% Hysteresis
Watchdog Disable Feature
Available in a Small 3-mm × 3-mm, 8-Pin VSON
Package
2 Applications
•
•
•
•
•
•
•
The TPS3852 includes a programmable window
watchdog timer for a wide variety of applications. The
dedicated watchdog output (WDO) enables increased
resolution to help determine the nature of fault
conditions. The watchdog timeouts can be
programmed either by an external capacitor, or by
factory-programmed default delay settings. The
watchdog can be disabled to avoid undesired
watchdog timeouts during the development process.
The TPS3852 is available in a small 3.00-mm × 3.00mm, 8-pin VSON package.
Device Information(1)
Safety Critical Applications
Telematics Control Units
High-Reliability Industrial Systems
Patient Monitoring
Industrial Control Systems
FPGAs and ASICs
Microcontrollers and DSPs
PART NUMBER
PACKAGE
TPS3852
BODY SIZE (NOM)
VSON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Space
Space
Typical Application Circuit
Undervoltage Threshold (VITN) Accuracy vs
Temperature
3.3 V
0.5
Unit 1
Unit 2
VDD
Microcontroller
VDD
RESET
RESET
SET1
WDO
NMI
MR
WDI
GPIO
CWD
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Unit 3
Unit 4
Unit 5
Average
0.3
Accuracy (%)
TPS3852
0.1
-0.1
-0.3
-0.5
-50
-25
0
25
50
Temperature (qC)
75
100
125
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 19
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
2
DATE
REVISION
NOTES
November 2016
*
Initial release.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
TPS3852
www.ti.com
SBVS302 – NOVEMBER 2016
5 Pin Configuration and Functions
DRB Package
VSON-8 (8-Pins)
Top View
VDD
1
CWD
2
MR
3
GND
4
Thermal
Pad
8
RESET
7
WDO
6
WDI
5
SET1
Not to scale
Pin Functions
NAME
NO.
I/O
DESCRIPTION
CWD
2
—
Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and
ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected (NC) further
enables the selection of the preset watchdog timeouts; see the Timing Requirements table.
When using a capacitor, the TPS3852 determines the window watchdog upper boundary with Equation 1. See
Table 3 and the CWD Functionality section for additional information.
GND
4
—
Ground pin
MR
3
I
Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to VDD. RESET remains
low for a fixed reset delay (tRST) time after MR is deasserted (high).
RESET
8
O
Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). RESET goes
low when VDD goes below the undervoltage threshold (VITN). When VDD is within the normal operating range, the
RESET timeout-counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined
below the specified power-on-reset (POR) voltage (VPOR). Above POR, RESET goes low and remains low until the
monitored voltage is within the correct operating range (above VITN+VHYST) and the RESET timeout is complete.
SET1
5
I
Logic input. Grounding the SET1 pin disables the watchdog timer.
VDD
1
I
Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.
WDI
6
I
Watchdog input. A falling transition (edge) must occur at this pin between the lower (tWDL(max)) and upper (tWDU(min))
window boundaries in order for WDO to not assert.
When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. The input at WDI is ignored
when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is disabled, then
WDI cannot be left unconnected and must be driven to either VDD or GND.
WDO
7
O
Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). WDO goes
low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout
occurs, WDO goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a highimpedance state.
—
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
Thermal pad
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
3
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage range
VDD
–0.3
7
V
Output voltage range
RESET, WDO
–0.3
7
V
SET1, WDI, MR
–0.3
7
V
CWD, CRST
–0.3
VDD + 0.3 (2)
V
Output pin current
±20
mA
Input current (all pins)
±20
mA
Voltage ranges
Continuous total power dissipation
See Thermal Information
Operating junction, TJ
Temperature
(3)
Operating free-air temperature, TA
(3)
Storage, Tstg
(1)
(2)
(3)
–40
150
°C
–40
150
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The absolute maximum rating is VDD + 0.3 V or 7.0 V, whichever is smaller.
Assume that TJ = TA as a result of the low dissipated power in this device.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Supply pin voltage
1.6
6.5
V
VSET1
SET1 pin voltage
0
6.5
V
VMR
MR pin voltage
0
6.5
V
CCWD
Watchdog timing capacitor
0.1 (1)
1000 (1)
nF
CWD
Pull-up resistor to VDD
9
10
11
kΩ
RPU
Pull-up resistor, RESET and WDO
1
10
100
kΩ
IRESET
RESET pin current
10
mA
IWDO
Watchdog output current
10
mA
TJ
Junction Temperature
125
°C
(1)
4
–40
Using a CCWD capacitor of 0.1 nF or 1000 nF gives a tWDU(typ) of 62.74 ms or 77.45 seconds, respectively.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
TPS3852
www.ti.com
SBVS302 – NOVEMBER 2016
6.4 Thermal Information
TPS3852
THERMAL METRIC (1)
DRB (VSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
50.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.6
°C/W
RθJB
Junction-to-board thermal resistance
25.8
°C/W
ψJT
Junction-to-top characterization parameter
1.3
°C/W
ψJB
Junction-to-board characterization parameter
25.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
At VITN + VHYST ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, T J ≤ 125°C, unless otherwise noted. The
open-drain pull-up resistors are 10 kΩ for each output. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GENERAL CHARACTERISTICS
VDD (1)
Supply voltage
IDD
Supply Current
1.6
10
6.5
V
19
µA
0.8
V
RESET FUNCTION
VPOR (2)
Power-on reset voltage
VUVLO (3)
Under Voltage Lock Out Voltage
VITN
Undervoltage threshold accuracy, entering
RESET
VDD falling
VITN – 0.8%
VHYST
Hysteresis voltage
VDD rising
0.2%
0.5%
0.8%
IMR
MR pin internal pull-up current
VMR = 0 V
500
620
700
nA
IRESET = 15 µA, VOL(MAX) = 0.25 V
1.35
V
VITN + 0.8%
WINDOW WATCHDOG FUNCTION
ICWD
CWD pin charge current
VCWD
CWD pin threshold voltage
CWD = 0.5 V
VOL
RESET, WDO output low
VDD = 5 V,
IRESET = IWDO = 3 mA
ID
RESET, WDO output leakage current, opendrain
VDD = VITN + VHYST,
VRESET = VWDO = 6.5 V
VIL
Low-level input voltage (MR, SET1)
VIH
High-level input voltage (MR, SET1)
VIL(WDI)
Low-level input voltage (WDI)
VIH(WDI)
High-level input voltage (WDI)
(1)
(2)
(3)
337
375
413
nA
1.192
1.21
1.228
V
0.4
V
1
µA
0.25
V
0.8
V
0.3 × VDD
0.8 × VDD
V
V
During power on, VDD must be a minimum 1.6 V for at least 300 µs before RESET correlates with VDD.
When VDD falls below VPOR, RESET and WDO are undefined.
When VDD falls below UVLO, RESET is driven low.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
5
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
6.6 Timing Requirements
At VITN + VHYST ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, T J ≤ 125°C, unless otherwise noted. The
open-drain pull-up resistors are 10 kΩ for each output. Typical values are at TJ = 25°C.
MIN
tINIT
TYP
CWD pin evaluation period
Minimum MR, SET1 pin pulse duration
Startup delay
MAX
UNIT
381
µs
1
µs
300
µs
RESET FUNCTION
tRST
Reset timeout period
170
tRST-DEL VDD to RESET delay
tMR-DEL
200
VDD = VITN + VHYST + 2.5%
35
VDD = VITN - 2.5%
17
MR to RESET delay
230
ms
µs
200
ns
Watchdog Function
CWD = NC, SET1 = 0 (1)
Watchdog disabled
CWD = NC, SET1 = 1 (1)
tWDL
Window watchdog lower boundary
680
800
CWD = 10kΩ to VDD,
SET1 = 0 (1)
1.5
1.85
CWD = NC, SET1 = 0 (1)
1360
setup
tWD-DEL
(1)
1600
CWD = 10kΩ to VDD,
SET1 = 0 (1)
ms
1840
ms
12.7
ms
Watchdog disabled
CWD = 10kΩ to VDD,
SET1 = 1 (1)
tWD-
2.2
Watchdog disabled
CWD = NC, SET1 = 1 (1)
Window watchdog upper boundary
ms
Watchdog disabled
CWD = 10kΩ to VDD,
SET1 = 1 (1)
tWDU
920
9.3
11.0
Setup time required for part to respond to changes on WDI after
being enabled
150
µs
Minimum WDI pulse width
50
ns
WDI to WDO Delay
50
ns
SET1 = 0 means VSET1 < VIL, SET1 = 1 means VSET1 > VIH
VITN + VHYST
VITN
VDD
VPOR
tRST
tRST-DEL
tWDL < t < tWDU (1)
RESET
t < tWDU
t < tWDU
WDI
VITN
tRST
X
X
t < tWDL
WDO
tRST
(1)
See Figure 2 for WDI timing requirements.
Figure 1. Timing Diagram
6
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
TPS3852
www.ti.com
SBVS302 – NOVEMBER 2016
Early Fault
WDI
WDO
Correct Operation
WDI
WDO
Late Fault
WDI
WDO
Valid
Window
Window
Timing
tWDL(min)
tWDL(typ)
tWDL(max)
tWDU(min)
tWDU(typ)
tWDU(max)
= Tolerance Window
Figure 2. TPS3852 Window Watchdog Timing
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
7
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
6.7 Typical Characteristics
All Typical Characteristics curves are taken at 25°C with, 1.6 V ≤ VDD ≤ 6.5 V unless other wise noted.
0.7
Manual Reset Threshold (V)
Supply Current (PA)
16
12
8
-40qC
0qC
25qC
105qC
125qC
4
0.6
0.5
0.4
0
0
1
2
3
4
VDD (V)
5
6
0.3
-50
7
VIL
VIH
-25
0
25
50
Temperature (qC)
75
100
125
VDD = 1.6 V
Figure 3. Supply Current vs VDD
Figure 4. MR Threshold vs Temperature
380
0.5
Unit 3
Unit 4
Unit 5
Average
0.3
376
Accuracy (%)
CWD Charging Current (nA)
Unit 1
Unit 2
372
368
0.1
-0.1
-0.3
1.6 V
6.5 V
364
-50
-25
0
25
50
Temperature (qC)
75
100
-0.5
-50
125
-25
0
25
50
Temperature (qC)
75
100
125
TPS3852G33
Figure 6. VITN + VHYST Accuracy vs Temperature
Figure 5. CWD Charging Current vs Temperature
45
0.5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
40
35
Frequency (%)
Accuracy (%)
0.3
0.1
-0.1
30
25
20
15
10
-0.3
5
-0.5
-50
0
-25
0
25
50
Temperature (qC)
75
100
TPS3852G33
-0.8
-0.6
-0.4 -0.2
0
0.2
0.4
VITN + VHYST Accuracy (%)
0.6
0.8
Includes G and H versions; with 3.3-V nominal monitored voltage;
total units = 15,536
Figure 7. VITN Accuracy vs Temperature
8
125
Figure 8. VITN + VHYST Accuracy Histogram
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
TPS3852
www.ti.com
SBVS302 – NOVEMBER 2016
Typical Characteristics (continued)
All Typical Characteristics curves are taken at 25°C with, 1.6 V ≤ VDD ≤ 6.5 V unless other wise noted.
45
70
40
60
50
30
Frequency (%)
Frequency (%)
35
25
20
15
40
30
20
10
10
5
0
0
-0.8
-0.6
-0.4
-0.2
0
0.2
VITN Accuracy (%)
0.4
0.6
0.8
0.2
Includes G and H versions; with 3.3-V nominal monitored voltage;
total units = 15,536
0.5
Hysteresis (%)
0.65
0.8
Includes G and H versions; with 3.3-V nominal monitored voltage;
total units = 15,536
Figure 9. VITN Accuracy Histogram
Figure 10. Hysteresis Histogram
1.6
1.6
-40qC
0qC
25qC
105qC
125qC
1.4
1.2
-40qC
0qC
25qC
105qC
125qC
1.4
1.2
1
VOL (V)
1
VOL (V)
0.35
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
0
1
2
3
4
5
6
0
1
2
IRESET (mA)
VDD = 1.6 V
3
IRESET (mA)
4
5
6
VDD = 6.5 V
Figure 11. Low-Level RESET Voltage vs RESET Current
Figure 12. Low-Level RESET Voltage vs RESET Current
50
210
-40qC
0qC
45
25qC
105qC
125qC
-40qC
0qC
25qC
105qC
125qC
Propagation Delay (ms)
Propagation Delay (Ps)
40
35
30
25
20
15
205
200
195
10
5
0
190
0
2
4
6
Overdrive (%)
8
TPS3852G33 entering undervoltage
10
0
2
4
6
Overdrive (%)
8
10
TPS3852G33 exiting undervoltage
Figure 13. Propagation Delay vs Overdrive
Figure 14. Propagation Delay (tRST) vs Overdrive
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
9
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
Typical Characteristics (continued)
All Typical Characteristics curves are taken at 25°C with, 1.6 V ≤ VDD ≤ 6.5 V unless other wise noted.
25
Glitch Immunity (Ps)
Overdrive = 3%
Overdrive = 5%
Overdrive = 7%
Overdrive = 9%
Overdrive = 10%
20
15
10
5
-50
-25
0
25
50
Temperature (qC)
75
100
125
VITN = 3.168 V
Figure 15. High to Low Glitch Immunity vs Temperature
10
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
TPS3852
www.ti.com
SBVS302 – NOVEMBER 2016
7 Detailed Description
7.1 Overview
The TPS3852 is a high-accuracy voltage supervisor with an integrated window watchdog timer. This device
includes a precision undervoltage supervisor with a threshold that achieves 0.8% accuracy over the specified
temperature range of –40°C to +125°C. In addition, the TPS3852 includes accurate hysteresis on the threshold,
making the device ideal for use with tight tolerance systems where voltage supervisors must ensure a RESET
before the minimum supply tolerance of the microprocessor or system-on-a-chip (SoC) is reached.
7.2 Functional Block Diagram
VDD
R1
RESET
R2
Precision
Clock
Reference
VDD
CWD
WDO
State
Machine
Cap
Control
MR
WDI
SET1
GND
Copyright © 2016, Texas Instruments Incorporated
(1)
Note: R1 + R2 = 4.5MΩ
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
11
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
7.3 Feature Description
7.3.1 RESET
Connect RESET to VPU through a 1-kΩ to 100-kΩ pullup resistor. RESET remains high (deasserted) when VDD is
greater than the negative threshold voltage (VITN). If VDD falls below the negative threshold (VITN), then RESET is
asserted, driving the RESET pin to low impedance. When VDD rises above VITN + VHYST, a delay circuit is
enabled that holds RESET low for a specified reset delay period (tRST). When the reset delay has elapsed, the
RESET pin goes to a high-impedance state and uses a pullup resistor to hold RESET high. The pullup resistor
must be connected to the desired voltage rail to allow other devices to be connected at the correct interface
voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor values. The
pullup resistor value is determined by output logic low voltage (VOL), leakage current (ID), and the current through
the RESET pin IRESET.
7.3.2 Manual Reset MR
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR
causes RESET to assert. After MR returns to a logic high and VDD is above VITN + VHYST, RESET is deasserted
after the reset delay time (tRST). If MR is not controlled externally, then MR can either be connected to VDD or left
floating because the MR pin is internally pulled up. When MR is asserted, the watchdog is disabled and all
signals input to WDI are ignored.
7.3.3 UV Fault Detection
The TPS3852 features undervoltage detection for common rails between 1.8 V and 5 V. The voltage is monitored
on the input rail of the device. If VDD drops below VITN, then RESET is asserted (driven low). When VDD is above
VITN + VHYST, RESET deasserts after tRST, as shown in Figure 16. The internal comparator has built-in hysteresis
that provides some noise immunity and ensures stable operation. Although not required in most cases, for noisy
applications, good analog design practice is to place a 1-nF to 100-nF bypass capacitor close to the VDD pin to
reduce sensitivity to transient voltages on the monitored signal.
VITN + VHYST
VDD
VITN
tRST + tRST-DEL
tRST-DEL
RESET
Undervoltage Limit
Figure 16. Undervoltage Detection
7.3.4 Watchdog Mode
This section provides information for the watchdog mode of operation.
7.3.4.1 SET1
The SET1 pin can enable and disable the watchdog timer. If SET1 is set to GND, the watchdog timer is disabled
and WDI is ignored. When the watchdog is disabled WDO will be in a high impedance state. If the watchdog
timer is disabled, drive the WDI pin to either GND or VDD to ensure that there is no increase in IDD. When SET1
is logic high, the watchdog operates normally. The SET1 pin can be changed dynamically; however, if the
watchdog is going from disabled to enabled there is a setup time tWD-setup where the watchdog does not respond
to changes on WDI, as shown in Figure 17.
12
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
TPS3852
www.ti.com
SBVS302 – NOVEMBER 2016
Feature Description (continued)
VDD
RESET
SET1
150 µs
Watchdog
Enabled/Disabled
Enabled
Disabled
Enabled
Figure 17. Enabling and Disabling the Watchdog
7.3.4.2 Window Watchdog Timer
This section provides information for the window watchdog mode of operation. A window watchdog is typically
employed in safety critical applications where a traditional watchdog timer is inadequate. In a traditional
watchdog there is a maximum time in which a pulse must be issued to prevent the reset from occurring. In a
window watchdog the pulse must be issued between a maximum lower window time (tWDL(max)) and the minimum
upper window time (tWDU(min)) set by the CWD pin.
7.3.4.3 Watchdog Input WDI
WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of
the input signal. For the first pulse, the watchdog acts as a traditional watchdog timer; thus, the first pulse must
be issued before tWDU(min). After the first pulse, to ensure proper functionality of the watchdog timer, always issue
the WDI pulse within the window of tWDL(max) and tWDU(min). If the pulse is issued in this region, then WDO remains
unasserted. Otherwise, the device asserts WDO, putting the WDO pin into a low-impedance state.
The watchdog input (WDI) is a digital pin. In order to ensure there is no increase in IDD, drive the WDI pin to
either VDD or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply
current (IDD) because of the architecture of the digital logic gates. When RESET is asserted, the watchdog is
disabled and all signals input to WDI are ignored. When RESET is no longer asserted, the device resumes
normal operation and no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to
either VDD or GND.
7.3.4.4 CWD
The CWD pin provides the user the functionality of both high precision factory programmed window watchdog
timing options and user programmable window watchdog timing. The CWD pin can be either pulled-up to VDD
through a resistor, have an external capacitor to ground, or be left floating. Every time that the part issues a reset
event and the supply voltage is above VITN the part will try to determine, which of these three options is
connected to the pin. There is an internal state machine that the device goes through to determine which option
is connected to the CWD pin. The state machine can take up to 381 μs to determine if the CWD pin is left
floating, pulled-up through a resistor, or connected to a capacitor.
If the CWD pin is being pulled up to VDD using a pull-up resistor then a 10-kΩ resistor should be used.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
13
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
Feature Description (continued)
7.3.4.5 Watchdog Output WDO
The TPS3852 features a window watchdog with an independent watchdog output (WDO). The independent
watchdog output gives the flexibility to flag when there is a fault in the watchdog timing without performing an
entire system reset. For legacy applications WDO can be tied to RESET. While the RESET output is not
asserted the WDO signal will maintain normal operation. However, when the RESET signal is asserted the WDO
pin will go into a high impedance state. This is due to using the standard RESET timing options when a fault
occurs on WDO. Once RESET is unasserted the window watchdog timer will resume normal operation.
14
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
TPS3852
www.ti.com
SBVS302 – NOVEMBER 2016
7.4 Device Functional Modes
Table 1 summarises the functional modes of TPS3852.
Table 1. Device Functional Modes
VDD
WDI
WDO
RESET
VDD < VPOR
—
—
Undefined
Ignored
High
Low
VPOR ≤ VDD < VDD(min)
VDD(min) ≤ VDD ≤ VITN + VHYST
VDD > VITN (2)
(1)
(2)
(3)
(1)
Ignored
High
Low
tWDL(max) < tPULSE <
tWDU(min) (3)
High
High
tPULSE > tWDU(min) (3)
Low
High
tPULSE < tWDL(max) (3)
Low
High
Only valid before VDD has gone above VITN + VHYST
Only valid after VDD has gone above VITN + VHYST
Where tPULSE is the time between falling edges on WDI
7.4.1 VDD is Below VPOR ( VDD < VPOR)
When VDD is less than VPOR, RESET is undefined and can be either high or low. The state of RESET largely
depends on the load that the RESET pin is experiencing.
7.4.2 Above Power-On-Reset, But Less Than VDD(min) (VPOR ≤ VDD < VDD(min))
When the voltage on VDD is less than VDD(min), and greater than or equal to VPOR, the RESET signal is asserted
(logic low). When RESET is asserted, the watchdog output WDO is in a high-impedance state regardless of the
WDI signal that is input to the device.
7.4.3 Normal Operation (VDD ≥ VDD(min))
When VDD is greater than or equal to VDD(min), the RESET signal is determined by VDD. When RESET is asserted,
WDO goes to a high-impedance state. WDO is then pulled high through the pullup resistor.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
15
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 CWD Functionality
The TPS3852 features three options for setting the watchdog window: connecting a capacitor to the CWD pin,
connecting a pullup resistor to VDD, and leaving the CWD pin unconnected. Figure 18 shows a schematic
drawing of all three options. If this pin is connected to VDD through a 10-kΩ pullup resistor or left unconnected
(high impedance), then the factory-programmed watchdog timeouts are enabled; see the Timing Requirements
table. Otherwise, the watchdog timeout can be adjusted by placing a capacitor from the CWD pin to ground.
VDD
TPS3852
TPS3852
VDD
TPS3852
VDD
VDD
VDD
10 k
375 nA
VDD
375 nA
375 nA
CWD
CWD
CWD
CCWD
Cap
Control
Cap
Control
Cap
Control
User Programmable
Capacitor to GND
CWD
10 NŸ 5HVLVWRU
Unconnected
to VDD
Copyright © 2016, Texas Instruments Incorporated
Figure 18. CWD Charging Circuit
8.1.1.1 Factory-Programmed Timing Options
If using the factory-programmed timing options (listed in Table 2), the CWD pin must either be unconnected or
pulled up to VDD through a 10-kΩ pullup resistor. Using these options enables high-precision, 15% accurate
watchdog timing.
Table 2. Factory-Programmed Watchdog Timing
INPUT
CWD
SET1
MIN
0
NC
1
10 kΩ to VDD
16
WATCHDOG LOWER BOUNDARY (tWDL)
MAX
MIN
920
1360
Watchdog disabled
680
0
1
TYP
WATCHDOG UPPER BOUNDARY (tWDU)
800
1.85
MAX
UNIT
Watchdog disabled
Watchdog disabled
1.5
TYP
1600
1840
ms
13.2
ms
Watchdog disabled
2.2
Submit Documentation Feedback
8.8
11.0
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
TPS3852
www.ti.com
SBVS302 – NOVEMBER 2016
8.1.1.2 Adjustable Capacitor Timing
Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected to
CWD, then a 375-nA current source charges CCWD until VCWD = 1.21 V. The TPS3852 determines the window
watchdog upper boundary with the formula given in Equation 1, where CCWD is in microfarads (µF) and tWDU is in
seconds.
tWDU(typ)(s) = 77.4 × CCWD(µF) + 0.055(s)
(1)
The TPS3852 is limited to using CCWD capacitors between 100 pF and 1 µF. Note that Equation 1 is for ideal
capacitors, capacitor tolerances cause the actual device timing to vary. For the most accurate timing, use
ceramic capacitors with COG dielectric material. As shown in Table 4, when using the minimum capacitance of
100 pF, the watchdog upper boundary is 62.74 ms; whereas with a 1-µF capacitance, the watchdog upper
boundary is 77.455 seconds. If a CCWD capacitor is used, Equation 1 can be used to set tWDU the window
watchdog upper boundary. Table 3 shows how tWDU can be used to calculate tWDL.
Table 3. Programmable CWD Timing
INPUT
CWD
CCWD
(1)
WATCHDOG LOWER BOUNDARY (tWDL)
SET1
MIN
0
1
TYP
WATCHDOG UPPER BOUNDARY (tWDU)
MAX
MIN
tWDU(max) x 0.5
0.85 x tWDU(typ)
Watchdog disabled
tWDU(min) x 0.5
tWDU x 0.5
TYP
MAX
UNIT
Watchdog disabled
tWDU(typ) (1)
1.15 x tWDU(typ)
s
Calculated from Equation 1 using ideal capacitors.
Table 4. tWDU Values for Common Ideal Capacitor Values
CCWD
WATCHDOG UPPER BOUNDARY (tWDU)
UNIT
MIN (1)
TYP
MAX (1)
100 pF
53.32
62.74
72.15
ms
1 nF
112.5
132.4
152.2
ms
10 nF
704
829
953
ms
100 nF
6625
7795
8964
ms
65836
77455
89073
ms
1 µF
(1)
Minimum and maximum values are calculated using ideal capacitors.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
17
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
8.1.2 Overdrive Voltage
Forcing a RESET is dependent on two conditions: the amplitude VDD is beyond the trip point (ΔV1 and ΔV2), and
the length of time that the voltage is beyond the trip point (t1 and t2). If the voltage is just under the trip point for a
long period of time, RESET asserts and the output is pulled low. However, if VDD is just under the trip point for a
few nanoseconds, RESET does not assert and the output remains high. The length of time required for RESET
to assert can be changed by increasing the amount VDD goes under the trip point. If VDD is under the trip point by
10%, the amount of time required for the comparator to respond is much faster and causes RESET to assert
much quicker than when barely under the trip point voltage. Equation 2 shows how to calculate the percentage
overdrive.
Overdrive = |( VDD / VITX – 1) × 100% |
(2)
In Equation 2, VITX corresponds to the threshold trip point. If VDD is exceeding the positive threshold, VITN + VHYST
is used. VITN is used when VDD is falling below the negative threshold. In Figure 19, t1 and t2 correspond to the
amount of time that VDD is over the threshold; the propagation delay versus overdrive for VITN and VITN + VHYST is
illustrated in Figure 13 and Figure 14, respectively.
The TPS3852 is relatively immune to short positive and negative transients on VDD because of the overdrive
voltage.
ûV1
Input Voltage
t1
VITN + VHYST
VDD
VITN
ûV2
t2
Time
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Overdrive Voltage
18
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
TPS3852
www.ti.com
SBVS302 – NOVEMBER 2016
8.2 Typical Application
A typical application for the TPS3852 is shown in Figure 20. The TPS3852G33 is used to monitor the 3.3-V,
VCORE rail powering the microcontroller.
VDD
SENSE
100 k
TPS3852
TPS3890
100 k
100 k
3.3 V
VCORE
Microcontroller
VDD
RESET
RESET
MR
WDO
NMI
SET1
WDI
GPIO
CWD
GND
MR
RESET
CT
6.8 µF
GND
GND
2.2 nF
Copyright © 2016, Texas Instruments Incorporated
Figure 20. Monitoring Supply Voltage and Watchdog Supervision of a Microcontroller
8.2.1 Design Requirements
(1)
Parameter
Design Requirement
Design Result
Watchdog Disable For
Initialization Period
Watchdog must remain disabled for 7 seconds until
logic enables the watchdog timer
7.21 seconds (typ)
Output Logic Voltage
3.3V CMOS
3.3V CMOS
Monitored Rail
3.3 V with a 5% threshold
Worst Case VITN = 3.142 V
(- 4.7% threshold)
Watchdog Window
250 ms, maximum
tWDL(max) = 135 ms, tWDU(min) = 181 ms
Maximum Device Current
Consumption
50 uA
52 uA (worst case) when RESET or WDO is
asserted (1)
Only includes the TPS3852G33 current consumption.
8.2.2 Detailed Design Procedure
8.2.2.1 Monitoring the 3.3V Rail
This application calls for very tight monitoring of the rail with only 5% of variation allowed on the rail. To ensure
this requirement is met, the TPS3852G33 was chosen for its -4% threshold. To calculate the worst-case for VITN,
the accuracy must also be taken into account. The worst-case for VITN can be calculated by Equation 3:
VITN(Worst
Case)
= VITN(typ) x 0.992 = 3.3 x 0.96 x 0.992 = 3.142 V
(3)
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
19
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
8.2.2.2 Calculating RESET and WDO Pullup Resistor
The TPS3852 uses an open-drain configuration for the RESET circuit, as shown in Figure 21. When the FET is
off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull
the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to
ensure that VOL is below the maximum value. To choose the proper pullup resistor, there are three key
specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRESET),
and VOL. The maximum VOL is 0.4 V, meaning that the effective resistor divider created must be able to bring the
voltage on the reset pin below 0.4 V with IRESET kept below 10 mA. For this example, with a VPU of 3.3 V, a
resistor must be chosen to keep IRESET below 50 μA because this value is the maximum consumption current
allowed. To ensure this specification is met, a pullup resistor value of 100 kΩ was selected, which sinks a
maximum of 33 μA when RESET or WDO is asserted. As illustrated in Figure 11, when the RESET current is at
33 μA and the low-level output voltage is approximately zero.
VPU
RESET
RESET
CONTROL
Copyright © 2016, Texas Instruments Incorporated
Figure 21. RESET Open-Drain Configuration
8.2.2.3 Setting the Window Watchdog
As illustrated in Figure 18, there are three options for setting the window watchdog. The design specifications in
this application require the programmable timing option (external capacitor connected to CWD). When a
capacitor is connected to the CWD pin, the window is governed by Equation 4. Equation 4 is only valid for ideal
capacitors, any temperature or voltage derating must be accounted for separately.
t WDU 0.055 0.25 0.055
CCWD PF
0.0025 PF
77.4
77.4
(4)
The nearest standard capacitor value to 2.5 nF is 2.2 nF. Selecting 2.2 nF for the CCWD capacitor gives the
following minimum and maximum timing parameters:
3
t WDU(MIN)
0.85 u t WDU(TYP)
0.85 u 77.4 u 2.2 u 10
0.055
t WDL(MAX)
0.5 u t WDU(MAX)
0.5 u ª1.15 u 77.4 u 2.2 u 10
¬
3
191 ms
(5)
0.055 º 129 ms
¼
(6)
Capacitor tolerance also influence tWDU(MIN) and tWDL(MAX). Select a ceramic COG dielectric capacitor for high
accuracy. For 2.2 nF, COG capacitors are readily available with a 5% tolerance, which results in a 5% decrease
in tWDU(MIN) and a 5% increase in tWDL(MAX), giving 181 ms and 135 ms, respectively. A falling edge must be
issued within this window.
8.2.2.4 Watchdog Disabled During Initialization Period
The watchdog is often needed to be disabled during startup to allow for an initialization period. When the
initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by
the TPS3852. To achieve this setup SET1 must start at GND. In this design, SET1 is controlled by a TPS3890
supervisor. In this application, the TPS3890 was chosen to monitor VDD as well, which means that RESET on the
TPS3890 stays low until VDD rises above VITN. When VDD comes up, the delay time can be adjusted through the
CT capacitor on the TPS3890. With this approach, the RESET delay can be adjusted from a minimum of 25 µs
to a maximum of 30 seconds. For this design, a minimum delay of 7 seconds is needed until the watchdog timer
is enabled. The CT capacitor calculation (see the TPS3890 data sheet) yields an ideal capacitance of 6.59 µF,
giving a closest standard ceramic capacitor value of 6.8 µF. When connecting a 6.8-µF capacitor from CT to
GND, the typical delay time is 7.21 seconds. Figure 22 illustrates the typical startup waveform for this circuit
when the watchdog input is off. Figure 22 illustrates that when the watchdog is disabled, the WDO output
remains high. See the TPS3890 data sheet for detailed information on the TPS3890.
20
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
TPS3852
www.ti.com
SBVS302 – NOVEMBER 2016
8.2.3 Glitch Immunity
Figure 25 shows the high to low glitch immunity for the TPS3852G33 with a 7% overdrive with VDD starting at 3.3
V. This curve shows that VDD can go below the threshold for 5.2 µs without RESET asserting.
8.2.4 Application Curves
Unless otherwise stated, application curves were taken at TA = 25°C.
VDD
2V/div
VDD
2V/div
128 ms
7.94 s
SET1
2V/div
WDI
2V/div
WDO
2V/div
WDO
2V/div
RESET
2V/div
RESET
2V/div
1s/div
50ms/div
Figure 22. Startup Without a WDI Signal
Figure 23. Typical WDI Signal
VDD
1V/div
(yellow)
VDD
1V/div
RESET
1V/div
(green)
5.2 µs
204 ms
RESET
2V/div
2µs/div
50ms/div
Figure 24. Typical RESET Delay
Figure 25. High to Low Glitch Immunity
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
21
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
9 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.6 V and 6.5 V. An
input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog
practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin.
10 Layout
10.1 Layout Guidelines
•
•
•
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
If a CCWD capacitor or pull-up resistor is used place them as close as possible to the CWD pin. If the CWD pin
is left unconnected make sure to minimize the amount of parasitic capacitance on the pin.
The pull-up resistors on RESET and WDO should be placed as close to the pin as possible.
10.2 Layout Example
Vin
RPU1
CVDD
Vin
RPU2
Vin
CCWD
VDD
1
8
RESET
CWD
2
7
WDO
MR
3
6
WDI
GND
4
5
SET1
GND Plane
Denotes a via
Figure 26. Typical Layout For TPS3852
22
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
TPS3852
www.ti.com
SBVS302 – NOVEMBER 2016
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
The TPS3851EVM-780 Evaluation Module can be used to evaluate this part. If this evaluation module is being
used then the part on the EVM must be changed to the TPS3852.
11.1.2 Device Nomenclature
Table 5. Device Nomenclature
DESCRIPTION
NOMENCLATURE
VALUE
TPS3852
(high-accuracy supervisor with window watchdog)
—
—
G
VITN = –4%
H
VITN = –7%
33
3.3 V
X
(nominal threshold as a percent of the nominal
monitored voltage)
yy(y) (1)
(nominal monitored voltage option)
(1)
For example TPS3852G33 corresponds to a 3.3 V nominal monitored voltage with a -4% nominal threshold.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• TPS3890 Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay (SLVSD65)
• TPS3851EVM-780 Evaluation Module (SBVU033)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
23
TPS3852
SBVS302 – NOVEMBER 2016
www.ti.com
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS3852
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3852G33DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
852GA
TPS3852G33DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
852GA
TPS3852H33DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
852PA
TPS3852H33DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
852PA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
