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TPS61161-Q1
SLVSA18A – SEPTEMBER 2009 – REVISED JULY 2015
TPS61161-Q1 White Led Driver with Digital and Pwm Brightness Control for up to 10
LEDs In Series
1 Features
3 Description
•
•
•
•
•
•
•
•
With a 40-V rated integrated switch FET, the
TPS61161-Q1 is a boost converter that drives up to
10 LEDs in series. The boost converter runs at 600kHz fixed switching frequency to reduce output ripple,
improve conversion efficiency, and allow for the use
of small external components.
1
Qualified for Automotive Applications
2.7-V to 18-V Input Voltage Range
38-V Open LED Protection for 10 LEDs
200-mV Reference Voltage With ±2% Accuracy
Flexible Digital and PWM Brightness Control
Built-In Soft Start
Up to 90% Efficiency
2-mm × 2-mm × 0.8-mm 6-pin QFN (DRV)
Package With Thermal Pad
The default white LED current is set with the external
sensor resistor Rset, and the feedback voltage is
regulated to 200 mV, as shown in the typical
application. During the operation, the LED current can
be controlled using the 1-wire digital interface
(EasyScale™ protocol) through the CTRL pin.
Alternatively, a pulse width modulation (PWM) signal
can be applied to the CTRL pin through which the
duty cycle determines the feedback reference
voltage. In either digital or PWM mode, the
TPS61161-Q1 does not burst the LED current;
therefore, it does not generate audible noises on the
output capacitor. For maximum protection, the device
features integrated open LED protection that disables
the TPS61161-Q1 to prevent the output from
exceeding the absolute maximum ratings during open
LED conditions.
2 Applications
•
•
•
Automotive Cluster Backlighting
High-Brightness LED Lighting
White LED Backlighting Media Form Factor
Displays
The TPS61161 is available in a space-saving, 2-mm
× 2-mm QFN (DRV) package with thermal pad.
Device Information(1)
PART NUMBER
PACKAGE
TPS61161-Q1
SON (6)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
L1
22 mH
VI 3 V to 18 V
C1
1 mF
TPS61161–Q1
ON/OFF
DIMMING
CONTROL
VIN
SW
CTRL
FB
COMP GND
C3
220 nF
L1: TDK VLCF5020T-220MR75-1
C1: Murata GRM188R61E105K
C2: Murata GRM21BR71H105K
D1: ONsemi MBR0540T1
D1
38 V Max
C2
1 mF
Rset
10 W
20 mA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61161-Q1
SLVSA18A – SEPTEMBER 2009 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
3
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................... 9
Device Functional Modes........................................ 10
8
Applications and Implementation ...................... 16
8.1 Application Information............................................ 16
8.2 Typical Application .................................................. 16
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
10.3 Thermal Considerations ........................................ 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Original (September 2009) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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5 Pin Configuration and Functions
DRV Package
6-Pin SON With Thermal Pad
Top View
FB
COMP
VIN
Thermal
Pad
CTRL
GND
SW
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
COMP
2
O
Output of the transconductance error amplifier. Connect an external capacitor to this pin to compensate the
regulator.
CTRL
5
I
Control pin of the boost regulator. It is a multi-functional pin which can be used for enable control, PWM and
digital dimming.
FB
1
I
Feedback pin for current. Connect the sense resistor from FB to GND.
GND
3
O
Ground
SW
4
I
This is the switching node of the IC. Connect the inductor between the VIN and SW pin. This pin is also
used to sense the output voltage for open LED protection
VIN
6
I
The input supply pin for the IC. Connect VIN to a supply voltage from 2.7 V to 18 V.
Thermal Pad
—
The thermal pad should be soldered to the analog ground plane. If possible, use thermal via to connect to
ground plane for ideal power dissipation.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage on VIN
(1)
(2)
Voltage on CTRL (2)
VI
MAX
UNIT
20
V
–0.3
20
V
V
–0.3
3
Voltage on SW (2)
–0.3
40
V
TJ
Operating junction temperature range
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Voltage on FB and COMP
(2)
MIN
–0.3
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
Charged-device model (CDM), per AEC Q100-011
±1000
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VI
Input voltage range, VIN
2.7
18
VO
Output voltage range
VIN
38
V
L
Inductor (1)
10
22
µH
fdim
PWM dimming frequency
5
100
kHz
At 10 kHz
0.5%
At 30 kHz
1.5%
V
Duty
PWM duty cycle resolution
CIN
Input capacitor
CO
Output capacitor (1)
0.47
10
µF
TA
Operating ambient temperature
–40
125
°C
(1)
1
µF
These values are recommended values that have been successfully tested in several applications. Other values may be acceptable in
other applications but should be fully tested by the user.
6.4 Thermal Information
TPS61161-Q1
THERMAL METRIC (1)
DRV (SON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
96.1
°C/W
89
RθJB
°C/W
Junction-to-board thermal resistance
65.9
°C/W
ψJT
Junction-to-top characterization parameter
3.2
°C/W
ψJB
Junction-to-board characterization parameter
66.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
40.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
VIN = 3.6 V, CTRL = VIN, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VI
Input voltage range, VIN
IQ
Operating quiescent current into VIN
Device PWM switching no load
2.7
ISD
Shutdown current
CRTL = GND, VIN = 4.2 V
UVLO
Undervoltage lockout threshold
VIN falling
Vhys
Undervoltage lockout hysteresis
2.2
18
V
1.8
mA
1
µA
2.5
V
70
mV
ENABLE AND REFERENCE CONTROL
V(CTRLh)
CTRL logic high voltage
VIN = 2.7 V to 18 V
V(CTRLl)
CTRL logic low voltage
VIN = 2.7 V to 18 V
1.2
R(CTRL)
CTRL pulldown resistor
toff
CTRL pulse width to shutdown
CTRL high to low
2.5
ms
tes_det
EasyScale detection time (1)
CTRL pin low
260
µs
tes_delay
EasyScale detection delay
tes_win
EasyScale detection window time
400
Measured from CTRL high
V
0.4
800
V
1600
kΩ
100
µs
1
ms
VOLTAGE AND CURRENT CONTROL
VREF
Voltage feedback regulation voltage
196
200
204
47
50
53
mV
VFB = 20 mV
17
20
23
2
µA
500
600
700
kHz
90%
93%
V(REF_PWM)
Voltage feedback regulation voltage under
brightness control
VFB = 50 mV
IFB
Voltage feedback input bias current
VFB = 200 mV
fS
Oscillator frequency
Dmax
Maximum duty cycle
tmin_on
Minimum on pulse width
40
ns
Isink
Comp pin sink current
100
µA
Isource
Comp pin source current
100
µA
Gea
Error amplifier transconductance
Rea
Error amplifier output resistance
fea
Error amplifier crossover frequency
VFB = 100 mV
240
320
400
mV
µmho
6
MΩ
5 pF connected to COMP
500
kHz
VIN = 3.6 V
0.3
POWER SWITCH
RDS(on)
N-channel MOSFET on-resistance
ILN_NFET
N-channel leakage current
VSW = 35 V, TA = 25°C
ILIM
N-Channel MOSFET current limit
D = Dmax
ILIM_Start
Start-up current limit
D = Dmax
tHalf_LIM
Time step for half current limit
Vovp
Open LED protection threshold
VIN = 3 V
0.6
0.7
Ω
1
µA
0.84
A
OC and OLP
0.56
0.7
0.4
A
5
37
Measured on the FB pin, percentage
of Vref, Vref = 200 mV and 20 mV
38
ms
39
V
V(FB_OVP)
Open LED protection threshold on FB
50%
tREF
VREF filter time constant
180
µs
tstep
VREF ramp up time
213
µs
EasyScale TIMING
tstart
Start time of program stream
2
tEOS
End time of program stream
2
360
µs
tH_LB
High time low bit
Logic 0
2
180
µs
tL_LB
Low time low bit
Logic 0
2 × tH_LB
360
µs
tH_HB
High time high bit
Logic 1
2 × tL_HB
360
µs
(1)
µs
To select EasyScale mode, the CTRL pin must be low for more than tes_det during tes_win
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Electrical Characteristics (continued)
VIN = 3.6 V, CTRL = VIN, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tL_HB
Low time high bit
Logic 1
VACKNL
Acknowledge output voltage low
Open drain, Rpullup =15 kΩ to VIN
tvalACKN
Acknowledge valid time
See
tACKN
Duration of acknowledge condition
See
TYP
2
MAX
UNIT
180
µs
0.4
V
(2)
2
µs
(2)
512
µs
THERMAL SHUTDOWN
Tshutdown
Thermal shutdown threshold
Thysteresis
Thermal shutdown threshold hysteresis
(2)
160
°C
15
°C
Acknowledge condition active 0, this condition will only be applied in case the RFA bit is set. Open-drain output, line needs to be pulled
high by the host with resistor load.
6.6 Typical Characteristics
Table 1. Table of Graphs
FIGURE
Efficiency TPS61161-Q1
VIN = 3.6 V; 4, 6, 8, 10 LEDs; L = 22 µH
Figure 1
Efficiency TPS61161-Q1
Figure 2
Current limit
TA = 25°C
Figure 3
Current limit
Figure 4
EasyScale step
Figure 5
PWM dimming linearity
VIN = 3.6 V; PWM Freq = 10 kHz and 40 kHz
Figure 5
Output ripple at PWM dimming
8 LEDs; VIN = 3.6 V; ILOAD = 20 mA; PWM Freq = 10 kHz
Figure 7
Switching waveform
8 LEDs; VIN = 3.6 V; ILOAD = 20 mA; L = 22 µH
Figure 8
Start-up
8 LEDs; VIN = 3.6 V; ILOAD = 20 mA; L =22 µH
Figure 9
Open LED protection
8 LEDs; VIN = 3.6 V; ILOAD = 20 mA; L = 22 µH
Figure 10
100
100
VI = 3.6 V
4 LEDs
VI = 12 V
6 LEDs
90
90
8 LEDs
80
Efficiency - %
Efficiency - %
80
10 LEDs
70
VI = 3.6 V
VI = 5 V
70
60
60
4 (12.8 V), 6 (19.2 V) LEDs
8 (25.6 V),10 (32 V) LEDs
50
50
10 LEDs - TPS61161 – Q1
40
40
0
10
20
30
Output Current - mA
40
Figure 1. Efficiency vs Output Current
6
50
0
10
20
30
Output Current - mA
40
50
Figure 2. Efficiency vs Output Current
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1000
1000
900
900
Switch Current Limit - mA
Switch Current Limit - mA
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800
700
600
500
800
700
600
500
400
400
300
20
30
40
50
60
Duty Cycle - %
70
80
300
-40
90
-20
0
20
40
60
80
Temperature - °C
100
120
140
Figure 4. Switch Current Limit vs Temperature
Figure 3. Switch Current Limit vs Duty Cycle
200
200
10 kHz, 40 kHz
180
160
160
FB Voltage - mV
FB Voltage - mV
140
120
100
80
120
80
60
40
40
20
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26
Easy Scale Step Step
28 30 32
Figure 5. FB Voltage vs EasyScale Step
0
0
20
40
60
PWM Duty Cycle - %
80
100
Figure 6. FB Voltage vs PWM Duty Cycle
PWM 2 V/div
SW
20 V/div
VOUT
20 mV/div
AC
VOUT 20 mV/div AC
IL
200 mA/div
ILED 10 mA/div
t - 100 ms/div
t - 1 ms/div
Figure 7. Output Ripple at PWM Dimming
Figure 8. Switching Waveform
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CTRL
5 V/div
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OPEN LED
5 V/div
FB
200 mV/div
VOUT
10 V/div
VOUT
10 V/div
COMP
500 mV/div
IL
200 mA/div
IL
200 mA/div
t - 100 ms/div
t - 2 ms/div
Figure 10. Open LED Protection
Figure 9. Start-Up
8
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7 Detailed Description
7.1 Overview
The TPS61161-Q1 is a high-efficiency, high-output voltage boost converter in small package size, The device is
ideal for driving up to 10 white LED in series. The serial LED connection provides even illumination by sourcing
the same output current through all LEDs, eliminating the need for expensive factory calibration. The device
integrates 40-V/0.7-A switch FET and operates in pulse width modulation (PWM) with 600kHz fixed switching
frequency. For operation see the block diagram. The duty cycle of the converter is set by the error amplifier
output and the current signal applied to the PWM control comparator. The control architecture is based on
traditional current-mode control; therefore, a slope compensation is added to the current signal to allow stable
operation for duty cycles larger than 50%. The feedback loop regulates the FB pin to a low reference voltage
(200mV typical), reducing the power dissipation in the current sense resistor.
7.2 Functional Block Diagram
C2
D1
1
Rset
4
L1
FB
SW
Reference
Control
Error
Amplifer
OLP
Vin
6
COMP
2
C1
PWM Control
C3
5
CTRL
Soft
Start-up
Ramp
Generator
+
Current
Sensor
Oscillator
GND
3
7.3 Feature Description
7.3.1 Soft Start-Up
Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device is
enabled, the voltage at FB pin ramps up to the reference voltage in 32 steps, each step takes 213 µs. This
ensures that the output voltage rises slowly to reduce the input current. Additionally, for the first 5 ms after the
COMP voltage ramps, the current limit of the switch is set to half of the normal current limit spec. During this
period, the input current is kept below 400 mA (typical). See the start-up waveform of a typical example,
Figure 9.
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Feature Description (continued)
7.3.2 Open LED Protection
Open LED protection circuitry prevents IC damage as the result of white LED disconnection. The TPS61161-Q1
monitors the voltage at the SW pin and FB pin during each switching cycle. The circuitry turns off the switch FET
and shuts down the IC as soon as the SW voltage exceeds the Vovp threshold and the FB voltage is less than
half of regulation voltage for 8 clock cycles. As a result, the output voltage falls to the level of the input supply.
The device remains in shutdown mode until it is enabled by toggling the CTRL pin logic. To allow the use of
inexpensive low-voltage output capacitor, the TPS61161-Q1 has different open lamp protection thresholds to
prevent the internal 40V FET from breaking down. The threshold is set at 38 V. The devices can be selected
according to the number of external LEDs and their maximum forward voltage.
7.3.3 Shutdown
The TPS61161-Q1 enters shutdown mode when the CTRL voltage is logic low for more than 2.5 ms. During
shutdown, the input supply current for the device is less than 1 µA (max). Although the internal FET does not
switch in shutdown, there is still a dc current path between the input and the LEDs through the inductor and
Schottky diode. The minimum forward voltage of the LED array must exceed the maximum input voltage to
ensure that the LEDs remain off in shutdown. However, in the typical application with two or more LEDs, the
forward voltage is large enough to reverse bias the Schottky and keep leakage current low.
7.3.4 Undervoltage Lockout
An undervoltage lockout prevents operation of the device at input voltages less than typical 2.2 V. When the
input voltage is below the undervoltage threshold, the device is shutdown and the internal switch FET is turned
off. If the input voltage rises by undervoltage lockout hysteresis, the IC restarts.
7.3.5 Thermal Shutdown
An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded.
The device is released from shutdown automatically when the junction temperature decreases by 15°C.
7.4 Device Functional Modes
7.4.1 LED Brightness Dimming Mode Selection
The CTRL pin is used for the control input for both dimming modes, PWM dimming and 1 wire dimming. The
dimming mode for the TPS61161-Q1 is selected each time the device is enabled. The default dimming mode is
PWM dimming. To enter the 1 wire mode, the following digital pattern on the CTRL pin must be recognized by
the IC every time the IC starts from the shutdown mode.
1. Pull CTRL pin high to enable the TPS61161-Q1, and to start the 1 wire detection window.
2. After the EasyScale detection delay (tes_delay, 100 µs) expires, drive CTRL low for more than the EasyScale
detection time (tes_detect, 260 µs).
3. The CTRL pin must be low for more than EasyScale detection time before the EasyScale detection window
(tes_win, 1 ms) expires. EasyScale detection window starts from the first CTRL pin low to high transition.
The IC immediately enters the 1-wire mode once these three conditions are met. The EasyScale communication
can start before the detection window expires. Once the dimming mode is programmed, it can not be changed
without another start-up. This means the IC needs to be shutdown by pulling the CTRL low for 2.5 ms and
restarts. See the Dimming Mode Detection and Soft Start (Figure 11) for a graphical explanation.
10
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Device Functional Modes (continued)
Insert battery
PWM signal
high
CTRL
low
PWM
mode
Startup
delay
FB ramp
Shutdown delay
200mV x duty cycle
FB
t
Insert battery
Enter ES mode
Enter ES mode
Timing window
Programming
code
Programming code
high
CTRL
low
ES detect time
ES
mode
ES detect delay
Shutdown
delay
IC
Shutdown
Programmed value
(if not programmed, 200mV default )
50mV
Startup delay
FB
FB ramp
FB ramp
Startup delay
50mV
Figure 11. Dimming Mode Detection and Soft Start PWM Brightness Dimming
7.4.2 PWM Brightness Dimming
When the CTRL pin is constantly high, the FB voltage is regulated to 200 mV typically. However, the CTRL pin
allows a PWM signal to reduce this regulation voltage; therefore, it achieves LED brightness dimming. The
relationship between the duty cycle and FB voltage is given by Equation 1.
VFB Duty u 200 mV
where
•
Duty = duty cycle of the PWM signal
200 mV = internal reference voltage
(1)
As shown in Figure 12, the IC chops up the internal 200-mV reference voltage at the duty cycle of the PWM
signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the
error amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for
brightness dimming, only the WLED dc current is modulated, which is often referred as analog dimming. This
eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and
duty cycle of PWM control. Unlike other scheme which filters the PWM signal for analog dimming, TPS61161-Q1
regulation voltage is independent of the PWM logic voltage level which often has large variations.
For optimum performance, use the PWM dimming frequency in the range of 5 kHz to 100 kHz. The requirement
of minimum dimming frequency comes from the EasyScale detection delay and detection time specification in the
dimming mode selection. Because the CTRL pin is logic only pin, adding external RC filter applied to the pin
does not work.
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Device Functional Modes (continued)
VBG
200 mV
CTRL
Error
Amplifier
COMP
FB
Figure 12. Block Diagram of Programmable FB Voltage Using PWM Signal
7.4.3 Digital 1 Wire Brightness Dimming
The CTRL pin features a simple digital interface to allow digital brightness control. The digital dimming can save
the processor power and battery life as it does not require a PWM signal all the time, and the processor can
enter idle mode if available.
The TPS61161-Q1 adopts the EasyScale protocol for the digital dimming, which can program the FB voltage to
any of the 32 steps with single command. The step increment increases with the voltage to produce pseudo
logarithmic curve for the brightness step. See the Table 2 for the FB pin voltage steps. The default step is full
scale when the device is first enabled (VFB = 200 mV). The programmed reference voltage is stored in an internal
register. A power reset clears the register value and reset it to default.
7.4.4 EasyScale: 1-Wire Digital Dimming
EasyScale is a simple but flexible one-pin interface to configure the FB voltage. The interface is based on a
master-slave structure, where the master is typically a microcontroller or application processor. Figure 13 and
Table 3 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte.
The device specific address byte is fixed to 72 hex. The data byte consists of five bits for information, two
address bits, and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The
Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale
compared with other on pin interfaces is that its bit detection is in a large extent independent from the bit
transmission rate. It can automatically detect bit rates from 1.7 kbit/s and up to 160 kbit/s.
12
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Table 2. Selectable FB Voltage
FB voltage
(mV)
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
5
0
0
0
0
1
2
8
0
0
0
1
0
3
11
0
0
0
1
1
4
14
0
0
1
0
0
5
17
0
0
1
0
1
6
20
0
0
1
1
0
7
23
0
0
1
1
1
8
26
0
1
0
0
0
9
29
0
1
0
0
1
10
32
0
1
0
1
0
11
35
0
1
0
1
1
12
38
0
1
1
0
0
13
44
0
1
1
0
1
14
50
0
1
1
1
0
15
56
0
1
1
1
1
16
62
1
0
0
0
0
17
68
1
0
0
0
1
18
74
1
0
0
1
0
19
80
1
0
0
1
1
20
86
1
0
1
0
0
21
92
1
0
1
0
1
22
98
1
0
1
1
0
23
104
1
0
1
1
1
24
116
1
1
0
0
0
25
128
1
1
0
0
1
26
140
1
1
0
1
0
27
152
1
1
0
1
1
28
164
1
1
1
0
0
29
176
1
1
1
0
1
30
188
1
1
1
1
0
31
200
1
1
1
1
1
DATA IN
DATABYTE
Device Address
Start
Start DA7 DA6 DA5 DA4 DA3 DA2 DA1
0
1
1
1
0
0
1
DA0 EOS Start RFA
0
A1
A0
D4
D3
D2
D1
D0
EOS
DATA OUT
ACK
Figure 13. EasyScale Protocol Overview
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Table 3. EasyScale Bit Description
BYTE
Device
Address
Byte
72 hex
Data byte
BIT
NUMBER
NAME
TRANSMISSION
DIRECTION
7
DA7
0 MSB device address
6
DA6
1
5
DA5
1
4
DA4
3
DA3
2
DA2
0
1
DA1
1
DESCRIPTION
1
IN
0
0
DA0
0 LSB device address
7 (MSB)
RFA
Request for acknowledge. If high, acknowledge is applied by device
6
A1
0 Address bit 1
5
A0
0 Address bit 0
4
D4
3
D3
2
D2
Data bit 2
1
D1
Data bit 1
0 (LSB)
D0
Data bit 0
Data bit 4
IN
ACK
Data bit 3
Acknowledge condition active 0, this condition will only be applied in case RFA bit is
set. Open-drain output, Line needs to be pulled high by the host with a pullup
resistor. This feature can only be used if the master has an open-drain output
stage. In case of a push pull output stage Acknowledge condition may not be
requested!
OUT
Easy Scale Timing, without acknowledge RFA = 0
t Start
DATA IN
t Start
Address Byte
DATA Byte
Static High
Static High
DA7
0
DA0
0
D0
1
RFA
0
TEOS
TEOS
Easy Scale Timing, with acknowledge RFA = 1
t Start
DATA IN
t Start
Address Byte
DATA Byte
Static High
Static High
DA7
0
DA0
0
TEOS
RFA
1
D0
1
Controller needs to
Pullup Data Line via a
resistor to detect ACKN
DATA OUT
tLow
Low Bit
(Logic 0)
t High
tLOW
t valACK
ACKN
t ACKN
Acknowledge
true, Data Line
pulled down by
device
Acknowledge
false, no pull
down
tHigh
High Bit
(Logic 1)
Figure 14. EasyScale™— Bit Coding
14
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All bits are transmitted MSB first and LSB last. Figure 14 shows the protocol without acknowledge request (Bit
RFA = 0), Figure 14 with acknowledge (Bit RFA = 1) request. Before both bytes, device address byte and data
byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least tstart (2 µs) before
the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition is
needed before the device address byte. The transmission of each byte is closed with an End of Stream condition
for at least tEOS (2 µs).
The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and
tHIGH. It can be simplified to:
High Bit: tHIGH > tLOW, but with tHIGH at least 2x tLOW, see Figure 14.
Low Bit: tHIGH < tLOW, but with tLOW at least 2x tHIGH, see Figure 14.
The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on
the relation between tHIGH and tLOW, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:
• Acknowledge is requested by a set RFA bit.
• The transmitted device address matches with the device address of the device.
• 16 bits is received correctly.
If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time tACKN, which is 512 µs
maximum then the Acknowledge condition is valid after an internal delay time tvalACK. This means that the internal
ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master
controller keeps the line low in this period. The master device can detect the acknowledge condition with its input
by releasing the CTRL pin after tvalACK and read back a logic 0. The CTRL pin can be used again after the
acknowledge condition ends.
The acknowledge condition may only be requested in case the master device has an open-drain output. For a
push-pull output stage, TI recommends using a series resistor in the CRTL line to limit the current to 500 µA for
such cases as:
• an accidentally requested acknowledge
• to protect the internal ACKN-MOSFET
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
In the application, TPS61161-Q1 drives 10 LEDs, the output current is set at 20mA, the circuit can support wide
range input voltage from 3 V to 18 V. By applying PWM signal on CTRL pin, the circuit can realize PWM
dimming control.
8.2 Typical Application
L1
22 mH
VI 3 V to 18 V
C1
1 mF
TPS61161–Q1
ON/OFF
DIMMING
CONTROL
VIN
SW
CTRL
FB
COMP GND
C3
220 nF
D1
38 V Max
C2
1 mF
Rset
10 W
L1: TDK VLCF5020T-220MR75-1
C1: Murata GRM188R61E105K
C2: Murata GRM21BR71H105K
D1: ONsemi MBR0540T1
20 mA
Figure 15. LED Drivers With 10 White LEDs Schematic
8.2.1 Design Requirements
Table 4 lists the input parameters for this design example.
Table 4. Design Parameters
PARAMETER
EXAMPLE VALUE
Brightness control
PWM Dimming
Input voltage
3 V to 18 V
Output current
20 mA
LED loads
10 LEDs
8.2.2 Detailed Design Procedure
8.2.2.1 Current Program
The FB voltage is regulated by a low 0.2-V reference voltage. The LED current is programmed externally using a
current-sense resistor in series with the LED string. The value of the RSET is calculated using Equation 2:
VFB
ILED
RSET
where
•
•
•
16
ILED = output current of LEDs
VFB = regulated voltage of FB
RSET = current sense resistor
(2)
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The output current tolerance depends on the FB accuracy and the current sensor resistor accuracy.
8.2.2.2 Maximum Output Current
The overcurrent limit in a boost converter limits the maximum input current and thus maximum input power for a
given input voltage. Maximum output power is less than maximum input power due to power conversion losses.
Therefore, the current limit setting, input voltage, output voltage and efficiency can all change maximum current
output. The current limit clamps the peak inductor current; therefore, the ripple must be subtracted to derive
maximum dc current. The ripple current is a function of switching frequency, inductor value and duty cycle. The
following equations take into account of all of the previous factors for maximum output current calculation.
1
IP
ª
§
1
1 ·º
«L u FS u ¨
¸»
© VOUT VF VIN VIN ¹ ¼»
¬«
where
•
•
•
•
•
•
IP = inductor peak to peak ripple
L = inductor value
VF = Schottky diode forward voltage
FS = switching frequency
VOUT = output voltage of the boost converter. It is equal to the sum of VFB and the voltage drop across LEDs.
(3)
IOUT _ MAX
I ·
§
VIN u ¨ ILIM P ¸ u K
2¹
©
VOUT
where
•
•
•
IOUT_MAX = maximum output current of the boost converter
ILIM = overcurrent limit
η = efficiency
(4)
For instance, when VIN is 3 V, 8 LEDs output equivalent to VOUT of 26 V, the inductor is 22 µH, the Schottky
forward voltage is 0.2 V; and then the maximum output current is 65 mA in typical condition. When VIN is 5 V, 10
LEDs output equivalent to VOUT of 32 V, the inductor is 22 µH, the Schottky forward voltage is 0.2 V; and then
the maximum output current is 85 mA in typical condition.
8.2.2.3 Inductor Selection
The selection of the inductor affects steady state operation as well as transient behavior and loop stability. These
factors make it the most important component in power regulator design. There are three important inductor
specifications, inductor value, dc resistance and saturation current. Considering inductor value alone is not
enough.
The inductor value determines the inductor ripple current. Choose an inductor that can handle the necessary
peak current without saturating, according to half of the peak-to-peak ripple current given by Equation 3, pause
the inductor dc current given by:
VOUT u IOUT
IIN _ DC
VIN u K
(5)
Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation
level, its inductance can decrease 20% to 35% from the 0-A value depending on how the inductor vendor defines
saturation current. Using an inductor with a smaller inductance value forces discontinuous PWM when the
inductor current ramps down to zero before the end of each switching cycle. This reduces the boost converter’s
maximum output current, causes large input voltage ripple and reduces efficiency. Large inductance value
provides much more output current and higher conversion efficiency. For these reasons, TI recommends a 10-µH
to 22-µH inductor value range. A 22-µH inductor optimized the efficiency for most application while maintaining
low inductor peak to peak ripple. Table 5 lists the recommended inductor for the TPS61161-Q1. When
recommending inductor value, the factory has considered –40% and 20% tolerance from its nominal value.
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TPS61161-Q1 has built-in slope compensation to avoid sub-harmonic oscillation associated with current mode
control. If the inductor value is lower than 10 µH, the slope compensation may not be adequate, and the loop can
be unstable. Therefore, customers must verify the inductor in their application if it is different from the
recommended values.
Table 5. Recommended Inductors for TPS61161-Q1
PART NUMBER
L
(µH)
DCR MAX
(Ω)
SATURATION CURRENT
(mA)
SIZE
(L × W × H mm)
VENDOR
Murata
LQH3NPN100NM0
10
0.3
750
3×3×1.5
VLCF5020T-220MR75-1
22
0.4
750
5×5×2
TDK
CDH3809/SLD
10
0.3
570
4×4×1
Sumida
A997AS-220M
22
0.4
510
4×4×1.8
TOKO
8.2.2.4 Schottky Diode Selection
The high switching frequency of the TPS61161-Q1 demands a high-speed rectification for optimum efficiency.
Ensure that the diode average and peak current rating exceeds the average output current and peak inductor
current. In addition, the diode’s reverse breakdown voltage must exceed the open LED protection voltage. The
ONSemi MBR0540 and the ZETEX ZHCS400 are recommended for TPS61161-Q1.
8.2.2.5 Compensation Capacitor Selection
The compensation capacitor C3 (see the block diagram), connected from COMP pin to GND, is used to stabilize
the feedback loop of the TPS61161-Q1. Use a 220-nF ceramic capacitor for C3.
8.2.2.6 Input and Output Capacitor Selection
The output capacitor is mainly selected to meet the requirements for the output ripple and loop stability. This
ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a
capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by
(VOUT VIN )IOUT
COUT
VOUT u FS u VRIPPLE
where
•
VRIPPLE = peak-to-peak output ripple.
(6)
The additional output ripple component caused by ESR is calculated using:
VRIPPLE _ ESR IOUT u RESR
(7)
Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or
electrolytic capacitors are used.
Take care when evaluating a ceramic capacitor’s derating under dc bias, aging, and ac signal. For example,
larger form factor capacitors (in 1206 size) have a resonant frequencies in the range of the switching frequency.
So the effective capacitance is significantly lower. The dc bias can also significantly reduce capacitance. Ceramic
capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore, leave the margin on the
voltage rating to ensure adequate capacitance at the required output voltage.
TI recommends the capacitor in the range of 1 µF to 4.7 µF for input side. The output requires a capacitor in the
range of 0.47 µF to 10 µF. The output capacitor affects the loop stability of the boost regulator. If the output
capacitor is below the range, the boost regulator can potentially become unstable. For example, if use the output
capacitor of 0.1 µF, a 470 nF compensation capacitor must be used for the loop stable.
The popular vendors for high value ceramic capacitors are:
TDK (http://www.component.tdk.com/components.php)
Murata (http://www.murata.com/cap/index.html)
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8.2.3 Application Curves
Figure 16. Input Voltage 12 V
Figure 17. Input Voltage 18 V
Figure 18. Input Voltage 4 V
9 Power Supply Recommendations
The TPS61161-Q1 device requires a single supply input voltage. This voltage can range from 3 V to 18 V and be
able to supply enough current for a given application.
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10 Layout
10.1 Layout Guidelines
As for all switching power supplies, especially those high frequency and high current ones, layout is an important
design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems.
To reduce switching losses, the SW pin rise and fall times are made as short as possible. To prevent radiation of
high frequency resonance problems, proper layout of the high frequency switching path is essential. Minimize the
length and area of all traces connected to the SW pin and always use a ground plane under the switching
regulator to minimize inter-plane coupling. The loop including the PWM switch, Schottky diode, and output
capacitor, contains high current rising and falling in nanosecond and should be kept as short as possible. The
input capacitor needs not only to be close to the VIN pin, but also to the GND pin to reduce the IC supply ripple.
Figure 19 shows a sample layout.
10.2 Layout Example
C1
Rset
Vin
LEDs Out
Vin
FB
L1
CTRL
COMP
CTRL
GND
SW
C3
C2
Minimize the
area of this
trace
GND
Place enough
VIAs around
thermal pad to
enhance thermal
performance
LEDs IN
Figure 19. TPS61161-Q1 Layout Example
10.3 Thermal Considerations
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This
restriction limits the power dissipation of the TPS61161-Q1. Calculate the maximum allowable dissipation,
PD(max), and keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is
determined using Equation 8:
125°C - TA
PD(max) =
RqJA
where
•
•
TA is the maximum ambient temperature for the application.
RθJA is the thermal resistance junction-to-ambient given in Thermal Information.
(8)
The TPS61161-Q1 comes in a thermally enhanced SON package. This package includes a thermal pad that
improves the thermal capabilities of the package. The RθJA of the SON package greatly depends on the PCB
layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using
thermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON PCB
Attachment application report (SLUA271).
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• How to Use Analog Dimming With the TPS6116x, SLVA471
• Design Tool for Analog Dimming Using a PWM Signal, SLVC336
• QFN/SON PCB Attachment, SLUA271
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
EasyScale, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS61161QDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PSJQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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