TPS75518KTTTG3



 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 D 5-A Low-Dropout Voltage Regulator D Available in 1.5-V, 1.8-V, 2.5-V, and 3.3-V D D D D D D D TO−220 (KC) PACKAGE (TOP VIEW) Fixed-Output and Adjustable Versions Open Drain Power-Good (PG) Status Output (Fixed Options Only) Dropout Voltage Typically 250 mV at 5 A (TPS75533) Low 125 µA Typical Quiescent Current Fast Transient Response 3% Tolerance Over Specified Conditions for Fixed-Output Versions Available in 5-Pin TO−220 and TO−263 Surface-Mount Packages Thermal Shutdown Protection EN IN GND OUTPUT FB/PG 1 2 3 4 5 Tab is GND TO−263 (KTT) PACKAGE (TOP VIEW) 1 2 3 4 5 EN IN GND OUTPUT FB/PG Tab is GND description The TPS755xx family of 5-A low dropout (LDO) regulators contains four fixed voltage option regulators with integrated power-good (PG) and an adjustable voltage option regulator. These devices are capable of supplying 5 A of output current with a dropout of 250 mV (TPS75533). Therefore, the device is capable of performing a 3.3-V to 2.5-V conversion. Quiescent current is 125 µA at full load and drops down to less than 1 µA when the device is disabled. The TPS755xx is designed to have fast transient response for large load current changes. TPS75533 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE TPS75515 400 VDO − Dropout Voltage − mV 350 IO = 5 A VO = 3.3 V 300 250 200 150 VO = 1.5 V Co = 100 µF 100 50 0 −50 −100 150 di + 1.25 A ms dt 5 −150 100 0 50 0 −40 −25 −10 5 20 35 50 65 80 95 110 125 0 20 40 TJ − Junction Temperature − °C 60 I O − Output Current − A ∆ VO − Change in Output Voltage − mV LOAD TRANSIENT RESPONSE 80 100 120 140 160 180 200 t − Time − µs Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001, Texas Instruments Incorporated 
 
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 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 description (continued) Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 250 mV at an output current of 5 A for the TPS75533) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 125 µA over the full range of output current). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled when EN is connected to a low-level voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = 25°C. The power-good terminal (PG) is an active low, open drain output, which can be used to implement a power-on reset or a low-battery indicator. The TPS755xx is offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.22 V to 5 V). Output voltage tolerance is specified as a maximum of 3% over line, load, and temperature ranges. The TPS755xx family is available in a 5-pin TO−220 (KC) and TO−263 (KTT) packages. AVAILABLE OPTIONS TJ −40°C −40 C to 125 125°C C OUTPUT VOLTAGE (TYP) TO−220 (KC) TO−263(KTT) 3.3 V TPS75533KC TPS75533KTT 2.5 V TPS75525KC TPS75525KTT 1.8 V TPS75518KC TPS75518KTT 1.5 V TPS75515KC TPS75515KTT Adjustable 1.22 V to 5 V TPS75501KC TPS75501KTT NOTE: The TPS75501 is programmable using an external resistor divider (see application information). The KTT package is available taped and reeled. Add an R suffix to the device type (e.g., TPS75501KTTR) to indicate tape and reel. VI 2 IN PG OUT 1 µF 5 PG 4 VO 1 EN + GND Co† 47 µF 3 † See application information section for capacitor selection details. Figure 1. Typical Application Configuration (For Fixed Output Options) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 functional block diagram—adjustable version VOUT VIN Current Sense UVLO SHUTDOWN ILIM R1 _ GND + FB EN UVLO R2 Thermal Shutdown VIN External to the Device Bandgap Reference Vref = 1.22 V functional block diagram—fixed version VOUT VIN UVLO Current Sense SHUTDOWN ILIM _ R1 + GND UVLO EN R2 Thermal Shutdown VIN Bandgap Reference Vref = 1.22 V PG Falling Edge Delay Terminal Functions (TPS755xx) TERMINAL NAME NO. I/O DESCRIPTION EN 1 I Enable input FB/PG 5 I Feedback input voltage for adjustable device/PG output for fixed options GND 3 IN 2 I Input voltage OUTPUT 4 O Regulated output voltage Regulator ground POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 TPS755xx PG timing diagram VIN1 VUVLO VUVLO t VOUT VIT +(see Note A) Threshold Voltage VIT − (see Note A) t PG Output t NOTE A: VIT −Trip voltage is typically 9% lower than the output voltage (91%VO). VIT− to VIT+ is the hysteresis voltage. detailed description The TPS755xx family includes four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, and 3.3 V), and an adjustable regulator, the TPS75501 (adjustable from 1.22 V to 5 V). The bandgap voltage is typically 1.22 V. pin functions enable (EN) The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in shutdown mode. When EN goes to logic low, the device will be enabled. power-good (PG) The PG terminal for the fixed voltage option devices is an open drain, active low output that indicates the status of VO (output of the LDO). When VO reaches approximately 91% of the regulated voltage, PG will go to a low impedance state. It will go to a high-impedance state when VO falls below approximately 89% (i.e. over load condition) of the regulated voltage. The open drain output of the PG terminal requires a pullup resistor. feedback (FB) FB is an input terminal used for the adjustable-output option and must be connected to the output terminal either directly, in order to generate the minimum output voltage of 1.22 V, or through an external feedback resistor divider for other output voltages. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and VO to filter noise is not recommended because it may cause the regulator to oscillate. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 detailed description (continued) input voltage (IN) The VIN terminal is an input to the regulator. output voltage (OUTPUT) The VOUTPUT terminal is an output to the regulator. absolute maximum ratings over operating junction temperature range (unless otherwise noted)Ĕ Input voltage range‡, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Maximum PG voltage (fixed options only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables Output voltage, VO (OUTPUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV ESD rating, CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE PACKAGE RθJC (°C/W) TO−220 2 RθJA (°C/W)§ 58.7¶ 2 38.7# § For both packages, the RθJA values were computed using JEDEC high K board (2S2P) with 1 ounce internal copper plane and ground plane. There was no air flow across the packages. ¶ RθJA was computed assuming a vertical, free standing TO-220 package with pins soldered to the board. There is no heatsink attached to the package. # RθJA was computed assuming a horizontally mounted TO-263 package with pins soldered to the board. There is no copper pad underneath the package. TO−263 recommended operating conditions Input voltage, VI|| Output voltage range, VO Output current, IO MIN MAX UNIT 2.8 5.5 V 1.22 5 V 0 5 A Operating virtual junction temperature, TJ −40 125 °C || To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 electrical characteristics over recommended operating junction temperature range (TJ = −40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 100 µF (unless otherwise noted) PARAMETER TEST CONDITIONS 1.22 V ≤ VO ≤ 5.5 V, Adjustable voltage TJ = 25°C TJ = 0 to 125°C 1.5 V Output TJ = 25°C, 2.8 V ≤ VI ≤ 5.5 V 2.8 V < VI < 5.5 V 1.8 V Output TJ = 25°C, 2.8 V ≤ VI ≤ 5.5 V 2.8 V < VI < 5.5 V 2.5 V Output TJ = 25°C, 3.5 V ≤ VI ≤ 5.5 V 3.5 V < VI < 5.5 V 3.3 V Output TJ = 25°C, 4.3 V ≤ VI ≤ 5.5 V 4.3 V < VI < 5.5 V Quiescent current (GND current) (see Notes 2 and 3) Output voltage line regulation (∆VO/VO) (see Note 3) 1.03 VO 0.98 VO 1.02 VO 1.746 V 1.854 2.5 2.425 2.575 3.399 125 200 VO + 1 V ≤ VI ≤ 5.5 V, TJ = 25°C VO + 1 V ≤ VI < 5.5 V 0.1 5.5 10 Power supply ripple rejection TPS75515 f = 100 Hz, VI = 2.8 V, TJ = 25°C, IO = 5 A Minimum input voltage for valid PG IO(PG) = 300 µA, V(PG) ≤ 0.8 V PG trip threshold voltage Fixed options only PG hysteresis voltage Fixed options only VO decreasing Measured at VO PG output low voltage Fixed options only PG leakage current Fixed options only µA POST OFFICE BOX 655303 ǒVImax * 2.8 VǓ 100 If VO > 2.5 V then VImin = VO + 1 V, VImax = 5.5 V: Line regulation (mV) + ǒ%ńVǓ V 10 µA 1 µA dB 0 V 93 0.5 O 0.15 O 1000 ǒVImax * ǒVO ) 1 VǓǓ 100 • DALLAS, TEXAS 75265 1000 A 0.1 89 IO(PG) = 1 mA V 14 60 NOTES: 1. The adjustable option operates with a 2% tolerance over TJ = 0 to 125 °C. 2. IO = 1 mA to 5 A 3. If VO ≤ 2.5 V then VImin = 2.8 V, VImax = 5.5 V: Line regulation (mV) + ǒ%ńVǓ %/V °C −1 VI = 2.8 V, V(PG) = 5 V %/V 150 EN = VI FB = 1.5 V µA A µVrms 35 TJ = 25°C TPS75501 V 0.04 Thermal shutdown junction temperature FB input current V 3.3 3.201 TJ = 25°C EN = VI, V 1.545 1.8 BW = 300 Hz to 50 kHz, TJ = 25°C, VI = 2.8 V VO = 0 V Standby current UNIT 1.5 1.455 0.35 TPS75515 Output current limit 6 MAX 0.97 VO Load regulation (see Note 2) Output noise voltage TYP VO 1.22 V ≤ VO ≤ 5.5 V 1.22 V ≤ VO ≤ 5.5 V, (see Note 1) Output voltage (see Note 2) MIN %VO %VO 0.4 V 1 µA 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 electrical characteristics over recommended operating junction temperature range (TJ = −40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 100 µF (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS Input current (EN) MIN EN = VI −1 EN = 0 V −1 High level EN input voltage TYP 0 µA 1 µA V 0.7 Dropout voltage, (3.3 V output) (see Note 4) Discharge transistor current UVLO VI UNIT 1 2 Low level EN input voltage VO MAX IO = 5 A, IO = 5 A, VI = 3.2 V, VI = 3.2 V VO = 1.5 V, TJ = 25°C, TJ = 25°C VI rising TJ = 25°C V 250 mV 500 10 2.2 25 mA 2.75 V UVLO hysteresis TJ = 25°C, VI falling 100 mV NOTE 4: IN voltage equals VO(typ) − 100 mV; TPS75515, TPS75518, and TPS75525 dropout voltage limited by input voltage range limitations (i.e., TPS75533 input voltage is set to 3.2 V for the purpose of this test). TYPICAL CHARACTERISTICS Table of Graphs FIGURE VO Output voltage vs Output current 2, 3 vs Junction temperature 4, 5 Ground current vs Junction temperature 6 Power supply ripple rejection vs Frequency 7 Output spectral noise density vs Frequency 8 zo Output impedance vs Frequency 9 vs Input voltage 10 VDO Dropout voltage VI Minimum required input voltage vs Junction temperature 11 vs Output voltage 12 Line transient response 13, 15 Load transient response VO 14, 16 Output voltage and enable voltage vs Time (start-up) 17 Equivalent series resistance vs Output current 19, 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 TYPICAL CHARACTERISTICS TPS75533 TPS75515 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 3.345 1.545 VI = 2.8 V TJ = 25°C VI = 4.3 V TJ = 25°C 1.530 VO − Output Voltage − V VO − Output Voltage − V 3.330 3.315 3.3 3.285 1.515 1.5 1.485 1.470 3.270 3.255 0 1 2 3 4 1.455 5 1 0 Figure 2 TPS75533 TPS75515 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 5 1.545 VI = 4.3 V VI = 2.8 V 3.33 1.530 VO − Output Voltage − V VO − Output Voltage − V 4 Figure 3 3.345 3.315 3.3 3.285 3.255 −40 −25 1.515 1.5 1.485 1.470 3.270 10 5 20 35 50 65 80 95 110 125 1.455 −40 −25 −10 5 20 35 Figure 4 Figure 5 POST OFFICE BOX 655303 50 65 80 95 110 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C 8 3 2 IO − Output Current − A IO − Output Current − A • DALLAS, TEXAS 75265 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 TYPICAL CHARACTERISTICS TPS755xx TPS75733 GROUND CURRENT vs JUNCTION TEMPERATURE POWER SUPPLY RIPPLE REJECTION vs FREQUENCY 90 150 PSRR − Power Supply Ripple Rejection − dB Ground Current − µ A VI = 5 V IO = 5 A 125 100 75 −40 −25 −10 5 20 35 50 65 80 VI = 4.3 V Co = 100 µF TJ = 25°C 80 70 IO = 1 mA 60 50 40 30 IO = 5 A 20 10 0 10 95 110 125 100 1k TJ − Junction Temperature − °C Figure 6 TPS75533 TPS75533 OUTPUT IMPEDANCE vs FREQUENCY IO = 5 A 1.5 IO = 1 mA 1 0.5 10 VI = 4.3 V Co = 100 µF TJ = 25°C 1 IO = 1 mA 0.1 IO = 5 A 0.01 100 1k f − Frequency − Hz 10M 100 VI = 4.3 V VO = 3.3 V Co = 100 µF TJ = 25°C 2 1M Figure 7 z o − Output Impedance − Ω Output Spectral Noise Density − µ V/ Hz 100k OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 2.5 0 10 10k f − Frequency − Hz 10k 100k 0.001 10 100 1k 10k 100k f − Frequency − Hz 1M 10M Figure 9 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 TYPICAL CHARACTERISTICS TPS75501 TPS75533 DROPOUT VOLTAGE vs INPUT VOLTAGE DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 450 IO = 5 A VO = 3.3 V 350 TJ = 125°C 350 VDO − Dropout Voltage − mV VDO − Dropout Voltage − mV 400 400 IO = 5 A 300 TJ = 25°C 250 TJ = −40°C 200 150 300 250 200 150 100 100 50 50 0 2.5 3 3.5 4 VI − Input Voltage − V 4.5 0 −40 −25 −10 5 5 MINIMUM REQUIRED INPUT VOLTAGE vs OUTPUT VOLTAGE 65 80 95 110 125 TPS75515 ∆ VO − Change in Output Voltage − mV IO = 5 A TJ = 125°C TJ = 25°C TJ = −40°C VO = 1.5 V IO = 5 A Co = 100 µF 50 0 −50 −100 3 VI − Input Voltage − V VI− Minimum Required Input Voltage − V 50 LINE TRANSIENT RESPONSE 4 2.8 1.75 2 3 2.25 2.5 2.75 VO − Output Voltage − V 3.25 3.5 3.8 2.8 0 50 100 150 200 250 300 350 400 450 500 t − Time − µs Figure 13 Figure 12 10 35 Figure 11 Figure 10 2 1.5 20 TJ − Junction Temperature − °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 TPS75533 LINE TRANSIENT RESPONSE VO = 1.5 V Co = 100 µF 100 50 0 −50 −100 di + 1.25 A ms dt 5 −150 0 0 20 40 60 100 VO = 3.3 V IO = 5 A Co = 100 µF 50 0 −50 −100 5.3 4.3 80 100 120 140 160 180 200 t − Time − µs 0 VI − Input Voltage − V 150 ∆ VO − Change in Output Voltage − mV TPS75515 LOAD TRANSIENT RESPONSE I O − Output Current − A ∆ VO − Change in Output Voltage − mV TYPICAL CHARACTERISTICS 50 100 150 200 250 300 350 400 450 500 t − Time − µs Figure 15 Figure 14 TPS75533 OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) TPS75533 VO − Output Voltage − V 200 100 0 di + 1.25 A ms dt −100 5 0 0 20 40 60 80 100 120 140 160 180 200 t − Time − µs Enable Voltage − V VO =3 .3 V Co = 100 µF I O − Output Current − A ∆ VO− Change in Output Voltage − mV LOAD TRANSIENT RESPONSE VI = 4.3 V IO = 10 mA TJ = 25°C 3.3 0 4.3 0 0 0.2 Figure 16 0.4 0.6 0.8 t − Time (Start-Up) − ms 1 Figure 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 TYPICAL CHARACTERISTICS To Load IN VI OUT + EN RL Co GND ESR Figure 18. Test Circuit for Typical Regions of Stability (Figures 19 and 20) (Fixed Output Options) TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT 10 Co = 680 µF TJ = 25°C ESR − Equivalent Series Resistance −Ω ESR − Equivalent Series Resistance −Ω 10 1 Region of Stability 0.1 Co = 47 µF TJ = 25°C 1 Region of Stability 0.2 Region of Instability 0.015 Region of Instability 0.01 0 1 2 0.01 3 4 5 0 IO − Output Current − A 1 2 3 4 5 IO − Output Current − A Figure 19 Figure 20 † Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 THERMAL INFORMATION The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJmax) above which normal operation is not assured. A system designer must design the operating environment so that the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJmax). The two main environmental variables that a designer can use to improve thermal performance are air flow and external heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment for a linear regulator that is operating at a specific power level. In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as: ǒ P max + V *V D I(avg) O(avg) Ǔ I O(avg) ) V I(avg) xI (1) (Q) Where: VI(avg) is the average input voltage. VO(avg) is the average output voltage. IO(avg) is the average output current. I(Q) is the quiescent current. For most TI LDO regulators, the quiescent current is insignificant compared to the average output current; therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding the ambient temperature (TA) and the increase in temperature due to the regulator’s power dissipation. The temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal resistances between the junction and the case (RθJC), the case to heatsink (RθCS), and the heatsink to ambient (RθSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the device, the more surface area available for power dissipation and the lower the object’s thermal resistance. Figure 21 illustrates these thermal resistances for (a) a TO−220 package attached to a heatsink, and (b) a TO−263 package mounted on a JEDEC High-K board. C B A TJ RθJC A B A B TC RθCS C RθSA TA TO−263 Package (b) C TO−220 Package (a) Figure 21. Thermal Resistances POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 THERMAL INFORMATION Equation 2 summarizes the computation: T J ǒ Ǔ ) R ) R + T ) P Dmax x R A θJC θCS θSA (2) The RθJC is specific to each regulator as determined by its package, lead frame, and die size provided in the regulator’s datasheet. The RθSA is a function of the type and size of heatsink. For example, black body radiator type heatsinks, like the one attached to the TO−220 package in Figure 21(a), can have RθCS values ranging from 5°C/W for very large heatsinks to 50°C/W for very small heatsinks. The RθCS is a function of how the package is attached to the heatsink. For example, if a thermal compound is used to attach a heatsink to a TO−220 package, RθCS of 1°C/W is reasonable. Even if no external black body radiator type heatsink is attached to the package, the board on which the regulator is mounted will provide some heatsinking through the pin solder connections. Some packages, like the TO−263 and TI’s TSSOP PowerPAD packages, use a copper plane underneath the package or the circuit board’s ground plane for additional heatsinking to improve their thermal performance. Computer aided thermal modeling can be used to compute very accurate approximations of an integrated circuit’s thermal performance in different operating environments (e.g., different types of circuit boards, different types and sizes of heatsinks, and different air flows, etc.). Using these models, the three thermal resistances can be combined into one thermal resistance between junction and ambient (RθJA). This RθJA is valid only for the specific operating environment used in the computer model. Equation 2 simplifies into equation 3: T J + T ) P Dmax x R θJA A (3) Rearranging equation 3 gives equation 4: R θJA + T J–T A (4) P Dmax Using equation 3 and the computer model generated curves shown in Figures 22 and 25, a designer can quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power dissipation, and operating environment. PowerPAD is a trademark of Texas Instruments. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 THERMAL INFORMATION TO−220 power dissipation The TO−220 package provides an effective means of managing power dissipation in through-hole applications. The TO−220 package dimensions are provided in the Mechanical Data section at the end of the data sheet. A heatsink can be used with the TO−220 package to effectively lower the junction-to-ambient thermal resistance. To illustrate, the TPS75525 in a TO−220 package was chosen. For this example, the average input voltage is 3.3 V, the output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55°C, the air flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is: P Dmax + (3.3 – 2.5) V x 3 A + 2.4 W (5) Substituting TJmax for TJ into equation 4 gives equation 6: R max + (125 – 55)°Cń2.4 W + 29°CńW θJA (6) From Figure 22, RθJA vs Heatsink Thermal Resistance, a heatsink with RθSA = 22°C/W is required to dissipate 2.4 W. The model operating environment used in the computer model to construct Figure 22 consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. Since the package pins were soldered to the board, 450 mm2 of the board was modeled as a heatsink. Figure 23 shows the side view of the operating environment used in the computer model. THERMAL RESISTANCE vs HEATSINK THERMAL RESISTANCE 65 Rθ JA − Thermal Resistance − ° C/W Natural Convection 55 Air Flow = 150 LFM 45 Air Flow = 250 LFM Air Flow = 500 LFM 35 25 15 No Heatsink 5 25 20 15 10 5 RθSA − Heatsink Thermal Resistance − °C/W 0 Figure 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 THERMAL INFORMATION TO−220 power dissipation (continued) 0.21 mm 0.21 mm 1 oz. Copper Power Plane 1 oz. Copper Ground Plane Figure 23 From the data in Figure 22 and rearranging equation 4, the maximum power dissipation for a different heatsink RθSA and a specific ambient temperature can be computed (see Figure 24). POWER DISSIPATION vs HEATSINK THERMAL RESISTANCE 10 PD − Power Dissipation Limit − W TA = 55°C Air Flow = 500 LFM Air Flow = 250 LFM Air Flow = 150 LFM Natural Convection No Heatsink 1 20 10 RθSA − Heatsink Thermal Resistance − °C/W Figure 24 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 THERMAL INFORMATION TO−263 power dissipation The TO−263 package provides an effective means of managing power dissipation in surface mount applications. The TO−263 package dimensions are provided in the Mechanical Data section at the end of the data sheet. The addition of a copper plane directly underneath the TO−263 package enhances the thermal performance of the package. To illustrate, the TPS75525 in a TO−263 package was chosen. For this example, the average input voltage is 3.3 V, the output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55°C, the air flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is: P Dmax + (3.3 – 2.5) V x 3 A + 2.4 W (7) Substituting TJmax for TJ into equation 4 gives equation 8: R max + (125 – 55)°Cń2.4 W + 29°CńW θJA (8) From Figure 25, RθJA vs Copper Heatsink Area, the ground plane needs to be 2 cm2 for the part to dissipate 2.4 W. The model operating environment used in the computer model to construct Figure 25 consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The package is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane. Figure 26 shows the side view of the operating environment used in the computer model. THERMAL RESISTANCE vs COPPER HEATSINK AREA 40 Rθ JA − Thermal Resistance − ° C/W No Air Flow 35 150 LFM 30 250 LFM 25 20 15 0 0.01 0.1 1 10 Copper Heatsink Area − cm2 100 Figure 25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 THERMAL INFORMATION TO−263 power dissipation (continued) 2 oz. Copper Solder Pad with 25 Thermal Vias 1 oz. Copper Power Plane 1 oz. Copper Ground Plane Thermal Vias, 0.3 mm Diameter, 1.5 mm Pitch Figure 26 From the data in Figure 25 and rearranging equation 4, the maximum power dissipation for a different ground plane area and a specific ambient temperature can be computed (see Figure 27). MAXIMUM POWER DISSIPATION vs COPPER HEATSINK AREA PD − Maximum Power Dissipation − W 5 TA = 55°C 250 LFM 4 150 LFM 3 No Air Flow 2 1 0 0.01 0.1 1 10 Copper Heatsink Area − cm2 Figure 27 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 APPLICATION INFORMATION programming the TPS75501 adjustable LDO regulator The output voltage of the TPS75501 adjustable regulator is programmed using an external resistor divider as shown in Figure 28. The output voltage is calculated using: V O +V ǒ1 ) R1 Ǔ R2 ref (9) Where: Vref = 1.224 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 40 µA and then calculate R1 using: R1 + ǒ V V Ǔ O *1 ref R2 (10) TPS75501 VI OUTPUT VOLTAGE PROGRAMMING GUIDE IN 1 µF OUTPUT VOLTAGE ≥2V EN ≤ 0.7 V OUT VO R1 Co FB GND R1 R2 UNIT 31.6 30.1 kΩ 3.3 V 51 30.1 kΩ 3.6 V 58.3 30.1 kΩ 2.5 V R2 Figure 28. TPS75501 Adjustable LDO Regulator Programming regulator protection The TPS755xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS755xx also features internal current limiting and thermal protection. During normal operation, the TPS755xx limits output current to approximately 10 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 


 
 
  
 


  

 
 SLVS293D − NOVEMBER 2000 − REVISED MAY 2002 APPLICATION INFORMATION input capacitor For a typical application, a ceramic input bypass capacitor (0.22 µF−1 µF) is recommended to ensure device stability. This capacitor should be as close as possible to the input pin. Due to the impedance of the input supply, large transient currents will cause the input voltage to droop. If this droop causes the input voltage to drop below the UVLO threshold, the device will turn off. Therefore, it is recommended that a larger capacitor be placed in parallel with the ceramic bypass capacitor at the regulator’s input. The size of this capacitor depends on the output current, response time of the main power supply, and the main power supply’s distance to the regulator. At a minimum, the capacitor should be sized to ensure that the input voltage does not drop below the minimum UVLO threshold voltage during normal operating conditions. output capacitor As with most LDO regulators, the TPS755xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 47 µF with an ESR (equivalent series resistance) of at least 200 mΩ. As shown in Figure 29, most capacitor and ESR combinations with a product of 47e−6 x 0.2 = 9.4e−6 or larger will be stable, provided the capacitor value is at least 47 µF. Solid tantalum electrolytic and aluminum electrolytic capacitors are all suitable, provided they meet the requirements described in this section. Larger capacitors provide a wider range of stability and better load transient response. This information along with the ESR graphs, Figures 19, 20, and 29, is included to assist in selection of suitable capacitance for the user’s application. When necessary to achieve low height requirements along with high output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet these guidelines. OUTPUT CAPACITANCE vs EQUIVALENT SERIES RESISTANCE 1000 Output Capacitance − µ F Region of Stability 100 ESR min x Co = Constant 47 Region x ofCInstability Y = ESRmin o 10 0.01 0.1 ESR − Equivalent Series Resistance − Ω Figure 29 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.2 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS75501KC ACTIVE TO-220 KC 5 50 RoHS & Green Call TI | SN N / A for Pkg Type -40 to 125 75501 Samples TPS75501KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS & Green Call TI | SN Level-2-260C-1 YEAR -40 to 125 75501 Samples TPS75501KTTRG3 ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 75501 Samples TPS75515KC ACTIVE TO-220 KC 5 50 RoHS & Green Call TI | SN N / A for Pkg Type -40 to 125 75515 Samples TPS75515KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS & Green Call TI | SN Level-2-260C-1 YEAR -40 to 125 75515 Samples TPS75518KC ACTIVE TO-220 KC 5 50 RoHS & Green Call TI | SN N / A for Pkg Type -40 to 125 75518 Samples TPS75518KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS & Green Call TI | SN Level-2-260C-1 YEAR -40 to 125 75518 Samples TPS75525KC ACTIVE TO-220 KC 5 50 RoHS & Green Call TI | SN N / A for Pkg Type -40 to 125 75525 Samples TPS75525KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS & Green Call TI | SN Level-2-260C-1 YEAR -40 to 125 75525 Samples TPS75533KC ACTIVE TO-220 KC 5 50 RoHS & Green Call TI | SN N / A for Pkg Type -40 to 125 75533 Samples TPS75533KCG3 ACTIVE TO-220 KC 5 50 RoHS & Green SN N / A for Pkg Type -40 to 125 75533 Samples TPS75533KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS & Green Call TI | SN Level-2-260C-1 YEAR -40 to 125 75533 Samples TPS75533KTTRG3 ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 75533 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of