TPS7A11
TPS7A11
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER
2020
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
www.ti.com
TPS7A11 500-mA, Low VIN, Low VOUT, Ultra-Low Dropout Regulator
1 Features
3 Description
•
•
The TPS7A11 is an ultra-small, low quiescent current,
low-dropout regulator (LDO). This device can source
500 mA with an outstanding ac performance (load and
line transient responses). This device has an input
range of 0.75 V to 3.3 V, and an output range of 0.5 V
to 3.0 V with a very high accuracy of 1.5% over load,
line, and temperature. This performance is ideal for
supplying power to the lower core voltages of modern
microcontrollers (MCUs) and analog sensors.
•
•
•
•
•
•
•
Ultra-low input voltage range: 0.75 V to 3.3 V
Ultra-low dropout for minimum power loss:
– 140 mV (maximum) at 500-mA DRV package
– 110 mV (maximum) at 500-mA YKA package
Low quiescent current:
– VIN IQ = 1.6 µA (typical)
– VBIAS IQ = 6 µA (typical)
1.5% accuracy over load, line, and temperature
High PSRR: 64 dB at 1 kHz
Available in fixed-output voltages:
– 0.5 V to 3.0 V (in 50-mV steps)
VBIAS range: 1.7 V to 5.5 V
Packages:
– 2.0-mm × 2.0-mm WSON (6)
– 0.74-mm × 1.09-mm DSBGA (5)
Active output discharge
2 Applications
•
•
•
•
•
•
Smart watches, fitness trackers
Wireless headphones and earbuds
Camera modules
Smart phones and tablets
Portable medical devices
Solid state drives (SSDs)
The TPS7A11 is equipped with an active pulldown
circuit to quickly discharge the output when disabled,
and provides a known start-up state.
The TPS7A11 is available in a small 2.00-mm × 2.00mm WSON, 6-pin (DRV) package and an ultra-small
0.74-mm × 1.09-mm, 5-pin DSBGA (YKA) package
that makes the device suitable for space-constrained
applications.
VBATTERY
CBIAS
OUT
Standalone
DC/DC Converter
Or PMU
Device Information (1)
BIAS
IN
IN
VOUT
OUT
CIN
PART NUMBER
COUT
PACKAGE
TPS7A11
EN
GND
The primary power path is through the IN pin and can
be connected to a power supply as low as 140 mV
above the output voltage. This device supports very
low input voltages with the use of an additional VBIAS
rail that is used to power the internal circuitry of the
LDO. The IN and BIAS pins consume very low
quiescent current of 1.6 µA and 6 µA, respectively.
The low IQ and ultra-low dropout features help to
increase the efficiency of the solution in powersensitive applications. For example, the supply
voltage to the IN pin can be an output of a highefficiency, DC/DC step-down regulator and the BIAS
pin supply voltage can be a rechargeable battery.
GND
TPS7A11
(1)
BODY SIZE (NOM)
WSON (6)
2.00 mm × 2.00 mm
DSBGA (5)
0.74 mm × 1.09 mm
(0.35-mm pitch)
For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
140
TJ
40 qC
0 qC
25 qC
Input Voltage Dropout (mV)
120
100
85 qC
105 qC
125 qC
80
60
40
20
0
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
500
Dropout vs IOUT and Temperature, YKA Package
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2020 Texas Instruments
Submit
Document
Feedback
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Product Folder Links: TPS7A11
1
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics................................................ 8
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................17
8 Application and Implementation.................................. 18
8.1 Application Information............................................. 18
8.2 Typical Application.................................................... 22
9 Power Supply Recommendations................................23
10 Layout...........................................................................24
10.1 Layout Guidelines................................................... 24
10.2 Layout Examples.................................................... 24
11 Device and Documentation Support..........................25
11.1 Device Support........................................................25
11.2 Documentation Support.......................................... 25
11.3 Receiving Notification of Documentation Updates.. 25
11.4 Support Resources................................................. 25
11.5 Trademarks............................................................. 26
11.6 Electrostatic Discharge Caution.............................. 26
11.7 Glossary.................................................................. 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2018) to Revision B (December 2020)
Page
• Updated the numbering format for tables and figures throughout the document............................................... 1
• Updated sequencing requirement to clarify differences between "A" and "non-A" versions.............................15
• Changed Device Nomenclature table............................................................................................................... 25
Changes from Revision * (September 2018) to Revision A (December 2018)
Page
• Changed YKA (DSBGA) package status from Preview to Production Data ...................................................... 1
• Added Evaluation Module subsection ..............................................................................................................25
2
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
5 Pin Configuration and Functions
OUT
NC
1
6
2 Thermal 5
IN
GND
Pad
EN
3
4
BIAS
Not to scale
TI recommends connecting the SON (DRV) package thermal pad to ground.
NC – No internal connection.
Figure 5-1. DRV Package, 6-Pin SON With Exposed Thermal Pad, Top View
Table 5-1. Pin Functions: DRV
PIN
NAME
NO.
I/O
DESCRIPTION
IN
6
Input
Input pin. A capacitor is required from IN to ground for stability. For best transient response, use
the nominal recommended value or larger ceramic capacitor from IN to ground. Follow the
recommended capacitor value as listed in the Recommended Operating Conditions table. Place
the input capacitor as close to the input pin of the device as possible.
OUT
1
Output
Regulated output pin. A capacitor is required from OUT to ground for stability. For best transient
response, use the nominal recommended value or larger ceramic capacitor from OUT to ground.
Follow the recommended capacitor value as listed in the Recommended Operating Conditions
table. Place the output capacitor as close to the output pin of the device as possible.
GND
5
—
BIAS
4
Input
BIAS pin. This pin enables the use of low-input voltage, low-output voltage (LILO) conditions. For
best performance, use the nominal recommended value or larger ceramic capacitor from BIAS to
ground. Follow the recommended capacitor value as listed in the Recommended Operating
Conditions table. Place the bias capacitor as close to the bias pin of the device as possible.
EN
3
Input
Enable pin. Driving this pin to logic high enables the device. Driving this pin to logic low disables
the device. If enable functionality is not required, this pin must be connected to IN or BIAS;
however, connecting EN to IN is only acceptable if the IN pin voltage is greater than 0.9 V.
NC
2
—
This pin is not internally connected. Connect to ground for better thermal dissipation or leave
floating.
—
Connect the thermal pad to a large-area ground plane.
Thermal pad
Ground pin. This pin must be connected to ground.
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
3
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
IN
A1
GND
BIAS
A3
OUT
C3
EN
B2
C1
Not to scale
Figure 5-2. YKA Package, 5-Pin DSBGA, Top View
Table 5-2. Pin Functions: YKA
PIN
NO.
A1
4
NAME
IN
A3
OUT
B2
GND
I/O
Input
DESCRIPTION
Input pin. A capacitor is required from IN to ground for stability. For best transient response, use the
nominal recommended value or larger ceramic capacitor from IN to ground. Follow the recommended
capacitor value as listed in the Recommended Operating Conditions table. Place the input capacitor as
close to the input pin of the device as possible.
Regulated output pin. A capacitor is required from OUT to ground for stability. For best transient
response, use the nominal recommended value or larger ceramic capacitor from OUT to ground. Follow
Output
the recommended capacitor value as listed in the Recommended Operating Conditions table. Place the
output capacitor as close to the output pin of the device as possible.
—
Ground pin. This pin must be connected to ground.
C1
BIAS
Input
BIAS pin. This pin enables the use of low-input voltage, low-output voltage (LILO) conditions. For best
performance, use the nominal recommended value or larger ceramic capacitor from BIAS to ground.
Follow the recommended capacitor value as listed in the Recommended Operating Conditions table.
Place the bias capacitor as close to the bias pin of the device as possible.
C3
EN
Input
Enable pin. Driving this pin to logic high enables the device. Driving this pin to logic low disables the
device. If enable functionality is not required, this pin must be connected to IN or BIAS; however,
connecting EN to IN is only acceptable if the IN pin voltage is greater than 0.9 V.
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted.(1)
MIN
Voltage
Current
(1)
(2)
Input, VIN
–0.3
3.6
Enable, VEN
–0.3
6.0
Bias, VBIAS
–0.3
6.0
Output, VOUT
–0.3
VIN + 0.3 (2)
Maximum output
Temperature
MAX
UNIT
V
Internally limited
A
Operating junction, TJ
–40
150
°C
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The absolute maximum rating is 3.6 V or (VIN + 0.3 V), whichever is less.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).
MIN
NOM
MAX
UNIT
VIN
Input voltage
0.75
3.3
VBIAS
Bias voltage
1.7
5.5
V
VOUT
Output voltage
0.5
3.0
V
IOUT
Peak output current
0
500
mA
CIN
Input capacitor
2.2
V
µF
CBIAS
Bias capacitor
COUT (1)
Output capacitor
2.2
22
µF
TJ
Operating junction temperature
–40
125
℃
(1)
0.1
µF
Maximum ESR must be lower than 250 mΩ
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
5
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
6.4 Thermal Information
TPS7A11
THERMAL
METRIC(1)
DRV (WSON)
YKA (DSBGA)
6 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
77.3
169.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
91.6
1.1
°C/W
RθJB
Junction-to-board thermal resistance
41.1
55.4
°C/W
ψJT
Junction-to-top characterization parameter
4.3
1.7
°C/W
ψJB
Junction-to-board characterization parameter
41.0
55.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
18.6
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = 1.0 V, CIN = 2.2 μF, COUT
= 2.2 μF, and CBIAS = 0.1 μF ( unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
Nominal accuracy
TEST CONDITIONS
TJ = 25°C
TYP
0.5
–20°C ≤ TJ ≤ 85, DRV package
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V,
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 500 mA
-1.25
1.25
–40°C ≤ TJ ≤ 85, YKA package
V
+ 0.5 V ≤ VIN ≤ 3.3 V,
Accuracy over temperature OUT(NOM)
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 500 mA
-1.25
1.25
–40°C ≤ TJ ≤ 125,
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V,
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 500 mA
-1.5
1.5
ΔVOUT / ΔVIN
VIN line regulation
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V
VBIAS line regulation
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V
ΔVOUT / ΔIOUT
Load regulation
0.1 mA ≤ IOUT ≤ 500 mA
TJ = 25°C, IOUT = 0 mA
Bias pin current
ISHDN(IN)
ICL
6
VBIAS shutdown current
VIN shutdown current
Output current limit
%/V
6
%/A
8
–40°C < TJ < 85°C, IOUT = 0 mA
11
IOUT = 0 mA
14
µA
60
1.6
2.1
–40°C < TJ < 85°C, IOUT = 0 mA
2.3
IOUT = 0 mA
2.6
µA
11
–40°C < TJ < 85°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
400
–40°C < TJ < 125°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
1200
–40°C < TJ < 85°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
1
–40°C < TJ < 125°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
3
nA
µA
VOUT = 0.9 × VOUT(NOM), YKA Package
625
920
1175
VOUT = 0.9 × VOUT(NOM), DRV Package
700
990
1250
Submit Document Feedback
%
%/V
IOUT = 500 mA
ISHDN(BIAS)
%
0.03
IOUT = 500 mA
Input pin current(1)
UNIT
0.001
0.2
3
TJ = 25°C, IOUT = 0 mA
IQ(IN)
MAX
-0.5
ΔVOUT / ΔVBIAS
IQ(BIAS)
MIN
mA
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
6.5 Electrical Characteristics (continued)
over TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = 1.0 V, CIN = 2.2 μF, COUT
= 2.2 μF, and CBIAS = 0.1 μF ( unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
ISC
TEST CONDITIONS
Short circuit current limit
VDO(IN)
VDO(BIAS)
VIN dropout
voltage(2)
VBIAS dropout voltage(2)
MIN
VOUT = 0 V
VBIAS PSRR
Vn
Output voltage noise
VUVLO(BIAS)
Bias supply UVLO
VUVLO_HYST(BIAS)
Bias supply hysteresis
VUVLO(IN)
Input supply UVLO
VUVLO_HYST(IN)
Input supply hysteresis
tSTR
Start-up time(3)
VHI(EN)
EN pin logic high voltage
VLO(EN)
EN pin logic low voltage
UNIT
mA
VIN = VOUT(NOM) – 0.1 V, IOUT = 500 mA,
YKA package
70
110
VIN = VOUT(NOM) – 0.1 V, IOUT = 500 mA,
DRV package
90
140
IOUT = 500 mA
0.85
1.2
IOUT = 250 mA
0.75
1.0
mV
V
64
f = 100 kHz,
VIN power-supply rejection VOUT = 1.0 V, IOUT = 50 mA
ratio
f = 1 MHz,
VOUT = 1.0 V, IOUT = 50 mA
VBIAS power-supply
rejection ratio
MAX
300
f = 1 kHz,
VOUT = 1.0 V, IOUT = 50 mA
VIN PSRR
TYP
37
dB
31
f = 1.5 MHz,
VOUT = 1.0 V, IOUT = 50 mA
35
f = 1 kHz,
VOUT = 1.0 V, IOUT = 500 mA
56
f = 100 kHz,
VOUT = 1.0 V, IOUT = 500 mA
43
f = 1 MHz,
VOUT = 1.0 V, IOUT = 500 mA
33
Bandwidth = 10 Hz to 100 kHz,
VOUT = 1.0 V, IOUT = 50 mA
dB
93.9
µVRMS
VBIAS rising
1.46
1.54
1.63
VBIAS falling
1.35
1.44
1.55
VBIAS hysteresis
80
mV
VIN rising
645
675
710
VIN falling
565
600
640
VIN hysteresis
75
525
V
mV
mV
1200
µs
0.4
V
0.9
V
IEN
EN pin current
EN = 5.5 V
10
nA
RPULLDOWN
Pulldown resistor
VBIAS = 3.3 V, P version only
120
Ω
TSD
Thermal shutdown
temperature
Shutdown, temperature rising
160
Reset, temperature falling
145
(1)
(2)
(3)
°C
This is the current flowing from VIN to GND.
Dropout is not measured for VOUT < 1.0 V.
Startup time = time from EN assertion to 0.95 × VOUT(NOM).
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
7
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
6.6 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
0.4
0.4
Change in Output Voltage ( )
0.3
0.2
85 qC
105 qC
125 qC
0.1
0
-0.1
-0.2
TJ
40 qC
0 qC
25 qC
0.3
Change in Output Voltage ( )
TJ
40 qC
0 qC
25 qC
-0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
-0.4
1.4
500
1.6
1.8
DRV package
2.2 2.4 2.6
Input Voltage (V)
2.8
3
3.2
3.4
Figure 6-2. Output Accuracy vs VIN and Temperature
140
0.4
0.2
85 qC
105 qC
125 qC
0.1
0
-0.1
-0.2
TJ
40qC
0qC
25qC
120
Input Votage Dropout (mV)
TJ
40 qC
0 qC
25 qC
0.3
Change in Output Voltage ( )
2
YKA package
Figure 6-1. Output Accuracy vs IOUT and Temperature
100
85qC
105qC
125qC
80
60
40
20
-0.3
-0.4
0
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
500
0
50
100
YKA package
150
200 250 300 350
Output Current (mA)
400
450
500
DRV package
Figure 6-3. Output Accuracy vs IOUT and Temperature
Figure 6-4. VIN Dropout vs IOUT and Temperature
140
0.25
TJ
40 qC
0 qC
25 qC
100
TJ
40 qC
0 qC
25 qC
0.2
85 qC
105 qC
125 qC
Change in Output Voltage ( )
120
Input Voltage Dropout (mV)
85 qC
105 qC
125 qC
80
60
40
20
0.15
85 qC
105 qC
125 qC
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
0
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
500
2
2.5
3
3.5
4
Bias Voltage (V)
4.5
5
5.5
YKA package
Figure 6-5. VIN Dropout vs IOUT and Temperature
8
Figure 6-6. Output Accuracy vs VBIAS and Temperature
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
1100
16
TJ
40qC
0qC
25qC
900
85qC
105qC
125qC
800
700
600
500
TJ
25qC
85qC
40qC
0qC
14
Bias Pin Current (PA)
Bias Voltage Dropout (mV)
1000
105qC
125qC
12
10
8
6
4
2
400
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
0
1.5
500
2
2.5
3
3.5
4
Bias Voltage (V)
4.5
5
5.5
IOUT = 0 mA
65
60
55
50
45
40
35
30
25
20
15
10
5
0
1.5
Figure 6-8. IQ(BIAS) vs VBIAS and Temperature
3
TJ
25qC
85qC
40qC
0qC
T
40 qC
0 qC
25 qC
2.8
105qC
125qC
2.6
Input Pin Current (PA)
Bias Pin Current (PA)
Figure 6-7. VBIAS Dropout vs IOUT and Temperature
2.4
2.2
2
1.8
1.6
1.4
1.2
2
2.5
3
3.5
4
Bias Voltage (V)
4.5
5
1
0.5
5.5
1
IOUT = 500 mA
1.5
2
2.5
Input Voltage (V)
3
3.5
IOUT = 0 mA
Figure 6-9. IQ(BIAS) vs VBIAS and Temperature
Figure 6-10. IQ(IN) vs VIN and Temperature
1.2
18
TJ
40qC
0qC
25qC
16
14
85qC
105qC
125qC
1
Output Voltage (V)
Input Pin Current (PA)
85 qC
105 qC
125 qC
12
10
8
6
0.8
0.6
TJ
40 qC
0 qC
25 qC
85 qC
105 qC
125 qC
0.4
4
0.2
2
0
1
1.5
2
2.5
Input Voltage (V)
3
3.5
0
100
200
300
400
500 600 700 800
Output Current (mA)
900 1000 1100
IOUT = 500 mA
Figure 6-11. IQ(IN) vs VIN and Temperature
Figure 6-12. Foldback Output Current Limit vs IOUT and
Temperature
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
9
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
3
3.5
TJ
40 qC
0 qC
25 qC
2.5
85 qC
105 qC
125 qC
VIN
VEN
2.5
VBIAS
VOUT
2
Voltage (V)
2
1.5
1
1.5
1
0.5
0.5
0
0
-0.5
0.6
-0.5
0.9
1.2
1.5
1.8
2.1
2.4
Input Voltage (V)
2.7
3
0
3.3
100
200
300
VOUT = 1.0 V, VEN < 0.4 V
700
Figure 6-13. ISHDN vs VIN and Temperature
Figure 6-14. Startup With VEN = VIN
VIN
VEN
VBIAS
VOUT
VIN
VEN
2.5
VBIAS
VOUT
2
Voltage (V)
2
1.5
1
1.5
1
0.5
0.5
0
0
-0.5
-0.5
0
100
200
300
400 500 600
Time (Ps)
700
800
900 1000
0
100
200
300
VOUT = 0.5 V
400 500 600
Time (Ps)
700
5
2.5
VBIAS
VOUT
50
4.5
25
4
Input Voltage (V)
2
1.5
1
0.5
0
-0.5
0
100
200
300
400 500 600
Time (Ps)
900 1000
Figure 6-16. Startup With Separated VEN
3
VIN
VEN
800
VOUT = 0.5 V
Figure 6-15. Startup With VEN and VBIAS Powering Up
Simultaneously
Voltage (V)
900 1000
3
2.5
700
800
900 1000
0
3.5
-25
VIN
-50
VOUT
-75
3
2.5
2
-100
1.5
-125
1
-150
0.5
-175
0
0
100
VOUT = 0.5 V
200
300
400 500 600
Time (Ps)
700
800
-200
900 1000
VOUT = 1.0 V, IOUT = 1 mA
Figure 6-17. Startup With VBIAS Powering Up After VIN and VEN
10
800
VOUT = 0.5 V
3
Voltage (V)
400 500 600
Time (Ps)
AC-coupled Output Voltage (mV)
Input Pin Shutdown Current (PA)
3
Submit Document Feedback
Figure 6-18. VIN Transient
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
100
450
0
400
-50
3.5
2.5
-100
VIN
-150
VOUT
-200
2
-250
1.5
-300
3
1
-350
0.5
-400
0
-450
900 1000
100
200
300
400 500 600
Time (Ps)
700
800
-100
350
-200
-300
300
VOUT
IOUT 250
-400
200
-500
150
-600
100
-700
50
-800
0
-900
-50
-1000
0
100
VOUT = 1.0 V, IOUT = 500 mA
450
0
400
-100
350
-200
-300
300
VOUT
IOUT 250
-400
200
-500
150
-600
100
-700
50
-800
0
-900
-50
-1000
300
400 500 600
Time (Ps)
700
800
AC-Coupled Output Voltage (mV)
100
Output Current (mA)
AC-Coupled Output voltage (mV)
500
200
-100
900 1000
1000
-200
VOUT
IOUT
500
-600
250
-800
0
200
VOUT
IOUT
750
-400
500
-600
250
-800
0
-250
1000
100
Power-Supply Rejection Ratio (dB)
1000
800
-250
1000
800
Figure 6-22. IOUT Transient
0
-1000
400
600
Time (Ps)
VOUT = 1.0 V, IOUT = 0 mA to 500 mA
1250
-200
750
-400
-1000
Output Current (mA)
AC-Coupled Output Voltage (mV)
-100
900 1000
0
0
200
400
600
Time (Ps)
800
1250
Figure 6-21. IOUT Transient
200
700
200
VOUT = 1.0 V, IOUT = 1 mA to 250 mA
0
400 500 600
Time (Ps)
Figure 6-20. IOUT Transient
200
100
300
VOUT = 1.0 V, IOUT = 0 mA to 250 mA
Figure 6-19. VIN Transient
0
200
Ouput Current (mA)
0
500
Output Current (mA)
200
0
AC-Coupled Output Voltage (mV)
Input Voltage (V)
4
50
AC-Coupled Output Voltage (mV)
5
4.5
IOUT
10 mA
50 mA
100 mA
200 mA
90
80
70
300 mA
400 mA
500 mA
60
50
40
30
20
10
0
10
VOUT = 1.0 V, IOUT = 1 mA to 500 mA
100
1k
10k
100k
Frequency (Hz)
1M
10M
CIN = 0 μF, VOUT = 1.0 V
Figure 6-23. IOUT Transient
Figure 6-24. VIN PSRR vs Frequency and IOUT
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
100
VDO
200 mV
400 mV
600 mV
90
80
800 mV
1000 mV
70
60
50
40
30
20
10
0
10
100
1k
10k
100k
Frequency (Hz)
1M
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
100
90
2.2 PF
70
60
50
40
30
20
10
CIN = 0 μF, VOUT = 1.0 V, IOUT = 500 mA, VDO = VIN – VOUT
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 6-26. VIN PSRR vs Frequency and COUT
100
50
90
2.4 V
3.0 V
3.5 V
80
VBIAS
4.0 V
4.5 V
5.0 V
5.5 V
70
60
50
40
30
20
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
10
10
0
10
100
1k
10k
100k
Frequency (Hz)
1M
IOUT, (PVRMS)
50 mA, (91.2)
300 mA, (85.4)
120 mA, (88.4)
400 mA, (83.7)
200 mA, (86.8)
500 mA, (82.1)
20
10
5
Output Voltage Noise (PV —Hz)
Power-Supply Rejection Ratio (dB)
100
CIN = 0 μF, VOUT = 1.0 V, IOUT = 500 mA
Figure 6-25. VIN PSRR vs Frequency and Dropout
10M
100
1k
1M
10M
Figure 6-28. Output Noise vs Frequency and IOUT
Figure 6-27. VBIAS PSRR vs Frequency and VBIAS
1.65
20
VOUT = 0.5 V, 32.2 PVRMS
VOUT = 1.0 V, 82.2 PVRMS
VOUT = 3.0 V, 193.9 PVRMS
10
1.6
Bias Voltage (UVLO) (V)
5
2
1
0.5
0.2
0.1
0.05
0.02
1.55
1.5
1.45
1.4
1.35
0.01
0.005
10
10k
100k
Frequency (Hz)
VOUT = 1.0 V
CIN = 2.2 μF, VOUT = 1.0 V, IOUT = 500 mA, CBIAS = 0 μF
Output Voltage Noise (PV —Hz)
22 PF
80
0
10
10M
COUT
10 PF
100
1k
10k
100k
Frequency (Hz)
1M
10M
1.3
-40
VBIAS UVLO (Falling)
VBIAS UVLO (Rising)
-20
0
20
40
60
80
Temperature (°C)
100
120
140
IOUT = 500 mA
Figure 6-29. Output Noise vs Frequency and VOUT
12
Figure 6-30. VUVLO(BIAS) Rising and Falling Threshold vs
Temperature
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
0.69
0.605
0.68
0.595
0.585
0.66
0.65
VIN UVLO (Falling)
VIN UVLO (Rising)
0.64
0.63
0.62
0.61
Enable Voltage (V)
Input Voltage (UVLO) (V)
0.67
VEN(LO)
VEN(HI)
0.575
0.565
0.555
0.545
0.535
0.6
0.525
0.59
0.58
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
Figure 6-31. VUVLO(IN) Rising and Falling Threshold vs
Temperature
140
0.515
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
Figure 6-32. Enable High and Low Threshold vs Temperature
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
13
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
7 Detailed Description
7.1 Overview
The TPS7A11 is a low-input, ultra-low dropout, and low quiescent current linear regulator that is optimized for
excellent transient performance. These characteristics make the device ideal for most battery-powered
applications. The implementation of the BIAS pin on the TPS7A11 vastly improves efficiency of low-voltage
output applications by allowing the use of a pre-regulated, low-voltage input supply that offers sub-band-gap
output voltages. This low-dropout regulator (LDO) offers foldback current limit, shutdown, thermal protection,
high output voltage accuracy of 1.5% over the recommended junction temperature range, and optional active
discharge.
7.2 Functional Block Diagram
Current
Limit
IN
OUT
Thermal
Shutdown
BIAS
+
Bandgap
EN
±
Global
UVLO
Internal
Controller
Active Discharge
P-Version Only
GND
7.3 Feature Description
7.3.1 Excellent Transient Response
The TPS7A11 responds quickly to a transient on the input supply (line transient) or the output current (load
transient) resulting from the device high input impedance and low output impedance across frequency. This
same capability also means that the device has a high power-supply rejection ratio (PSRR) and low internal
noise floor (en). The LDO approximates an ideal power supply with outstanding line and load transient
performance.
The choice of external component values optimizes the small- and large-signal response; see the Input and
Output Capacitor Requirements section for proper capacitor selection.
14
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
7.3.1.1 Global Undervoltage Lockout (UVLO)
The TPS7A11 uses two undervoltage lockout circuits: one on the BIAS pin and one on the IN pin to prevent the
device from turning on before either VBIAS and VIN rise above their lockout voltages. The two UVLO signals are
connected internally through an AND gate, as shown in Figure 7-1, that allows the device to be turned off when
either of these rails are below the lockout voltage.
UVLO(IN)
Global UVLO
UVLO(BIAS)
Figure 7-1. Global UVLO circuit
7.3.2 Active Discharge
The active discharge option has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when
the device is disabled in order to actively discharge the output voltage. The active discharge circuit is activated
by driving the enable pin to logic low to disable the device, or when the device is in thermal shutdown.
The discharge time after disabling the device depends on the output capacitance (COUT) and the load resistance
(RL ) in parallel with the 120-Ω pulldown resistor. Equation 1 calculates this time:
t=
120 · RL
120 + RL
· COUT
(1)
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input. This reverse current flow
can cause damage to the device. Limit reverse current to no more than 5% of the device-rated current.
7.3.3 Enable Pin
The enable pin for the device is active high. The output of the device is turned on when the enable pin voltage is
greater than the EN pin logic high voltage, and the output of the device is turned off when the enable pin voltage
is less than the EN pin logic low voltage. A voltage less than the EN pin logic low voltage on the enable pin
disables all internal circuits.
7.3.4 Sequencing Requirement
The IN, BIAS, and EN pin voltages can be sequenced in any order without causing damage to the device. The
start up is always monotonic regardless of the sequencing order or the ramp rates of the IN, BIAS, and EN pins.
For optimum device performance, VBIAS should be present before enabling the device because the device
internal circuitry is powered by VBIAS. For part numbers with an A following the voltage digits (example:
TPS7A11xxPA), the shutdown current is independent of sequencing. For part numbers without an A following the
voltage digits (example: TPS7A11xxP), the shutdown current into the BIAS input may increase by approximately
2 µA if the BIAS supply was present before the LDO was enabled and then disabled. This behavior can be
avoided with part numbers without an A by applying a logic high enable signal before applying the BIAS supply.
See the Recommended Operating Conditions table for proper voltage ranges of the IN, BIAS, and EN pins.
7.3.5 Internal Foldback Current Limit
The internal foldback current limit circuit is used to protect the LDO against high-load current faults or shorting
events. The foldback mechanism lowers the current limit as the output voltage decreases and limits power
dissipation during short-circuit events, while still allowing for the device to operate at the rated output current;
see Figure 6-12.
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
15
TPS7A11
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
www.ti.com
For example, when VOUT is 90% of VOUT(nom), the current limit is ICL (typical); however, if VOUT is forced to 0 V,
the current limit is ISC (typical). In many LDOs, the foldback current limit can prevent start up into a constantcurrent load or a negatively-biased output. A brick-wall current limit is when there is an abrupt current stop after
the current limit is reached. The foldback mechanism for this device goes into a brick-wall current limit when
VOUT is 90% of VOUT(nom), thus limiting current to ICL (typical). When VOUT is approximately 0 V, current is limited
to ISC (typical) in order to provide normal start up into a variety of loads. Thermal shutdown can be activated
during a current-limit event because of the high power dissipation typically found in these conditions. To provide
proper operation of the current limit, minimize the inductances to the input and load. Continuous operation in
current limit is not recommended.
7.3.6 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the thermal junction
temperature (TJ ) of the main pass-FET rises to the thermal shutdown temperature (TSD) for shutdown listed in
the Electrical Characteristics table. Thermal shutdown hysteresis ensures that the LDO resets again (turns on)
when the temperature falls to TSD for reset.
The thermal time constant of the semiconductor die is fairly short, and thus the device may cycle on and off
when thermal shutdown is reached until the power dissipation is reduced.
For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the
device to exceed the operational specifications. Although the internal protection circuitry of the device is
designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat
sinking. Continuously running the device into thermal shutdown or above a junction temperature of 125°C
reduces long-term reliability.
A fast start up when TJ > TSD for reset (typical, outside of the specified operation range) causes the device
thermal shutdown to assert at TSD for reset, and prevents the device from turning on until the junction
temperature is reduced below TSD for reset.
16
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
7.4 Device Functional Modes
The device has the following modes of operation:
•
•
•
Normal operation: The device regulates to the nominal output voltage
Dropout operation: The pass element operates as a resistor and the output voltage is set as VIN – VDO
Disabled: The output of the device is disabled and the discharge circuit is activated
Table 7-1 shows the conditions that lead to the different modes of operation.
Table 7-1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
VBIAS
VEN
IOUT
TJ
Normal mode
VIN > VOUT (nom) + VDO
and VIN > VIN(min)
VBIAS > VOUT + VDO(BIAS)
VEN > VHI(EN)
IOUT < ICL
TJ < TSD for
shutdown
Dropout mode
VIN(min) < VIN < VOUT
(nom) + VDO(IN)
VBIAS < VOUT + VDO(BIAS)
VEN > VHI(EN)
IOUT < ICL
TJ < TSD for
shutdown
VIN < VUVLO(IN)
VBIAS < VBIAS(UVLO)
VEN < VLO(EN)
—
TJ > TSD for
shutdown
Disabled mode
(any true condition
disables the device)
7.4.1 Normal Mode
The device regulates the output to the nominal output voltage when all normal mode conditions in Table 7-1 are
met.
7.4.2 Dropout Mode
The device is not in regulation, and the output voltage tracks the input voltage minus the voltage drop across the
pass element of the device. In this mode, the PSRR, noise, and transient performance of the device are
significantly degraded.
7.4.3 Disable Mode
In this mode the pass element is turned off, the internal circuits are shut down, and the output voltage is actively
discharged to ground by an internal resistor.
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
17
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in an application depends on the application requirements. This section
discusses key device features and how to best implement them to achieve a reliable design.
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input,
output, and bias pins. Multilayer ceramic capacitors are the industry standard for these types of applications, but
must be used with good judgment. Ceramic capacitors that use X7R-, X5R-, and COG-rated dielectric materials
provide relatively good capacitive stability across temperature. Avoid Y5V-rated capacitors because of large
variations in capacitance. Regardless of the ceramic capacitor type selected, ceramic capacitance varies with
operating voltage and temperature. As a rule of thumb, assume that effective capacitance decreases by as much
as 50%. The input, output, and bias capacitors recommended in the Recommended Operating Conditions table
account for an effective capacitance of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
A minimum input ceramic capacitor is required for stability. A minimum output ceramic capacitor is also required
for stability, refer to the Recommended Operating Conditions table for the minimum capacitors values.
The input capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR.
A higher-value input capacitor may be necessary if large, fast rise-time load or line transients are anticipated, or
if the device is located several inches from the input power source. Dynamic performance of the device is
improved with the use of an output capacitor larger than the minimum value specified in the Recommended
Operating Conditions table.
Although a bias capacitor is not required, connect a 0.1-µF ceramic capacitor from BIAS to GND for best analog
design practice. This capacitor counteracts reactive bias sources if the source impedance is not sufficiently low.
Place the input, output, and bias capacitors as close as possible to the device to minimize trace parasitics.
8.1.3 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current while
output voltage regulation is maintained. See Figure 6-20 to Figure 6-23 for typical load transient response. There
are two key transitions during a load transient response: the transition from a light to a heavy load, and the
transition from a heavy to a light load. The regions in Figure 8-1 are broken down as described in this section.
Regions A, E, and H are where the output voltage is in steady-state operation.
tAt
tCt
B
tDt
tEt
tGt
tHt
F
Figure 8-1. Load Transient Waveform
18
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
During transitions from a light load to a heavy load, the:
•
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage
regulation (region C)
During transitions from a heavy load to a light load, the:
•
•
Initial voltage rise results from the LDO sourcing a large current, and leads to an increase in the output
capacitor charge (region F)
Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
8.1.4 Dropout Voltage
Generally, the dropout voltage often refers to the minimum voltage difference between the input and output
voltage (VDO = VIN – VOUT) that is required for regulation. When VIN – VOUT drops below the required VDO for the
given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout
voltage is linearly proportional to the output current because the device is operating as a resistive switch, see
Figure 6-4 and Figure 6-5.
Dropout voltage is also affected by the drive strength for the gate of the pass element, which is nonlinear with
respect to VBIAS on this device because of the inherited nonlinearity of the pass element gate capacitance, see
Figure 6-7.
8.1.5 Behavior During Transition From Dropout Into Regulation
Some applications may have transients that place this device into dropout, especially when this device can be
powered from a battery with relatively high ESR. The load transient saturates the output stage of the error
amplifier when the pass element is driven fully on, making the pass element function like a resistor from VIN to
VOUT. The error amplifier response time to this load transient is limited because the error amplifier must first
recover from saturation and then places the pass element back into active mode. During this time, VOUT
overshoots because the pass element is functioning as a resistor from VIN to VOUT.
When VIN ramps up slowly for start-up, the slow ramp-up voltage may place the device in dropout. As with many
other LDOs, the output can overshoot on recovery from this condition. However, this condition is easily avoided
through the use of the enable signal.
If operating under these conditions, apply a higher dc load or increase the output capacitance to reduce the
overshoot. These solutions provide a path to dissipate the excess charge.
8.1.6 Undervoltage Lockout Circuit Operation
The VIN UVLO circuit makes sure that the device remains disabled before the input supply reaches the minimum
operational voltage range. The VIN UVLO circuit also makes sure that the device shuts down when the input
supply collapses. Similarly, the VBIAS UVLO circuit makes sure that the device stays disabled before the bias
supply reaches the minimum operational voltage range. The VBIAS UVLO circuit also makes sure that the device
shuts down when the bias supply collapses.
Figure 8-2 depicts the UVLO circuit response to various input or bias voltage events. The diagram can be
separated into the following parts:
•
•
•
•
Region A: The device does not start until the input or bias voltage reaches the UVLO rising threshold
Region B: Normal operation, regulating device
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hystersis). The
output may fall out of regulation but the device is still enabled.
Region D: Normal operation, regulating device
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
19
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
•
•
•
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO
rising threshold is reached and a normal start-up follows.
Region F: Normal operation followed by the input or bias falling to the UVLO falling threshold
Region G: The device is disabled when the input or bias voltages fall below the UVLO falling threshold to 0 V.
The output falls as a result of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN / VBIAS
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 8-2. Typical VIN or VBIAS UVLO Circuit Operation
8.1.7 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
Equation 2 calculates the maximum allowable power dissipation for the device in a given package:
PD-MAX = [(TJ – TA) / RθJA]
(2)
Equation 3 represents the actual power being dissipated in the device:
PD = (IGND + IOUT) × (VIN – VOUT)
(3)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A11 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device depends on the ambient temperature and the thermal resistance
across the various interfaces between the die junction and ambient air.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 4, maximum power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA). The equation is rearranged in Equation 5 for output current.
TJ = TA + (RθJA × PD)
(4)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
(5)
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB,
and copper-spreading area, and is only used as a relative measure of package thermal performance. For a welldesigned thermal layout, RθJA is actually the sum of the DRV package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
20
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
8.1.8 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 6 and are given in the Electrical Characteristics table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
(6)
where:
•
•
•
PD is the power dissipated as explained in Equation 3
TT is the temperature at the center-top of the device package
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.9 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is shown in Figure 8-3 and can
be separated into the following regions:
•
•
•
Output Current (A)
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level; see the Dropout Voltage section for more details.
The rated output current limits the maximum recommended output current level. Exceeding this rating causes
the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– Equation 5 provides the shape of the slope. The slope is nonlinear because the maximum rated junction
temperature of the LDO is controlled by the power dissipation across the LDO, thus when VIN – VOUT
increases the output current must decrease.
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited
by Thermals
Limited by
Maximum VIN
Limited by
Minimum VIN
VIN ± VOUT (V)
Figure 8-3. Continuous Operation Diagram With Description of Regions
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
21
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
8.2 Typical Application
2.4 V ~ 5.5 V
IN
OUT
Low Iq
DC/DC Converter
Rechargeable
Battery
CBIAS
1.2 V
CIN
BIAS
IN
1.0 V
OUT
VOUT
COUT
TPS7A11
EN
GND
GND
Figure 8-4. High Efficiency Supply From a Rechargeable Battery
8.2.1 Design Requirements
Table 8-1 lists the parameters for this design example.
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
1.2 V
VBIAS
2.4 V (min)
VOUT
1.0 V
IOUT
150 mA (typical), 500 mA (peak)
8.2.2 Detailed Design Procedures
This design example is powered by a rechargeable battery that can be a building block in many portable
applications. Noise-sensitive portable electronics require an efficient small-size solution for their power supply.
Traditional LDOs are known for their low efficiency in contrast to the low-input, low-output voltage (LILO) LDOs
such as the TPS7A11. The use of a bias rail in the TPS7A11 allows the device to operate at a lower input
voltage, thus reducing the power dissipation across the die and maximizing device efficiency. Equation 7
calculates the efficiency for this design.
Efficiency = η = POUT/PIN ×100 % = (VOUT × IOUT) /(VIN × IIN + VBIAS × IBIAS) × 100 %
(7)
Equation 7 reduces to Equation 8 because the design example load current is much greater than the quiescent
current of the bias rail.
Efficiency = η = (VOUT × IOUT) / (VIN × IIN) × 100%
22
Submit Document Feedback
(8)
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
8.2.3 Application Curve
Figure 8-5 shows a plot of the calculated efficiency.
100
Efficiency ( )
80
60
40
20
0
0.001
0.01
0.1
1
10
Output Current (mA)
100
1000
VIN = VEN = 1.2 V, CIN = 2.2 µF, VOUT = 1.0 V, COUT = 2.2 µF, VBIAS = 2.4 V, CBIAS = 0.1 µF
Figure 8-5. TPS7A11 Output Efficiency at 1.2 VIN and 1.0 VOUT
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 0.75 V to 3.3 V and a bias supply
voltage range of 1.7 V to 5.5 V. The input and bias supplies must be well regulated and free of spurious noise. To
make sure that the output voltage is well regulated and dynamic performance is optimum, the input supply must
be at least VOUT(nom) + 0.5 V and VBIAS = VOUT(nom) + VDO(BIAS).
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
23
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
10 Layout
10.1 Layout Guidelines
For correct printed circuit board (PCB) layout, follow these guidelines:
•
•
•
Place input, output, and bias capacitors as close to the device as possible
Use copper planes for device connections to optimize thermal performance
Place thermal vias around the device to distribute heat
10.2 Layout Examples
OUT
IN
CIN
COUT
A1
GND
A3
B2
C1
C3
CBIAS
EN
BIAS
Figure 10-1. Recommended Layout for YKA Package
Ground Plane
To Bias Supply
4
BIAS
5
GND
EN
3
NC
2
To Enable
Signal
Thermal Pad
CBIAS
COUT
CIN
6
IN
OUT
1
To Load
To Input Supply
Ground Plane
Figure 10-2. Recommended Layout for DRV Package
24
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS7A11. The TPS720xxDRVEVM evaluation module (and related user guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
11.1.2 Spice Model
Spice models for this device are available through the for the TPS7A11 product folder under the Tool and
Software tab.
11.1.3 Device Nomenclature
Table 11-1. Device Nomenclature (1) (2)
(1)
(2)
PRODUCT
VOUT
TPS7A11xx(x)(P)(A)yyyz
xx(x) is the nominal output voltage. For output voltages with a resolution of 50 mV, two digits are used in
the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
(P), when present, indicates the active discharge option.
(A), when present, indicates the BIAS shutdown current is independent of sequencing. See the
Sequencing Requirement section.
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
() indicates optional placeholders.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 0.5 V to 3.0 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS720xxDRVEVM Evaluation Module user's guide
• Texas Instruments, Using New Thermal Metrics application report
• Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package application report
• Texas Instruments, TIDA-01566 Light Load Efficient, Low Noise Power Supply Reference Design for
Wearables and IoT design guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
25
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS7A11
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS7A1105PYKAR
ACTIVE
DSBGA
YKA
5
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
G
TPS7A1106PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1R6H
TPS7A1106PDRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1R6H
TPS7A1106PYKAR
ACTIVE
DSBGA
YKA
5
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
H
TPS7A11075PYKAR
ACTIVE
DSBGA
YKA
5
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
I
TPS7A1108PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1R7H
TPS7A1108PDRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1R7H
TPS7A1109PYKAR
ACTIVE
DSBGA
YKA
5
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
J
TPS7A11105PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1R9H
TPS7A11105PDRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1R9H
TPS7A11105PYKAR
ACTIVE
DSBGA
YKA
5
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
K
TPS7A1110PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1R8H
TPS7A1110PDRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1R8H
TPS7A1110PYKAR
ACTIVE
DSBGA
YKA
5
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
L
TPS7A1111PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RAH
TPS7A1111PDRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RAH
TPS7A1111PYKAR
ACTIVE
DSBGA
YKA
5
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
3
TPS7A1112PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RBH
TPS7A1112PDRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RBH
TPS7A1112PYKAR
ACTIVE
DSBGA
YKA
5
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
U
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
30-Sep-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS7A1115PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RCH
TPS7A1115PDRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RCH
TPS7A1118PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RDH
TPS7A1118PDRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RDH
TPS7A1118PYKAR
ACTIVE
DSBGA
YKA
5
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
M
TPS7A1119PYKAR
ACTIVE
DSBGA
YKA
5
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
D
TPS7A1125PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1REH
TPS7A1125PDRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1REH
TPS7A1128PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RFH
TPS7A1128PDRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RFH
TPS7A1128PYKAR
ACTIVE
DSBGA
YKA
5
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
N
TPS7A1130PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RGH
TPS7A1130PDRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1RGH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
