XTR108EAG4

XT R XTR108 108 SBOS187C – OCTOBER 2001 – REVISED JULY 2005 4-20mA, TWO-WIRE TRANSMITTER “Smart” Programmable with Signal Conditioning FEATURES DESCRIPTION ● COMPLETE TRANSMITTER + RTD LINEARIZATION ● TWO-WIRE, 4-20mA OUTPUT ● VOLTAGE OUTPUT (0.5V to 4.5V) ● ELIMINATES POTENTIOMETERS AND TRIMMING ● DIGITALLY CALIBRATED ● 5V SUB-REGULATOR OUTPUT ● SERIAL SPI BUS INTERFACE ● SSOP-24 PACKAGE The XTR108 is a “smart,” programmable, 4-20mA, two-wire transmitter designed for temperature and bridge sensors. Zero, span, and linearization errors in the analog signal path can be calibrated via a standard digital serial interface, eliminating manual trimming. Non-volatile external EEPROM stores calibration settings. The all-analog signal path contains an input multiplexer, autozeroed programmable-gain instrumentation amplifier, dual programmable current sources, linearization circuit, voltage reference, sub-regulator, internal oscillator, control logic, and an output current amplifier. Programmable level shifting compensates for sensor DC offsets. Selectable up- and down-scale output indicates out-of-range and burnout per NAMUR NE43. Automatic reset is initiated when supply is lost. APPLICATIONS ● ● ● ● ● ● REMOTE RTD TRANSMITTERS PRESSURE BRIDGE TRANSMITTERS STRAIN GAGE TRANSMITTERS SCADA REMOTE DATA ACQUISITION WEIGHING SYSTEMS INDUSTRIAL PROCESS CONTROL Current sources, steered through the multiplexer, can be used to directly excite RTD temperature sensors, pressure bridges, or other transducers. An uncommitted op amp can be used to convert current into a voltage. The XTR108 is specified for –40°C to +85°C. CS1 CS2 SDIO SCLK EEPROM Gain and Offset SPI and Control Circuits Excitation Linearization V/I-0 VPS 4-20mA V/I-2 V/I-3 V/I-4 Multiplexer V/I-1 IO PGA V/I RLOAD V/I-5 R1 R2 R3 R4 R5 XTR108 IRet RTD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. Copyright © 2001-2005, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Loop Supply Voltage, VPS ............................ Dependent on External FET XTR Supply Voltage, External VS (Referenced to IRET Pin) ............ +5.5V This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Input Voltage to Multiplexer (Referenced to IRET Pin) ................ 0V to VS Output Current Limit ................................................................ Continuous Storage Temperature Range ......................................... –55°C to +125°C Junction Temperature .................................................................... +165°C Lead Temperature (soldering, 10s) ............................................... +300°C ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. PACKAGE/ORDERING INFORMATION(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY XTR108EA XTR108EA/2K5 Rails Tape and Reel, 2500 PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR XTR108EA SSOP-24 DBQ –40°C to +85°C XTR108EA " " " " " NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = –40°C to +85°C. At TA = +25°C, VPS = 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to IRET pin. XTR108EA PARAMETER VIN TO IOUT TRANSFER FUNCTION Output Specified Range Over-Scale Limit Resolution Fault Over-Scale Level(1) Under-Scale Limit Resolution Fault Under-Scale Level(1) Output for Zero Input Zero Error, Unadjusted vs Temperature vs Loop-Supply Voltage, VLOOP vs Common-Mode Voltage Adjustment Resolution, Zero Input Adjustment Range, Zero Input Span(2) Initial, Unadjusted Drift (vs Temperature) Span Adjustment Resolution Span Adjustment Range PGA + Output Amplifier(3) Nonlinearity, Ideal Input PGA Autozeroing Internal Frequency PGA Offset Voltage (RTI)(4) vs Temperature vs Supply Voltage, VS vs Common-Mode Voltage Common-Mode Input Range Input Bias Current vs Temperature Input Offset Current vs Temperature 2 CONDITIONS MIN TYP MAX UNITS 20 mA mA mA mA mA IO = VIN (Span) + 4mA 4 Digital Select: 21-28.5mA Above Over-Scale Selected Digital Select: 2.2-3.6mA Below Under-Scale Selected 0.5 +1.0 0.2 –0.4 VIN = 0V ±50 ±0.2 0.02 ±1 1.8 ±4 VLOOP = 7.5V to 24V VCM = 0.2V to 3.5V Span = IO/VIN RVI = 6.34kΩ Full-Scale VIN = 50mV ±1.5 ±1 40 0.05 49.3 % ppm/°C % 3150 0.01 6.5 ±10 ±0.02 ±0.5 105 VCM = 1V VS = 4.5V to 5.5V VCM = 0.2V to 3.5V 0.2 ±50 VS – 1.5 50 Doubles/10°C 10 Doubles/10°C µA µA/°C µA/V µA/V µA/Step mA mA/V % kHz µV µV/°C µV/V dB V pA pA pA pA XTR108 www.ti.com SBOS187C ELECTRICAL CHARACTERISTICS (Cont.) Boldface limits apply over the specified temperature range, TA = –40°C to +85°C. At TA = +25°C, VPS = 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to IRET pin. XTR108EA PARAMETER PGA (Cont.) Input Impedance: Differential Input Impedance: Common-Mode Voltage Noise, 0.1Hz to 10Hz PGA Gain Gain Range Steps Initial Error vs Temperature Output Voltage Range(5) Typical Operating Range Capacitive Drive Short-Circuit Current ZERO OFFSET DACS Zero-Code Output Level RTO(6) of Current Amplifier RTO(6) of PGA Coarse DAC, 256 Steps Adjustment Range RTO(6) of Current Amplifier RTO(6) of PGA Step Size RTO(6) of Current Amplifier RTO(6) of PGA Linearity Fine DAC, 256 Steps Adjustment Range RTO(6) of Current Amplifier RTO(6) of PGA Step Size RTO(6) of Current Amplifier RTO(6) of PGA Linearity Noise, RTO(6) CONDITIONS LINEARIZATION DAC Linearization Range, 256 Steps Max Linearization Coefficient Step Size SUB-REGULATOR, VS Voltage vs Temperature vs Loop-Supply Voltage 6.25, 12.5, 25, 50, 100, 200, 400 Gain = 6.25, 12.5, 25, 50 G = 100, 200 G = 400 6.25 RLOAD = 6.34kΩ to IRET for 4-20mA XTR Output 0.2 ±0.5 ±0.5 ±0.8 ±30 MAX UNITS GΩ || pF GΩ || pF µVp-p 400 ±2.5 ±3 ±3.5 4.5 0.5 to 2.5 200 +6/–9 VCM = 1V, VIN = 0V RV/I = 6.34kΩ V/V % % % ppm/°C V V pF mA 4.116 522 7 Bits + Sign mA mV –3.77 to +3.77 –470 to +470 mA mV 0.029 3.7 ±0.5 7 Bits + Sign mA mV LSB –236 to +236 –29.4 to +29.4 µA mV 0.0018 0.23 ±1 1.1 mA mV LSB µAp-p Relative to Zero-Code Level Relative to Zero-Code Level f = 0.1Hz to 10Hz RSET = 12.1kΩ 49 50 10 51 A/A ppm/°C 480 493 7 Bits + Sign –195 to +195 1.54 7 Bits + Sign –12.2 to +12.2 96 510 µA VS – 2 f = 0.1Hz to 10Hz ∆IREF/∆VIN, RLIN = 15.8kΩ µA µA µA nA ±0.2 ±0.5 ±35 ±0.2 ±10 VS – 1.5 100 0.015 LSB LSB ppm/°C % ppm/°C V MΩ µAp-p 8 Bits 0.99 3.9 µA/mV nA/mV Supply Voltage for XTR 4.8 VLOOP = 7.5V to 24V XTR108 SBOS187C TYP 30 || 6 50 || 20 6 CURRENT AMPLIFIER Current Gain Current Gain Drift CURRENT SOURCES, IREF1 AND IREF2 Zero-Code Output Level, Each Coarse DAC, 256 Steps Adjustment Range(7) Step Size Fine DAC, 256 Steps Adjustment Range(7) Step Size Linearity Coarse Fine vs Temperature Matching vs Temperature Compliance Voltage, Positive(5) Output Impedance Current Noise MIN www.ti.com 5.1 ±50 ±0.03 5.4 V ppm/°C mV/V 3 ELECTRICAL CHARACTERISTICS (Cont.) Boldface limits apply over the specified temperature range, TA = –40°C to +85°C. At TA = +25°C, VPS = 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to IRET pin. XTR108EA PARAMETER OVER- AND UNDER-SCALE LIMITING Over-Scale DAC: 16 Steps Adjustment Range RTO(6) of Current Amplifier RTO(6) of PGA Step Size RTO(6) of Current Amplifier RTO(6) of PGA Accuracy Under-Scale DAC: 8 Steps Adjustment Range RTO(6) of Current Amplifier RTO(6) of PGA Step Size RTO(6) of Current Amplifier RTO(6) of PGA Accuracy CONDITIONS MIN RVI = 6.34kΩ RVI = 6.34kΩ VOLTAGE REFERENCE, VREF Internal Bandgap vs Temperature UNCOMMITTED OP AMP Input Offset Voltage vs Temperature vs Common-Mode Voltage Open-Loop Gain Common-Mode Input Range Output Voltage Range DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIL VIH VOL VOH Input Current IIH (CS1) IIL (CS1) IIH, IIL (SCLK, DIO) UNITS Bits 20.7 to 28.1 2.625 to 3.563 mA V 0.49 62.5 ±10 3 mA mV % Bits 2.17 to 3.55 275 to 450 mA mV 0.195 25 ±5 mA mV % ±50 V ppm/°C VS – 0.2 mV µV/°C dB dB V V ±2 ±3 90 110 0 to 3.5 VCM = 2V RL = 10kΩ to VS / 2 MAX 4 1.193 ±5 0.2 CMOS 0 3.5 IOL = 300µA IOH = –300µA VS – 1 3.5 < VIN < VS 0 < VIN < 0.8 0 < VIN < VS –200 –20 –20 INTERNAL OSCILLATOR Frequency, fOSC –120 –6 –6 0.8 VS 0.4 V V V V 10 10 10 µA µA µA 210 TEMPERATURE RANGE Specification Operating θJA, Junction to Ambient LOOP SUPPLY Voltage Range Quiescent Current TYP 100 °C °C °C/W 0.5 V mA –40 –55 with Supertex DN2540 RSET Open, LINReg = 0, No Sensor Current(8)(9) kHz +85 +125 7.5 NOTES: (1) Over-scale and under-scale complies with NAMUR NE43 recommendation. (2) Span adjustment is determined by PGA gain and sensor excitation. (3) Span can be digitally adjusted in three ways: PGA gain, current reference Coarse, and current reference Fine. (4) RTI = Referred to Input. (5) Current source output voltage measured with respect to IRET. (6) RTO = Referred to Output. (7) Excitation DAC range sufficient to adjust span fully between PGA gain steps. (8) Output current into external circuitry is limited by an external MOS power FET. (9) Measured with over- and under-scale limits disabled. 4 XTR108 www.ti.com SBOS187C PIN CONFIGURATION Top View SSOP V/I-0 1 24 OPA +IN V/I-1 2 23 OPA –IN V/I-2 3 22 OPA OUT V/I-3 4 21 REFOUT V/I-4 5 20 REFIN V/I-5 6 19 RSET XTR108 CFILTER 7 18 CS1 RLIN 8 17 SCLK VO 9 16 SDIO IIN 10 15 CS2 IO 11 14 VGATE IRET 12 13 VS PIN ASSIGNMENTS PIN V/I-0 V/I-1 V/I-2 V/I-3 V/I-4 V/I-5 CFILTER RLIN VO IIN IO IRET VS VGATE CS2 SDIO SCLK CS1 RSET REFIN REFOUT OPA OUT OPA –IN OPA +IN NAME FUNCTION Channel 0 and/or IREF Out Channel 1 and/or IREF Out Channel 2 and/or IREF Out Channel 3 and/or IREF Out Channel 4 and/or IREF Out Channel 5 and/or IREF Out Filter Capacitor Linearization PGA Output Current Input Output Current Return Current Voltage Regulator Gate Voltage Chip Select 2 Serial Data Input/Output Serial Clock Chip Select 1 Resistor for Reference Voltage Reference Input Voltage Reference Output Uncommitted Op Amp Output Uncommitted Op Amp Negative Input Uncommitted Op Amp Positive Input MUX Input to PGA and/or IREF to Sensor MUX Input to PGA and/or IREF to Sensor MUX Input to PGA and/or IREF to Sensor MUX Input to PGA and/or IREF to Sensor MUX Input to PGA and/or IREF to Sensor MUX Input to PGA and/or IREF to Sensor Filter to Reduce Chopper Noise in Autozeroing PGA Linearization Range Adjustment Resistor PGA Amplified Output of Differential Sensor Input Input to Output Current Amplifier 4-20mA Current for Output Loop Return for All External Circuitry Current Supply Voltage for XTR and External Circuitry, If Used Gate Voltage for External MOSFET Transistor Select for XTR Serial Port to External EEPROM (Output from XTR Only) Serial Data Input or Output Serial Clock Select for External µC Serial Port (Input to XTR Only) Sets Current Reference Voltage Reference Input to XTR Voltage Reference Output from Internal Bandgap Uncommitted Op Amp Output Uncommitted Op Amp Negative Input Uncommitted Op Amp Positive Input MUX MUX MUX MUX MUX MUX Input Input Input Input Input Input XTR108 SBOS187C www.ti.com 5 TYPICAL CHARACTERISTICS At TA = +25°C, V+ = 24V, unless otherwise noted. RVI = 6.34kΩ. COMMON-MODE REJECTION vs FREQUENCY TRANSCONDUCTANCE vs FREQUENCY 90 G = 400 60 50 80 G = 200 40 Rejection (20log mA ) V Transconductance (20log mA ) V 70 G = 50 30 20 10 0 –10 G = 6.25 70 60 G = 100 50 40 30 G = 6.25 G = 400 20 –20 –30 100 10 10k 1k 10 100k 200k 100 1k IZERO VLOOP REJECTION RATIO vs FREQUENCY 100k IREF VLOOP REJECTION RATIO vs FREQUENCY 100 120 90 110 80 Transconductance (–20 log(mA/V)) Transconductance (–20 log(mA/V)) 10k Frequency (Hz) Frequency (Hz) 70 60 50 100 90 80 40 70 30 60 20 10 100 1k 10k 10 100 Frequency (Hz) 1k 10k Frequency (Hz) IREF vs TEMPERATURE IOUT DRIFT AVERAGE 492 20% 18% Percent of Units 16% IREF (µA) 490 488 14% 12% 10% 8% 6% 4% 2% 1.00 0.90 Temperature (°C) 0.70 125 0.50 100 0.30 75 0.10 50 –0.10 25 –0.30 0 –0.50 –25 –0.70 0% –50 –0.90 486 –75 IOUT Drift (µA/°C) 6 XTR108 www.ti.com SBOS187C TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, V+ = 24V, unless otherwise noted. RVI = 6.34kΩ. LARGE INPUT STEP RESPONSE VIN VIN LARGE INPUT STEP RESPONSE 20mA IOUT IOUT 20mA 4mA 4mA PGA Gain = 6.25 CFILT = 0 PGA Gain = 6.25 CFILT = 0.01µF 500µs/div SMALL INPUT STEP RESPONSE SMALL INPUT STEP RESPONSE VIN VIN 250µs/div 20mA IOUT IOUT 20mA 4mA 4mA PGA Gain = 200 CFILT = 0 PGA Gain = 200 500µs/div 250µs/div IREF NOISE POWER IZERO CURRENT NOISE POWER 10 100 Noise Density (nA/√Hz) Noise Density (nA/√Hz) CFILT = 0.01µF 1.0 0.1 10 1 1 10 100 1k 10k 1 Frequency (Hz) XTR108 SBOS187C www.ti.com 10 100 Frequency (Hz) 1k 10k 7 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, V+ = 24V, unless otherwise noted. RVI = 6.34kΩ. INPUT NOISE POWER DENSITY PGA PEAK-TO-PEAK NOISE (RTI) 1000 1.25µV/div Noise Density (nV√Hz) BW: 0.1Hz to 10Hz 100 CFILT = 0.01 10 1 10 100 1k 5s/div 10k Frequency (Hz) OVERVIEW 8 EE PROM SDIO CS2 The XTR108 is a 4-20mA current-loop transmitter that allows the user to digitally adjust the gain, offset, and linearity correction of the analog output to calibrate the sensor. The digital data for adjustment are stored in an external EEPROM device. The analog signal path is composed of a compound multiplexer (MUX), programmable gain instrumentation amplifier (PGA), and an output current amplifier. Analog support functions include digitally controlled current sources for sensor excitation, PGA offset control, linearization, voltage reference, and voltage regulator. The digital interface communicates with external devices for calibration and to store the resultant data in an SPI compatible EEPROM. A complete system is shown in Figure 1. The XTR108 serial interface is SPI compatible and only requires four connections to the calibration controller: a serial clock (SCLK), a serial data line (SDIO), a chip select line (CS1), and a ground sense line. All logic signals to the XTR108 must be referenced to the potential of the ground sense line (IRET pin on the XTR108). Within this entire system there may exist three different “GND” voltage levels. In addition, the voltage difference between the IRET and IO potential will depend on the output current level. It is not certain that the “GND” potential of the calibration system will be at the same potential of either the IRET or IO potential, and therefore the isolation couplers are shown in Figure 1. All voltages specified for the XTR108 are with reference to the IRET pin. SCLK CS1 Isolation Couplers Calibration System Calib GND XTR108 IO IRET TX GND RV PS RX GND FIGURE 1. Complete System Level Configuration with Three Unique Ground Voltage Levels. The XTR108 also needs to communicate with the external EEPROM device independently from the calibration controller to retrieve the calibration constants during normal operation. The XTR108 provides a second chip select function (CS2) for the EEPROM device to facilitate this communication. XTR108 www.ti.com SBOS187C THEORY OF OPERATION REFERENCE The XTR108 has an on-board precision bandgap voltage reference with output at pin 21 (REFOUT). The value of the reference is factory-trimmed to 1.193V, with a typical temperature drift of 5ppm/°C. Pins 21 (REFOUT) and 20 (REFIN) must be connected together to use the internal reference. External circuitry, such as a voltage excited sensor or an Analog-to-Digital Converter (ADC), can be connected to the REFOUT pin. The unbuffered REFOUT is capable of sourcing current but not sinking. If the application necessitates, an external reference can be connected to the XTR108 REFIN pin, as long as the reference does not exceed 1.4V. The REFIN pin has a high input impedance with the input current not exceeding a few nanoamps. If over-scale and under-scale limiting is disabled, the PGA can be used with rail-to-rail voltage output, for example, in applications that require a 0.5V to 4.5V voltage scale. The PGA uses advanced auto-zero circuit techniques to achieve high DC precision, and reduce mismatches and errors within the chip such as input offset, offset temperature drift, and lowfrequency noise (see the input noise typical characteristic). The basic clock frequency of the auto-zero loop is about 6.5kHz. Due to the switching nature of the auto-zero circuit, the output of the PGA can have a noticeable clock feedthrough ripple in higher gains. This noise can be reduced by the addition of a 0.01µF capacitor between pin 7 (CFILTER) and the local ground, pin 12 (IRET). This creates a one-pole low-pass filter with –3dB frequency at about 1.5kHz. If wider bandwidth or faster settling time is needed, the CFILTER can be reduced or eliminated at the expense of higher glitch amplitude at the output. Please refer to the typical step response traces for settling time comparisons. INPUT MULTIPLEXER The XTR108 input multiplexer is a full 6 by (2+2) crosspoint switch. The current references and PGA inputs can be independently connected to any of the six external pins, including simultaneous connections to the same pin. This allows a great flexibility in the sensor excitation and input configuration. The input pins must not be driven below the IRET potential or above VS. See Figure 2 for an RTD sensor connected to pin VIN0 with both IREF supplied and PGA VIN+ sensed at that pin. The other five input pins are used for a bank of RZ resistors that can be selected during the calibration process for a particular measurement range. PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER The programmable gain instrumentation amplifier has seven voltage-gain settings in binary steps from 6.25V/V to 400V/V. The input common-mode range of the PGA is 0.2V to 3.5V above the IRET potential. Normally, in the application for 4-20mA transmitters, the PGA output voltage range should be set to VZERO = 0.5V and VFS = 2.5V. Connecting a resistor (RVI = 6.34kΩ) between pin 9 (VO) and pin 10 (IIN) converts this voltage to the signal for the output amplifier that produces a 4-20mA scale current output. In this mode, the PGA voltage gain converts to an overall transconductance in the range of 50mA/V to 3200mA/V (approximately). Table I shows the gain to transconductance relationship. VOLTAGE GAIN V/V 6.25 12.5 OUTPUT TRANSCONDUCTANCE mA/V 49 99 FULL-SCALE DIFFERENTIAL VIN mV 320 160 25 50 40 Two output-referred, 8-bit Digital-to-Analog Converters (DACs) (coarse and fine with a pedestal) set the zero level of the PGA output. They allow setting a desired zero-scale output level and compensate the initial offset at the PGA input due to the sensor and resistor mismatches, sensor non-idealities, etc. Both coarse and fine DACs are bidirectional and allow the output level to be set above or below a preset pedestal. Output signals of the DACs, IZ COARSE and IZ FINE, are summed with the pedestal, IZ PROGRAM. Each of the DACs has 8-bit resolution (256 steps) with 4-bit overlap between the coarse and fine DACs. This means that one LSB of the coarse DAC is equal to 16 fine LSBs, and the full-scale range of the fine DAC is equal to 16 coarse LSBs. This effectively produces 12-bit adjustment resolution. This overlap allows the user to set pre-calculated values before the calibration, using the coarse DAC only and adjust the zero output level with the fine DAC during the calibration process see Table II for the equations for calculating the value of the output when zero differential voltage is applied at the PGA input. For the adjustment range, LSB sizes, and linearity values of the Zero DACs, please refer to the electrical characteristics table. Note that a DAC can be set to a value that produces an output below the under-scale level. In this case, the underscale limit will prevent the output from getting to the desired value. The value of the minimum scale should not be set so low that the PGA voltage output, VO, goes below its specified range of 0.2V from IRET. 100 200 400 197 394 789 1577 3155 80 ZERO DACS 20 10 5 TABLE I. PGA Gain, Corresponding Loop Transductance and Input Full-Scale Differential Voltage. ADJUSTABLE OVER-SCALE AND UNDER-SCALE LIMITING CIRCUIT The XTR108 incorporates circuitry to set adjustable limits at the output in cases when the sensor signal goes above or below its range. There are 16 levels for over-scale limit adjustment (4-bit DAC) and 8 levels for the under-scale (3-bit DAC). XTR108 SBOS187C www.ti.com 9 FIGURE 2. XTR108 Internal Block Diagram. www.ti.com RTD RCM V/I-5 V/I-4 V/I-3 V/I-2 V/I-1 V/I-0 RZ1 RZ2 RZ3 RZ4 RZ5 OPA OUT 1 Multiplexer 10 XTR108 SBOS187C 2 Σ OPA –IN 0.01µF CFILT PGA ILIN DAC IREF DAC OPA +IN 15.8kΩ RLIN CS2 12.1kΩ RSET IIN OSC RVI 6.34kΩ VOUT SDIO SCLK SPI and Control Circuits Linearization Circuit Zero DAC CS1 2.5kΩ 51Ω Output Current Amplifier Sub-Regulator Driver XTR108 Voltage Reference REFIN IRET IO VS VGate CGATE REFOUT CREG 4-20mA CLOOP – + RLOAD Loop Supply OVERALL PROGRAM COARSE DAC FINE DAC VOLTAGE REFERRED TO VO PIN WITH RESPECT TO IRET CURRENT REFERRED TO IOUT PIN VZERO = VZ PROGRAM + VZ COARSE + VZ FINE IZERO = IZ PROGRAM + IZ COARSE + IZ FINE V Z PROGRAM = V Z COARSE = V Z FINE = 3.5V REF 8 I Z PROGRAM = V REF N13 • 80 4 I Z COARSE = V REF N12 • 80 64 I Z FINE = 175V REF 8R VI 5V REF N13 • 8R VI 4 5V REF N12 • 8R VI 64 NOTE: N13 and N12 are assigned decimal values of registers 13 and 12, respectively. TABLE II. Equations for Calculating Zero Output. The circuit is designed for compliance with NAMUR NE43 recommendation for sensor interfaces. The limit levels are listed in Tables VII and VIII. Because of the large step sizes, units that use this feature should be checked if the value is critical. The under-scale limit circuit will override the Zero DAC level if it is set lower and there is not enough sensor offset at the PGA input. It may be necessary to disable limiting if the XTR108 is used in applications other than a 4-20mA transmitter, where the PGA output is between 0.5V and 4.5V. SENSOR FAULT DETECTION CIRCUIT To detect sensor burnout and/or short, a set of four comparators is connected to the inputs of the PGA. If any of the inputs are taken outside of the PGA’s common-mode range, the corresponding comparator sets a sensor fault flag that causes the PGA output to go either to the upper or lower error limit. The state of the fault condition can be read in the digital form from register 3. The direction of the analog output is set according to the “Alarm Configuration Register” (see Table X). The level of the output is produced as follows: if the over-scale/under-scale limiting is enabled, the error levels are: over-scale limit +2LSBs of the over-scale DAC, about 1mA referred to IOUT or 0.125V referred to VO, of under-scale limit –2LSBs of the under-scale DAC, about 0.4mA referred to IOUT or 0.05V referred to VO. If the overscale/under-scale limiting is disabled, the PGA output voltage will go to within 150mV of either positive or negative supply (VS or IRET), depending on the alarm configuration bit corresponding to the error condition. matched internal resistors determines a current gain of this block. Note that the IOUT pin is always biased below the substrate potential. EXCITATION CURRENT DACS AND RSET RESISTOR Two matched adjustable reference current sources are available for sensor excitation. The defining equations are given in Table III. Both current sources are controlled simultaneously by the coarse and fine DACs with a pedestal. The external resistor RSET is used to convert the REF voltage into the reference current for the sensor excitation DACs. The total current output of the DACs is split, producing two references: IREF1 and IREF2. Both of the current references match very closely over the full adjustment range without mismatched differential steps. Both current reference outputs must be within the compliance range, i.e.: one reference cannot be floated since it will change the value of the other current source. The recommended value of RSET is 12.1kΩ for use with 100Ω RTD sensors. This generates IREF1, 2 = 492µA currents when both coarse and fine DACs are set to zero. The value of the RSET resistor can be increased if lower reference currents are required, i.e.: for 1000Ω RTD or a bridge sensor. REFERENCE CURRENT OVERALL PROGRAM COARSE DAC OUTPUT CURRENT AMPLIFIER + RVI RESISTOR To produce the 4-20mA output, the XTR108 uses a current amplifier with a fixed gain of 50A/A. The voltage from the PGA is converted to current by the external resistor, RVI. Pin IRET, the common potential of the circuit (substrate and local ground), is connected to the output and inverting input of the amplifier. This allows collecting all external and internal supply currents, sensor return current, and leakage currents from the different parts of the system and accounting for them in the output current. The current from RVI flows into the pin IIN that is connected to the noninverting input and therefore, is at ground potential as well. The ratio of two FINE DAC IREF PROGRAM = IREF COARSE = IREF FINE = 5V REF R SET V REF N11 • 64 R SET N V REF • 10 R SET 1024 NOTE: N11 and N10 are the decimal values of registers 11 and 10, respectively. TABLE III. Equations for Calculating the Values of Each Reference Current. Similar to the Zero DACs, the outputs of the fine and coarse DAC are summed together with the pedestal IREF PROGRAM. Each of the excitation DACs has 8-bit resolution (256 steps) with 4-bit overlap between the coarse and the fine. This XTR108 SBOS187C IREF1, 2 = IREF PROGRAM + IREF COARSE + IREF FINE www.ti.com 11 means that one LSB of the coarse DAC is equal to 16 fine LSBs, and the full-scale range of the fine DAC is equal to 16 coarse LSBs. This effectively produces 12-bit adjustment resolution. This allows the user to set pre-calculated values before the calibration, using the coarse DAC only and adjust the reference current output level with the fine DAC during the calibration process. LINEARIZATION CIRCUIT AND RLIN RESISTOR The XTR108 incorporates circuitry for correcting a secondorder sensor nonlinearity. A current proportional to the voltage at the input of the PGA is added to the sensor excitation. The RLIN resistor is used to convert this voltage into current. By appropriately scaling this current using the linearization DAC, parabolic sensor nonlinearity can be improved by up to a 40:1 ratio, as shown in Figure 3. The linearization coefficient (ratio of the reference current change to the input voltage) is expressed in µA/mV as follows: G LIN = ∆I REF N14 • V IN 16 • R LIN where N14 is the decimal value from register 14. The recommended value of the resistor is 15.8kΩ, for use with 100Ω RTD sensors. This value produces a full-scale linearization coefficient of about 1mA/V. Please see the section below on using the XTR108 with an RTD temperature sensor. If the sensor excitation is scaled down by increasing the value of RSET, the value of RLIN should be scaled proportionally. 5 Nonlinearity (%) 4 3 2 1 Uncorrected RTD Nonlinearity Corrected Nonlinearity 0 n-channel depletion-mode MOS transistor and three capacitors, see Figure 2. A number of third-party suppliers make n-channel depletion-mode MOSFETs. A list of devices tested by Texas Instruments, Inc. is shown in Table IV with the capacitor values recommended for those devices. MANUFACTURER MOSFET MODEL CGATE VALUE Supertex DN2535, DN2540 DN3535, DN3525 220pF 1000pF Siliconix ND2012, ND2020 220pF Infineon BSP149 1000pF TABLE IV. Recommended Gate Capacitor Values For Selected MOSFETs. The capacitors CLOOP (0.01µF), CREG (2.2µF), and CGATE are required for the regulator loop stability and supply bypass. They should be placed in close proximity to the XTR108 on the PCB. An additional 1µF capacitor may be used to bypass the supply of an EEPROM chip. If a MOSFET other than those listed in Table IV is used, the value of CGATE should be adjusted such that there is no overshoot of VS during power-up and supply glitches. Any VS overshoot above 7.5V may damage the XTR108 or deteriorate its performance. LOOP VOLTAGE The XTR108 transmitter minimum loop voltage can somewhat be effected by the choice of the external MOSFET. The devices are tested to 7.5V compliance with Supertex DN2540; choosing other MOSFETs can change this value slightly. The maximum loop voltage is limited by the power dissipation on the MOSFET as well as its breakdown voltage. Possible ambient temperatures and the power dissipation should be taken into account when selecting the MOSFET package. The external MOSFET can dissipate a considerable amount of power when running at high loop supply. For example, if VLOOP = 24V and IOUT = 20mA, the DC power dissipated by the MOSFET is: PMOSFET = IOUT (VLOOP – VS) = 380mΩ FIGURE 3. Pt100 Nonlinearity Correction Using the XTR108. For a SOT-89 package soldered on an FR5 board, this will cause a 30°C rise in the temperature. The power dissipation gets significantly higher when the circuit is driven into an over-scale condition. Therefore, special attention should be paid to removing the heat from the MOSFET, especially with small-footprint packages such as SOT-89 and TO-92. Please follow manufacturer’s recommendations about the package thermal characteristics and board mounting. SUB-REGULATOR WITH EXTERNAL MOSFET UNCOMMITTED OP AMP The XTR108 is manufactured using a low-voltage CMOS process with maximum supply voltage limited to 5.5V. For applications in a 4-20mA current loop, a special sub-regulator circuit is incorporated in the device that requires an external For added flexibility in various applications, the XTR108 has an on-chip uncommitted operational amplifier. The op amp has rail-to-rail output range. The input range extends to IRET potential. –1 –200°C +850°C Process Temperature (°C) 12 XTR108 www.ti.com SBOS187C The uncommitted amplifier can be used for a variety of purposes, such as voltage sensor excitation, buffering the REFOUT pin, four-wire RTD connection, or sensing the bridge voltage for temperature compensation. CONTROL REGISTERS POWER-GOOD/POWER-ON RESET DESCRIPTION OF CONTROL REGISTERS In case of a supply brownout condition or short interruption, the XTR108 power-good detection circuit will initiate a chip reset that will cause all registers to be reset to 0’s and a cycle of EEPROM read to begin. The circuit generates a reset if VS droops below 1.5V and then recovers up to the normal level. Address = 0: Control Register 1 If the RST bit is set to ‘1’ in a write operation, all the registers in the XTR108 will be returned to their power-on reset condition. The RST bit will always read as a ‘0’. CSE, the checksum error bit, is read only and will be set to ‘1’ if a checksum error has been detected. This bit is cleared by a reset operation or by detection of a valid checksum. The remaining bits are reserved and must be set to ‘0’. Address = 3: Fault Status Register This register is a read-only register. If the input voltage to the PGA exceeds the linear range of operation, the XTR108 will indicate this error condition (typically caused by a sensor fault) by setting the under-scale or over-scale error level depending on the state of the Alarm Configuration Register (Address = 7). Information on the nature of the fault may be read in digital form from this register, as shown in Table VI. The remaining bits will be set to ‘0’. Table V shows the registers that control the analog functions of the XTR108. USING THE XTR108 IN VOLTAGE OUTPUT MODE The XTR108 can be used not only in 4-20mA current loops, but also as a low-power, single-supply, "smart" sensorconditioning chip with voltage output. In this mode, the I RET pin must be connected below ground (–200mV < IRET < –25mV). This negative voltage is required to overcome the input offset voltage of the output current amplifier and prevent it from turning on and drawing excessive current. An application circuit that generates this negative voltage using the XTR108 clock output and a simple charge pump is shown in the application section. The sub-regulator with an external MOSFET may or may not be used. If the circuit is powered externally, the supply voltage must be in the range of 5V ±0.5V. BIT F0 F1 F2 F3 FAULT MODE Negative Input Exceeds Positive Limit. Negative Input Exceeds Negative Limit. Positive Input Exceeds Positive Limit. Positive Input Exceeds Negative Limit. TABLE VI. Register 3, Fault Status Register. Instruction D7 D6 D5 D4 D3 D2 D1 D0 Read/Write R/W 0 0 0 A3 A2 A1 A0 Read/Write Operation EEPROM Mode 0 1 1 1 1 1 1 1 Assert CS2 Ignore Serial Data/A Data Bit D7 D6 D5 D4 D3 D2 D1 D0 RST 0 0 0 0 FD 0 AC7 0 0 FG7 CG7 FZ7 CZ7 L7 S7 CSE 0 0 0 0 US2 0 AC6 VP2 IB2 FG6 CG6 FZ6 CZ6 L6 S6 0 0 0 0 0 US1 0 AC5 VP1 IB1 FG5 CG5 FZ5 CZ5 L5 S5 0 0 0 0 0 US0 0 AC4 VP0 IB0 FG4 CG4 FZ4 CZ4 L4 S4 0 0 0 F3 0 OS3 0 AC3 0 0 FG3 CG3 FZ3 CZ3 L3 S3 0 0 0 F2 0 OS2 G2 AC2 VN2 IA2 FG2 CG2 FZ2 CZ2 L2 S2 0 0 0 F1 0 OS1 G1 AC1 VN1 IA1 FG1 CG1 FZ1 CZ1 L1 S1 0 0 0 F0 RBD OS0 G0 AC0 VN0 IA0 FG0 CG0 FZ0 CZ0 L0 S0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Read/Write Reserved Reserved Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Control Register 1 Fault Status Register Control Register 2 Over/Under-Scale Register PGA Gain Alarm Config. Register PGA Input Config. Register IREF Output Config. Register Fine IREF Adjust Register Coarse IREF Adjust Register Fine Zero Adjust Register Coarse Zero Adjust Register Linearization Adjust Register Checksum Register TABLE V. Analog Control Registers. XTR108 SBOS187C www.ti.com 13 Address = 4: Control Register 2 If the RBD bit is set to ‘1’, the automatic read-back from the EEPROM will be disabled after a valid checksum byte is received in Register 15. This bit is read from the EEPROM during a read-back by the XTR108 and allows the user to program the XTR108 to read the EEPROM data once (instead of continuously), and then disables the automatic read-back function. The XTR108 will continuously read the EEPROM if RBD is set to ‘0’. The remaining bits in this register must be set to ‘0’. Address = 5: Over- and Under-Scale Register This register sets the magnitude of the over-scale current limit and the magnitude of the under-scale current limit. The threshold level, as shown in Table VII and VIII, is the normal analog (no error condition) output limit. If an input voltage to the PGA exceeds the linear operation range, the output will be programmed to either the over-scale error level or the under-scale error level. The over-scale error level is 10mA greater than the over-scale threshold level. The under-scale error level is 0.4mA less than the underscale threshold level. The FD bit will disable the over-scale and under-scale limiting function as well as the PGA fault indication error levels. Address = 6: PGA Gain Register This register sets the gain of the programmable-gain amplifier. The unused bits must always be set to ‘0’. The gain step to register content is given in Table IX. Address = 7: Alarm Configuration Register This register configures whether the XTR108 will go overscale or under-scale for various detected fault conditions at the input of the PGA. Table X defines each of the bits. If a bit corresponding to the particular error is set to ‘1’, the output will go over-scale when it occurs and if a bit corresponding to the particular error is set to ‘0’, the output will go under-scale. OS3 OS2 OS1 OS0 VO OVER-SCALE THRESHOLD IO OVER-SCALE THRESHOLD RVI = 6.34kΩ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2.625V 2.6875V 2.75V 2.8125V 2.875V 2.9375V 3.0V 3.0625V 3.125V 3.1875V 3.25V 3.3125V 3.375V 3.4375V 3.5V 3.5625V 20.7mA 21.2mA 21.7mA 22.2mA 22.7mA 23.2mA 23.7mA 24.2mA 24.6mA 25.1mA 25.6mA 26.1mA 26.6mA 27.1mA 27.6mA 28.1mA TABLE VII. Register 5, Over-Scale Threshold. US2 US1 US0 VO UNDER-SCALE THRESHOLD 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 450mV 425mV 400mV 375mV 350mV 325mV 300mV 275mV IO UNDER-SCALE THRESHOLD RVI = 6.34kΩ 3.55mA 3.35mA 3.15mA 2.96mA 2.76mA 2.56mA 2.37mA 2.17mA TABLE VIII. Register 5, Under-Scale Threshold. G2 G1 G0 PGA VOLTAGE GAIN 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 6.25V/V 12.5V/V 25V/V 50V/V 100V/V 200V/V 400V/V Reserved SIGNAL PATH TRANSCONDUCTANCE RVI = 6.34kΩ 49mA/V 99mA/V 197mA/V 394mA/V 789mA/V 1577mA/V 3155mA/V TABLE IX. Register 6, PGA Gains. BIT AC AC AC AC AC AC AC AC # 7 h l 6 l h 5 l l 4 h h 3 n l 2 n h 1 l n 0 h n VINN VINP NOTES: ‘h’ = input exceeds positive common-mode range, ‘l’ = input exceeds negative common-mode range, and ‘n’ = input pin is within the CM range. TABLE X. Register 7, Alarm Configuration Register. Address = 8: PGA Input Configuration Register This register connects the inputs of the PGA to the various multiplexed input pins. Tables XI and XII show the relationship between register, contents, and PGA inputs. VP2 VP1 VP0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PGA POSITIVE INPUT PGA PGA PGA PGA PGA PGA VIN+ VIN+ VIN+ VIN+ VIN+ VIN+ Connected Connected Connected Connected Connected Connected Reserved Reserved to to to to to to V/ I-0 V/ I-1 V/ I-2 V/ I-3 V/ I-4 V/ I-5 TABLE XI. Register 8, PGA Positive Input Selection. VN2 VN1 VN0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PGA NEGATIVE INPUT PGA PGA PGA PGA PGA PGA VIN– VIN– VIN– VIN– VIN– VIN– Connected Connected Connected Connected Connected Connected Reserved Reserved to to to to to to V/ I-0 V/ I-1 V/ I-2 V/ I-3 V/ I-4 V/ I-5 TABLE XII. Register 8, PGA Negative Input Selection. 14 XTR108 www.ti.com SBOS187C Address = 9: IREF Output Configuration Register This register connects the reference currents to the various multiplexed input pins. IREF connection codes are given in Table XIII. Address = 10: Fine IREF Adjust Register This register sets the code to the 8-bit Fine DAC that adjusts the magnitude of both reference currents. The DAC output value has a bipolar range (for each reference current) and can be calculated using the equations in Table III. IA2 IA1 IA0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 IB2 IB1 IB0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 IREF CONNECTION IREF1 IREF1 IREF1 IREF1 IREF1 IREF1 Connected to Connected to Connected to Connected to Connected to Connected to Reserved Reserved V/ I-0 V/ I-1 V/ I-2 V/ I-3 V/ I-4 V/ I-5 IREF CONNECTION IREF2 IREF2 IREF2 IREF2 IREF2 IREF2 Connected to Connected to Connected to Connected to Connected to Connected to Reserved Reserved V/ I-0 V/ I-1 V/ I-2 V/ I-3 V/ I-4 V/ I-5 TABLE XIII. Register 9, IREF Output Configuration. Address = 11: Coarse IREF Adjust Register This register sets the code to the 8-bit coarse DAC that adjusts the magnitude of both reference currents. The nominal value for the reference current (both Coarse and Fine adjust set to ‘0’) is IPROGRAM • 5. See Table III for formulas. Address = 12: Fine Zero-Adjust Register This register sets the code to the 8-bit Fine DAC that adjusts the magnitude of the zero output currents. Equations are given in Table II. Negative numbers are in Binary Two’s Complement. Address = 13: Coarse Zero-Adjust Register This register sets the code to the 8-bit Coarse DAC that adjusts the magnitude of zero-output current. See Table II for equations. Negative numbers are given in Binary Two’s Complement. Address = 14: Linearization Adjust Register This register sets the code to the 8-bit DAC that adjusts the magnitude of the linearization feedback current. Value is unipolar to 255. Address = 15: Checksum Register This register contains the checksum byte that is used to validate the data read from the EEPROM. If a write occurs to this register, and the checksum is invalid, an error condition will set (CSE = ‘1’). If the checksum is valid, the error condition will be cleared (CSE = ‘0’). If a checksum error is detected, the XTR108 will program itself to the lowest under-scale error level. SERIAL INTERFACE PROTOCOL The XTR108 has an SPI-compatible serial interface. The data is transmitted MSB first in 8-bit bytes. The first byte is an instruction byte in which the first bit is a read/write flag (‘0’ = write, ‘1’ = read), the lowest four bits are the register address and the remaining three bits are set to zero. The second, and all successive bytes, are data. During a write operation, the successive data bytes are written to successive registers within the XTR108. The address is automatically incremented at the completion of each byte. The SDIO line is always an input during a write operation. During a read operation, the SDIO line becomes an output during the second and successive bytes. As in the case of a write operation, the address is automatically incremented at the completion of each byte. Each communication transaction is terminated when CS1 is de-asserted. The CS2 line remains de-asserted during read and write operations. The calibration controller also needs to be able to read from and write to the external EEPROM device. This is accomplished by sending a special instruction code (0x7F) to the XTR108. At the completion of this instruction byte, the XTR108 will assert the CS2 line to select the EEPROM device and ignore all data on the SDIO line until CS1 is deasserted and reasserted. The CS2 line will also be deasserted when CS1 is de-asserted. This allows the calibration controller to communicate with the EEPROM device directly. The calibration controller then has control over the timing required to write data to the EEPROM device. In normal operation, the XTR108 reads data from the EEPROM device to retrieve calibration coefficients. This is accomplished by the read-back controller on the XTR108. The readback controller is clocked by an on-chip oscillator and provides stimulus to the EEPROM device over the SCLK, SDIO, and CS2 lines to perform the read operation, while simultaneously providing stimulus to the serial interface controller in the XTR108. The read-back controller defaults to being active when the XTR108 is powered on and will be continuously active unless disabled. (It will start a new read operation as soon as the previous operation is completed, see Figure 4.) A control bit (RBD) is provided to allow the XTR108 to read the EEPROM once and then stop. The read-back controller will abort a read-back operation when the CS1 line is asserted. The calibration controller must wait at least 40µs after setting the CS1 line LOW before the first rising edge of SCLK occurs. For an external controller to write directly to the XTR108 (sensor calibration operation) or load data into the EEPROM, it is necessary to interrupt the default read-back mode. For both of these modes, the SCLK direction must be reversed. See Figure 5 for the timing of this operation. First, the SCLK line must be pulled LOW for at least 20ns (t10). Then CS1 is set LOW. The XTR108 will set DIO to a tri-state within 20ns (t13) and CS2 HIGH within 50ns (t12). After a delay of at least 40µs (t11), the external system will start communication with a rising edge on SCLK. XTR108 SBOS187C www.ti.com 15 Hi-Z SCLK t8 t8 DIO 0 0 0 t9 0 0 0 1 1 0 0 0 Instruction/Address to EEPROM 0 0 1 0 0 Data from EEPROM CS2 FIGURE 4. Timing Diagram for the XTR108 Continuous Readback Cycle. (See Table XIV for timing key.) SCLK t10 t11 DIO t13 CS2 t12 CS1 FIGURE 5. Interrupting an XTR108 EEPROM Readback Cycle. (See Table XIV for timing key.) As long as CS1 is held LOW, the external system can write to the EEPROM. See Figure 7 for this timing. Releasing CS1 will allow the XTR108 to resume in the read-back mode. For interactive calibration operations, the first command to the XTR108 should set bit 0, Register 4 (RBD). This will disable the read-back mode. It will be possible to write to the various registers and cycle CS1. If RBD is not set, then as soon as CS1 is released, the XTR108 will read the EEPROM 16 contents which will overwrite the data just loaded. Figure 6 shows read and write timing. To be compatible with SPI EEPROM devices, the XTR108 latches input data on the rising edge of SCLK. Output data transitions on the falling edge of SCLK. All serial interface transactions must be framed by CS1. CS1 must be asserted to start an operation, and it must be de-asserted to terminate an operation. XTR108 www.ti.com SBOS187C CS1 t7 t1 t5 SCLK t2 t2 t3 t4 t6 DIO FIGURE 6. Timing Diagram for Writing to and Reading From the XTR108 with EEPROM Readback Disabled. (See Table XIV for timing key.) SCLK DIO 0 1 1 1 1 1 1 1 Instruction to XTR108 Data to/from EEPROM CS1 t14 CS2 FIGURE 7. Writing to and Reading From the EEPROM Device From External Controller. (See Table XIV for timing key.) SPEC DESCRIPTION MIN t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 CS1 LOW to SCLK Rising Setup Time SCLK Pulse Width HIGH and LOW DIO to SCLK Rising Setup Time DIO to SCLK Rising Hold Time CS1 to Last SCLK Rising Hold Time SCLK Falling to DIO Driven Valid by XTR108 CS1 to DIO Tri-State SCLK Pulse Width During EEPROM Readback CS2 HIGH Between Successive EEPROM Readbacks SCLK Driven LOW Before CS1 LOW When Interrupting XTR108 Readback from EEPROM CS1 LOW to SCLK Rising Setup Time When Interrupting XTR108 EEPROM Readback CS1 Falling to CS2 HIGH CS1 Falling to DIO Tri-State CS1 Rising to CS2 HIGH XTR108 EEPROM Update Rate in Continuous Readback Mode 2.0 100 20 20 20 0 0 TYP MAX 50 20 5 10 20 40 0 0 0 50 20 20 0.9 UNITS ns ns ns ns ns ns ns us us ns us ns ns ns kHz TABLE XIV. Timing Diagram Key. XTR108 SBOS187C www.ti.com 17 EEPROM DATA STORAGE The XTR108 automatically reads data from an SPI-compatible EEPROM device. The models 25C040 from MicroChip and the AT25010 from Atmel have been tested and are known to work. Equivalent devices with an SPI interface can be expected to work. The XTR108 will read data from addresses 4 through 15 of the EEPROM. The address in the EEPROM is the same as the address for the corresponding data in the XTR108. The XTR108 will not write data to the EEPROM. The external calibration controller is responsible for writing data to the EEPROM. CHECKSUM FUNCTION To validate the data from the EEPROM device, the XTR108 calculates a checksum on the incoming serial-data stream during each write operation. The value written to the EEPROM that will be transferred to register 15 during an EEPROM read operation must be such that the sum of the data in registers 4 through 15 totals 0xFF (255). The sum is calculated by performing an add/accumulate function on all of the data bytes of a read operation. An end-around carry is used during the add/accumulate operation. If a carry-out was generated in the previous add operation, it is used as a carry-in for the next add operation for the checksum operation. The following code shows how the value of register 15 could be calculated: Sum = 0 FOR Index = 4 TO 14 Sum = Sum + Data [Index] IF Sum > 255 THEN Sum = Sum – 255 NEXT Index Data [15] = 255 – Sum For a test or calibration operation, it may be necessary to write to a few select registers. This may be accomplished without writing to register 15. To accomplish this, write to the necessary registers and release CS1. There is no need to update register 15. If the command is to disable the automatic read-back function by setting the RDB bit in register 4, it is necessary to rewrite the entire register set data with a correct checksum value in register 15. The automatic read-back mode will be disabled upon successful checksum operation. The checksum error flag is also cleared when the XTR108 is reset (i.e.: at power ON). Write operations that do not write to the checksum register will have no effect on the checksum error flag. By locating the checksum register after the last configuration register and including the checksum register in the EEPROM read operation, the data is validated by the checksum function. EEPROM DATA SECURITY Since the data in the EEPROM directly affects the analog output of the XTR108, the data in the EEPROM needs to be secure from accidental write operations. SPI EEPROM devices have a write-protect function on one of the pins. An additional connection to the calibration controller would be required if the write-protect pin is used to prevent accidental write operations. SPI EEPROM devices require a special 18 write enable instruction to be executed to write data to the EEPROM. It is unlikely that this would accidentally be written to the EEPROM device and then be followed by a valid write operation. Further security can be obtained by using an SPI EEPROM device that has internal write-protect control bits. These bits are nonvolatile and must be cleared before write operations are allowed. SURGE PROTECTION Remote connections to current transmitters can sometimes be subjected to voltage surges. It is prudent to limit the maximum surge voltage applied to the XTR108 with various zener diodes and surge-clamping diodes specially designed for this purpose. Since the maximum voltage on the XTR108 loop is limited by the external MOSFET breakdown voltage, usually more than 200V, the requirement to the clamping devices are not very strict. For example, a 50V protection diode will assure proper transmitter operation at normal loop voltages without significant leakage yet provide an appropriate level of protection against voltage surges. In case of prolonged (seconds and longer) overvoltage, lower voltage clamps may be used to limit the power dissipation on the transmitter. Most surge-protection zener diodes have a diode characteristic in the forward direction that will conduct excessive current, possibly damaging receiving-side circuitry if the loop connections are reversed. If a surge protection diode is used, a series diode or diode bridge should be used for protection against reversed connections. REVERSE-VOLTAGE PROTECTION The XTR108’s low compliance rating (7.5V) permits the use of various voltage protection methods without compromising operating range. Figure 8 shows a diode bridge circuit which allows normal operation even when the voltage connection lines are reversed. The bridge causes a two diode drop (approximately 1.4V) loss in loop supply voltage. This results in a compliance voltage of approximately 9V—satisfactory for most applications. If 1.4V drop in loop supply is too much, a diode can be inserted in series with the loop supply voltage and the V+ pin. This protects against reverse output connection lines with only a 0.7V loss in loop supply voltage. RADIO FREQUENCY INTERFERENCE The long wire lengths of current loops invite radio frequency interference. RF energy can be rectified by the sensitive input circuitry of the XTR108 causing errors. This generally appears as an unstable output current that varies with the position of loop supply or input wiring. If the RTD sensor is remotely located, the interference may enter at the input terminals. For integrated transmitter assemblies with short connection to the sensor, the interference more likely comes from the current loop connections. Bypass capacitors on the input reduce or eliminate this input interference. Connect these bypass capacitors to the IRET terminal, see Figure 9. Although the DC voltage at the IRET terminal is not equal to 0V (at the loop supply, VPS) this circuit point can be considered the transmitter’s “ground.” The 0.01µF capacitor connected between VLOOP and IO may help minimize output interference. XTR108 www.ti.com SBOS187C NOTE: (1) Zener Diode 36V: 1N4753A or General Semiconductor TransorbTM 1N6286A. Use lower voltage zener diodes with loop power supply voltages less than 30V for increased protection. See “Over-Voltage Surge Protection.” 10 V+ 0.01µF XTR108 14 D1(1) 1N4148 Diodes 13 RL Maximum VPS must be less than minimum voltage rating of zener diode. VPS IO 11 IRET 12 The diode bridge causes a 1.4V loss in loop supply voltage. FIGURE 8. Reverse Voltage and Over-Voltage Protection. RTD APPLICATION The values to be entered into the DAC control registers are given by the formulas in Table XV. EXCITATION CURRENT IREF 1) For a chosen temperature range, using an industry-standard polynomial set as shown in Table XVI, calculate RTD values at min, max, and the middle temperatures: (R MIN , R MAX , and R MID ) 2) Calculate a relative nonlinearity BV using the RTD values from above: Coarse DAC code  64 • IREFR SET  − 320 N11 = round  VREF   BV = Fine DAC Code  1024 • IREFR SET  − 5120 − 16 • N11 N10 = round  VREF   3) Pick an external zero resistor, RZ closest to RMIN. Selecting RZ greater than RMIN will cause a voltage offset that must be corrected by the PGA zero adjustment. 4) Calculate the linearization coefficient:: ZERO OUTPUT IZERO Coarse DAC Code  32 • I ZEROR VI  − 140 N13 = round   5 • VREF  G LIN = Fine DAC Code  512 • I ZEROR VI  − 2240 − 16 • N13  N12 = round  5 • VREF   Lin DAC Code N14 = round (16 • GLINR LIN ) TABLE XV. Equations for DAC Code Calculation. This procedure allows calculation of the parameters needed to calculate the DAC codes for an RTD sensors application. [ ] 1 + + 1 0 850 At B for C t ° < < °C [ ] R t = R O 1 + At + B12 + C (t − 100°C)t 3 for − 200°C < t < 0°C Rt = RO 2 (0.5 + BV ) R MAX 2 BV – (0.5 – BV ) R MIN – 2 BV R Z If the value of GLIN is larger than GLIN MAX = (16/ RLIN) the external resistor RLIN has to be changed. If GLIN is significantly smaller (> 10 times) than GLIN MAX, the RLIN value should be increased to minimize the DAC quantization errors. For 100Ω RTD sensors the required linearization coefficients are in the range from 0.3 to 0.6 mA/V (1/kΩ) for all measurement ranges. Therefore an external RLIN value of 15.8kΩ is good setting the full-scale GLIN MAX ~ = 1mA/V. For 1kΩ RTD’s the RLIN should be increased proportionally. LINEARIZATION COEFFICIENT GLIN S tan dard RTD Polynomials : R MAX + R MIN 2 R MAX – R MIN R MID – 5) Choose the output zero and full-scale level values, for instance: IOUTMIN = 4mA, IOUTMAX = 20mA. A = 3.9083e − 3 B = −5.775e − 7 C = −4.183e − 12 R O − base RTD value at 0°C (100Ω or 1kΩ) TABLE XVI. Standard RTD Descriptive Equations. XTR108 SBOS187C www.ti.com 19 6) Choose PGA gain from the available list and calculate the initial excitation current using: I REF1,2 = (I OUTMAX ) ( Step 3. • Calculate corrections using the following equations: ) – I OUTMIN • 1 – G LIN ( R MAX – R Z ) • R VI 50 • A PGA • ( R MAX – R MIN ) I REFA = R Z A = R MIN + Important: the PGA gain value should be chosen such that the IREF value is within ±35% of 5VREF/RSET to allow room for calibration adjustments without having to go to another span step. G LINA = 7) The required DAC zero offset current value can be calculated by: I ZERO = I OUTMIN – (I MEAS2 – I MEAS1 ) R VI 50 A PGA ( R MAX – R MIN ) IREFB = (I ZERO – I MEAS1 )R VI 50 A PGA I REFA 2 BV (0.5 + BV )R MAX – (0.5 – BV )R MIN – 2BV R ZA (IOUTMAX – I OUTMIN ) • (1 – GLIN _ A (RMAX – RZ A )) • RVI ( 50 • APGA • (RMAX – RMIN ) ) ( ∆IREF = IREF – IREFA + IREF – IREFB 50 • A PGA I REF ( R MIN – R Z ) Adjusted IREF fine DAC Code : N10 A = N10 R VI Example: Measurement Range: TMIN = –20°C, TMAX = 50°C; 100Ω RTD. 1) RMIN = 92.16Ω, RMAX = 119.40Ω, RMID = 105.85Ω; ∆IZERO = IOUTMIN – IZERO – )  1024 • ∆IREFR SET  + round   VREF   ( 50 • APGAIREFB RMIN – R Z A ) R VI  512 • ∆IZEROR VI  Adjusted IZERO fine DAC Code : N12 A = N12 + round   5 • VREF   2) Sensor relative nonlinearity: BV = 0.0026; 3) Choosing RZ = 90.9Ω (closest to RMIN 2% value); 4) Linearization coefficient: GLIN = 0.3804mA/V; 5) 4-20mA output span; 6) PGA voltage gain APGA = 200, sensor excitation current IREF1,2 = 368.39mA; 7) Zero offset DAC: IZERO = 3.268mA CALIBRATION PROCEDURE FOR RTD SENSORS Step 1 Initial parameters calculation. • Using the procedure above, compute IREF, APGA, IZERO, and GLIN based on TMIN, TMAX, and nominal values of RZ, RSET, and RVI. Use the equation in Table XV to calculate the DAC register values. • Configure the input MUX, write PGA gain, reference, and offset DAC registers of the XTR108 with calculated settings. Note: write GLIN = 0 (no linearization) to XTR108 at this step; Step 2 Measurement. • Set RTD resistor value (or oven temperature) to minimum scale, measure output signal IMEAS1; • Set RTD resistor value (or oven temperature) to maximum scale, measure output signal IMEAS2; 20 This takes into account resistor value deviations, all offsets and gain errors of the coarse DACs and PGA. If the adjusted abs(N12A) > 128 or abs(N10A) > 128, adjust the coarse DAC first, then recalculate the fine DAC value; • Update all the DAC register value, including linearization DAC. Step 4 (optional). Measure output signal IMEAS3 with maximum RTD value still connected to the input from step 2; Step 5 (optional). Compute GLIN correction and update LinDAC register; Step 6 (optional). Make verification measurements at min- and max-input signal; If linearity check is needed: make a measurement at mid-scale; write EEPROM data. Step 7. Set the desired over-scale, under-scale signal limits and sensor burnout indication configuration. Verify and adjust the over-scale and under-scale levels by applying the positive and negative overdriving differential signals to the PGA inputs. XTR108 www.ti.com SBOS187C SAMPLE ERROR ANALYSIS Table XVII shows a detailed computation of the error accumulation. The sample error budget is based on a typical RTD circuit (Pt100, 200°C measurement span). Note that these calculations are based on typical characteristics where no maximum or minimum characteristic is available. The assumption is made that all errors are positive and additive. As the various error sources are independent, a closer approximation to nominal performance might be to accumulate the errors with a root-sum-square calculation. SAMPLE ERROR CALCULATION RTD value at 4mA Output (RRTD MIN) 100Ω: RTD Measurement Range 200°C; Ambient Temperature Range (∆TA) 20°C; Supply Voltage Change (∆V+) 5V; CommonMode Voltage Change (∆CM) 0.1V. Chosen XTR108 parameters: PGIA gain = 50; IREF = 518.9µA; Full-scale VIN = 40mW. Register 06 = 0H03; Register 11 = 0H11; Register 13 = 0HFC; Register 14 = 0H70. ERROR SOURCE INPUT Input Offset Voltage vs Common Mode Input Bias Current Input Offset Current ERROR EQUATION SAMPLE ERROR CALCULATION Note (1) CMRR • ∆CM/(VIN MAX) • 106 Note (1) Note (1) 5µV/V • 0.1V/0.04V • 106 Total Input Error: EXCITATION Current Reference Accuracy vs Common Mode Current Reference Matching DAC Resolution and Linearity GAIN Span Nonlinearity Note (1) ∆CM/ROUT • RRTD MIN/(VIN MAX) • 106 Note (1) 1LSBFINE • RRTD MIN/(VIN MAX) • 106 0.1V/100MΩ • 100Ω/40mV 96nA • 100Ω/40mV • 106 Total Excitation Error: Note (1) Nonlinearity (%)/100% • 106 CALIBRATED ERROR (ppm of Full Scale) 0 12.5 0 0 12.5 0 2.5 240 242.5 0.01%/100% • 106 Total Gain Error: 0 100 100 Note (2) 2 • 1.8µA/16mA • 106 Total Output Error: 0 6 225 231 OUTPUT Zero Output vs Supply DAC Resolution and Linearity Note (1) (IZERO vs V+) • ∆V+/16mA • 106 2LSBFINE/16mA • 106 DRIFT (∆TA = 20°C) Input Offset Voltage Current Reference Accuracy Current Reference Matching Span Zero Output Drift • ∆TA/(VIN MAX) • 106 Drift • ∆TA Drift • ∆TA • IREF • RRTD MIN/(VIN MAX) Drift • ∆TA Drift • ∆TA 0.02µV/°C • 20°C/40mV • 106 35ppm • 20°C 15ppm • 20°C • 518.9µA • 100/40mV 30ppm • 20°C Note (1) Total Drift Error: 10 700 390 600 250 1950 NOISE (0.1Hz to 10Hz, Typ) Input Offset Voltage Current Reference Zero Output VN/(VIN MAX) • 106 IREF Noise • RRTD MIN/(VIN MAX) • 106 IZERO Noise/16mA • 106 6µV/40mV • 106 0.015µA • 100Ω/40mV • 106 1.1µA/16mA • 106 Total Noise Error: 150 37.5 68.5 256 TOTAL ERROR: 2792 (1997)(3) 0.28% (0.20%)(3) NOTES: (1) Does not contribute to the output error due to calibration. (2) All errors are referred to input unless otherwise stated. (3) Calculated as rootsum–square. TABLE XVII. Sample Error Budget Calculation. XTR108 SBOS187C www.ti.com 21 APPLICATIONS RTD CONNECTION METHODS Two-Wire Connection The simplest circuit that can be used to connect an RTD to the XTR108 is the two-wire connection shown in Figure 9. If the RTD is separated from the XTR108 by any distance the resistance of the lead wires can cause significant error in the reading. This wire resistance is noted as RLINE1 and RLINE2. If the RF filter is not required, then the PGA inputs could be taken from the same pins as are used for the current sources. Three-Wire Connection It is possible to minimize the errors caused by the lead-wire resistance by connecting the RTD, see Figure 10. Operating under the assumption that the wire connecting pin 1 to the XTR108 is the same length as the wire at pin 2, and with the current through the RTD identical to the current through RZ any error voltage caused by the lead-wire is the same on both sides. This appears as a common-mode voltage and is subtracted by the PGA. The circuit in Figure 10 also shows a scheme where one board can be optimized for a wide range of temperatures. Consider a range of applications where there are up to five different minimum temperatures. Select RZ1 through RZ5 to be optimum for each of the minimum temperatures. The configuration codes in the EEPROM can be set to select that resistor for that unique situation. Four-Wire Connection For those applications where the resistance of the lead-wires is not equal, it may be an advantage to add a precision op amp to a four-wire connection, see Figure 11. The voltage offset and drift are error terms that degrade the operation of the system. This circuit does not suffer any loss of accuracy for the resistance of the RTD lead-wires. BRIDGE SENSOR CONNECTIONS Fixed Voltage Excitation There exists a class of sensors that are best supplied with a voltage source excitation such as the bridge sensor shown in Figure 12. The excitation voltage here is given by:  R  VEX = VREF 1 + 1  R  2 Uni-Directional Linearity Control The circuit in Figure 13 shows a bridge sensor with an excitation voltage that is adjusted to linearize the response using the same algorithm as the RTD linearization. VEX = 2 • I REF R I 1kΩ 1 1kΩ RTD RZ 0.01µF 0.01µF RLINE2 Multiplexer RLINE1 IRET RCM 2 0.01µF FIGURE 9. Two-Wire RTD Connection with RF Filter at Input Terminals. 22 XTR108 www.ti.com SBOS187C R21 Equal line resistances here create a small common-mode voltage which is rejected by the XTR108. R22 R23 1 RLINE2 RLINE1 Multiplexer 2 R24 R25 RTD IRET RLINE3 3 Resistance in this line causes a small common-mode voltage which is rejected by the XTR108. RCM 0.01µF FIGURE 10. Three-Wire RTD Connection with Multiple Minimum Temperature Capabilities. VS RLINE1 RLINE2 1 2 RTD RLINE3 RLINE4 3 4 Multiplexer RZ OPA277 IRET RCM 0.01µF FIGURE 11. Four-Wire RTD Connection. XTR108 SBOS187C www.ti.com 23 VREF R1 Multiplexer R2 IRET FIGURE 12. Voltage Excited Bridge with Excitation Derived from VREF. VREF Multiplexer R1 IRET FIGURE 13. Voltage Excited Bridge with Uni-Directional Linearity by Control. 24 XTR108 www.ti.com SBOS187C VOLTAGE OUTPUT MODE USING SIMPLE CURRENT PUMP In order for the voltage output mode of the XTR108 to operate properly, a negative voltage needs to be applied to the IRET pin (–200mV < IRET < –25mV). For systems without a negative supply a charge pump is an easy way to generate this voltage. Figure 14 shows a simple and inexpensive way to build this charge pump using two resistors, two capacitors, and two diodes (in an SOT package). The charge pump uses the clock signal from the XTR108 SCLK pin to operate; consequently, the XTR108 must be in continuous EEPROM read mode (register 4, bit 0). Figure 15 shows the typical output of this circuit (–50mV dc). VOUT = −50mV BAV99 OPA –IN OPA +IN CS1 CS2 36.5kΩ 1nF SDIO SCLK 30kΩ 330pF XTR108 SPI and Control Circuits OPA OUT REFIN OSC Σ Voltage Reference REFOUT IREF DAC +5V ILIN DAC Sub-Regulator Driver 2 −200mV < VOA+ < −25mV Zero DAC V/I-0 V/I-3 V/I-4 Multiplexer V/I-1 V/I-2 DSUB PGA Q1 Output Current Amplifier IQ1 = 0mA 0mV V/I-5 RZ1 RZ2 RZ3 RZ4 RZ5 2.5kΩ Linearization Circuit RTD CFILT RCM VS +0V 1 VGate RLIN 0.01µF 15.8kΩ 51Ω IO RSET VOUT IIN IRET 12.1kΩ VOUT FIGURE 14. Voltage Output Mode Using Simple Current Pump. XTR108 SCLK 5.0V −50mV Charge Pump Output FIGURE 15. Output Waveform of Simple Current Pump. XTR108 SBOS187C www.ti.com 25 COMMUNICATIONS WITH THE XTR108 USING A MICROCONTROLLER When communicating with the XTR108, special care must be taken to avoid getting a false clock. When CS1 is driven low, the false clock is generated because the microcontroller clock pin is in high-impedance state, which forces the clock pin to a logic high. Immediately after CS1 is driven low, the microcontroller drives the clock pin low. This sequence creates a glitch that the XTR interprets as a clock; see Figure 16. This condition can be avoided by driving the SCLK pin low just prior to applying CS1 low; see Figure 17. A series resistance should be placed between the microcontroller and the XTR108 because driving SCLK low before CS1 can create a bus contention; see Figure 18. SCLK is driven low by the microcontroller just before CS1 is driven low. SCLK is in High Z mode (Pulled high by the pull-up in the XTR108) SCLK CS1 FIGURE 17. Proper Method to Drive the XTR108 to Avoid False Clock. SCLK will be high immediately after CS1 is driven low. This is seen by the XTR108 as an false clock. XTR108 Microcontroller VCC CS1 SCLK is in High Z mode (Pulled high by the pull-up in the XTR108) 1kΩ SCLK SCLK DIO SCLK DIO CS2 CS CS1 SCLK DIO Memory FIGURE 16. False Clock. 26 FIGURE 18. Resistor Protects XTR108 and Microcontroller During Bus Contention. XTR108 www.ti.com SBOS187C PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) XTR108EA ACTIVE SSOP DBQ 24 50 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 XTR108EA XTR108EA/2K5 ACTIVE SSOP DBQ 24 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 XTR108EA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of