CAT24C01B

CAT24C01B 1K-Bit Serial EEPROM FEATURES I 2-Wire Serial Interface I 1.8 to 6.0Volt Operation I Low Power CMOS Technology I 4-Byte Page Write Buffer I Self-Timed Write Cycle with Auto-Clear I 1,000,000 Program/Erase Cycles I 100 Year Data Retention I 8-pin DIP, 8-pin SOIC, 8 pin TSSOP or 8-pin MSOP I Commercial, Industrial and Automotive Temperature Ranges I "Green" Package Options Available DESCRIPTION The CAT24C01B is a 1K-bit Serial CMOS EEPROM internally organized as 128 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT24C01B features a 4-byte page write buffer. The device operates via a 2wire serial interface and is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP or 8-pin MSOP. PIN CONFIGURATION DIP Package (P, L, GL) NC NC NC VSS 1 2 3 4 8 7 6 5 VCC TEST SCL SDA SOIC Package (J, W, GW) NC NC NC VSS 1 2 3 4 MSOP Package (R, Z, GZ) NC NC NC VSS 1 2 3 4 8 7 6 5 PIN FUNCTIONS Pin Name NC SDA SCL VCC VSS D is Ground VCC NC TEST NC SCL NC SDA VSS o c 1 2 3 4 TSSOP Package (U, Y, GY) 8 7 6 5 i t n 8 7 6 5 VCC TEST SCL SDA u n VCC VSS SDA BLOCK DIAGRAM EXTERNAL LOAD d e a P XDEC t r DOUT ACK SENSE AMPS SHIFT REGISTERS WORD ADDRESS BUFFERS COLUMN DECODERS START/STOP LOGIC VCC TEST SCL SDA CONTROL LOGIC E2PROM EEPROM DATA IN STORAGE Function No Connect Serial Data/Address Serial Clock +1.8V to +6.0V Power Supply SCL STATE COUNTERS HIGH VOLTAGE/ TIMING CONTROL TEST Test Input (GND, VCC or Floating) © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1081, Rev. E CAT24C01B ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) .................................. 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol NEND(3) TDR(3) VZAP(3) ILTH(3)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-up Min 1,000,000 100 2000 100 Max *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Units Cycles/Byte Years Volts mA Reference Test Method MIL-STD-883, Test Method 1033 D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Symbol ICC ISB (5) Parameter Power Supply Current Standby Current (VCC = 5.0V) Input Leakage Current Output Leakage Current Input Low Voltage ILI ILO VIL VIH VOL1 VOL2 CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) CIN(3) Test Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL, WP) Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range. is D Input High Voltage Output Low Voltage (VCC = 3.0V) Output Low Voltage (VCC = 1.8V) o c i t n Min –1 u n Limits Typ d e Max 3 1 10 10 0.4 0.5 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 a P t r Units mA µA µA µA V V V V Test Conditions fSCL = 100 KHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC VCC x 0.3 VCC + 0.5 VCC x 0.7 IOL = 3 mA IOL = 1.5 mA Doc. No. 1081, Rev. E 2 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C01B A.C. CHARACTERISTICS VCC = +1.8V to +6.0V, CL=1TTL Gate and 100pF (unless otherwise specified). Read & Write Cycle Limits Symbol Parameter 1.8V, 2.5V Min FSCL TI(1) tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF (1) 4.5V-5.5V Min Max 400 100 Units Max 100 100 3.5 Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time 4.7 4 4.7 4 1.2 SDA and SCL Rise Time SDA and SCL Fall Time tSU:STO tDH Stop Condition Setup Time Data Out Hold Time Power-Up Timing(1)(2) Symbol tPUR tPUW Write Cycle Limits Symbol tWR The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus is D o c Parameter Power-up to Read Operation Power-up to Write Operation i t n u n 0 250 4.7 100 4.7 1 d e 1.2 0.6 0.6 0 100 0.6 100 Max 1 1 0.6 a P 1 0.3 300 t r kHz ns µs µs µs µs µs µs ns ns µs ns µs ns 300 Units ms ms Parameter Min Typ Max 10 Units ms Write Cycle Time interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its input. Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. 1081, Rev. E CAT24C01B FUNCTIONAL DESCRIPTION The CAT24C01B uses a 2-wire data transmission protocol. The protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24C01B operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. SDA: Serial Data/Address The CAT24C01B bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wired with other open drain or open collector outputs. 2-WIRE BUS PROTOCOL The following defines the features of the 2-wire bus protocol: PIN DESCRIPTIONS SCL: Serial Clock The CAT24C01B serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin. (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. Figure 1. Bus Timing tF tLOW SCL tSU:STA tHD:STA tHIGH tLOW tR tHD:DAT SDA IN tAA SDA OUT Figure 2. Write Cycle Timing SCL SDA Figure 3. Start/Stop Timing D is SDA SCL 8TH BIT BYTE n o c i t n u n tSU:DAT tDH tWR d e a P t r tSU:STO tBUF 5020 FHD F03 ACK STOP CONDITION START CONDITION ADDRESS 5020 FHD F04 5020 FHD F05 START BIT Doc. No. 1081, Rev. E STOP BIT 4 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C01B START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24C01B monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24C01B responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8bit byte. When the CAT24C01B is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24C01B will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24C01B. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24C01B acknowledge once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information Figure 4. Acknowledge Timing is D o c START i t n 1 u n The CAT24C01B writes up to 4 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to 3 additional bytes. After each byte has been transmitted the CAT24C01B will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged. If the Master transmits more than 4 bytes prior to sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten. Once all 4 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24C01B in a single write cycle. d e a P t r Note: Catalyst Semiconductor does program all "1" data into the entire memory array prior to shipping our EEPROM products. SCL FROM MASTER 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE 5020 FHD F06 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. 1081, Rev. E CAT24C01B Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT24C01B initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the byte address for a write operation. If the CAT24C01B is still busy with the write operation, no ACK will be returned. If the CAT24C01B has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. ing with an acknowledge and by issuing a stop condition. Refer to Figure 7 for the start word address, read bit, acknowledge and data transfer sequence. Sequential Read The Sequential READ operation can be initiated after the 24C01B sends the initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24C01B will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation is terminated when the Master fails to respond with an acknowledge, thus sending the STOP condition. READ OPERATIONS The READ operation for the CAT24C01B is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Two different READ operations are possible: Byte READ and Sequential READ. It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issure a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. Byte Read The data being transmitted from the CAT24C01B is output sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24C01B address bits so that the entire memory array can be read during one operation. If more than bytes are read out, the counter will “wrap around” and continue to clock out data bytes. To initiate a read operation, the master sends a start condition followed by a seven bit word address and a read bit. The CAT24C01B responds with an acknowledge and then transmits the eight bits of data. The read operation is terminated by the master; by not respond- Figure5. Byte Write Timing Figure 6. Page Write Timing S T A R T S M S B LRA S/C BW K A C K A C K A C K S T O P P is D BUS ACTIVITY: SDA LINE BUS ACTIVITY: o c BUS ACTIVITY: SDA LINE BUS ACTIVITY: i t n S T A WORD R ADDRESS(n) T S M S B u n DATA n d e S T O P P A C K a P t r LRA S/C BW K WORD ADDRESS(n) DATA n DATA n+1 DATA n+3 Doc. No. 1081, Rev. E 6 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C01B Figure 7. Byte Read Timing S T A WORD R ADDRESS(n) T S M S B LRA S/C BW K A C K BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY CAT24C01B DATA n S T O P P Figure 8. Sequential Read Timing BUS ACTIVITY MASTER ADDRESS SDA LINE BUS ACTIVITY CAT24C01B RA /C WK DATA n A C K A C K DATA n+1 ORDERING INFORMATION Prefix CAT Device # 24C01B Optional Company ID Product Number 24C01B: 1K is D Package P: PDIP J: SOIC, JEDEC U: TSSOP R: MSOP L: PDIP (Lead-free, Halogen-free) W: SOIC (Lead-free, Halogen-free) Y: TSSOP (Lead-free, Halogen-free) Z: MSOP (Lead-free, Halogen-free) GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) GW: SOIC (Lead-free, Halogen-free, NiPdAu lead plating) GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating) GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating) o c i t n Suffix J Temperature Range Blank = Commercial (0°C to 70°C) I = Industrial (-40°C to 85°˚C) A = Automotive (-40°C to 105°C) E = Extended (-40°C to 125°C) u n I d e DATA n+2 A C K a P DATA n+x t r S T O P P -1.8 TE13 Rev A(2) Tape & Reel Operating Voltage Blank: 2.5V - 6.0V 1.8: 1.8V - 6.0V Die Revision Notes: (1) The device used in the above example is a 24C01BJI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWA). For additional information, please contact your Catalyst sales office. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. 1081, Rev. E REVISION HISTORY Date 04/17/2004 Revision Comments B Update Ordering Information Update Rev. Number 7/7/2004 08/03/05 C E Added die revision to Ordering Information Update Ordering Information Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ MiniPot™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. is D o c i t n u n d e a P t r Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.caalyst-semiconductor.com Publication #: Revison: Issue date: 1081 E 08/03/05