CAT24C164YIT3

CAT24C164 FEATURES 16-Kb CMOS Serial EEPROM, Cascadable DEVICE DESCRIPTION The CAT24C164 is a 16-Kb CMOS cascadable Serial EEPROM device organized internally as 128 pages of 16 bytes each, for a total of 2048x8 bits. The device supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non-volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. External address pins make it possible to address up to eight CAT24C164 devices on the same bus. ■ Supports Standard and Fast I2C Protocol ■ 1.8 V to 5.5 V Supply Voltage Range ■ 16-Byte Page Write Buffer ■ Hardware Write Protection for entire memory ■ Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA). ■ Low power CMOS technology ■ 1,000,000 program/erase cycles ■ 100 year data retention ■ Industrial temperature range ■ RoHS-compliant 8-lead PDIP, SOIC, TSSOP and 8-pad TDFN packages. For Ordering Information details, see page 15. PIN CONFIGURATION PDIP (L) SOIC (W) TSSOP (Y) TDFN (VP2) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA FUNCTIONAL SYMBOL VCC SCL A2, A1, A0 WP CAT24C164 SDA For the location of Pin 1, please consult the corresponding package drawing. PIN FUNCTIONS A0, A1, A2 SDA SCL WP VCC VSS Device Address Inputs Serial Data Input/Output Serial Clock Input Write Protect Input Power Supply Ground * Catalyst carries the I2C protocol under a license from the Philips Corporation. VSS © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1118, Rev. A CAT24C164 ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature Voltage on Any Pin with Respect to Ground(2) RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years -65°C to +150°C -0.5 V to +6.5 V D.C. OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. ed. Symbol ICCR ICCW ISB IL VIL VIH VOL1 VOL2 Parameter Read Current Write Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA VCC < 2.5 V, IOL = 1.0 mA Test Conditions Read, fSCL = 400 kHz Write, fSCL = 400 kHz All I/O Pins at GND or VCC Pin at GND or VCC -0.5 Min Max 1 1 1 1 VCC x 0.3 Units mA mA μA μA V V V V VCC x 0.7 VCC + 0.5 0.4 0.2 PIN IMPEDANCE CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. ed. Symbol CIN(3) CIN(3) IWP(5) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current Conditions VIN = 0 V VIN = 0 V VIN < VIH, VCC = 5.5 V VIN < VIH, VCC = 3.3 V VIN < VIH, VCC = 1.8 V VIN > VIH Note: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC = 5 V, 25°C (5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Max 8 6 200 150 100 1 Units pF pF μA Doc. No. 1118, Rev. A 2 CAT24C164 A.C. CHARACTERISTICS(1) VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C. Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF(2) tSU:STO tBUF tAA tDH Ti(2) tSU:WP tHD:WP tWR tPU(2, 3) Note: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands. Fast Min 0.6 1.3 0.6 0.6 0 100 Max 400 Units kHz μs μs μs μs μs ns 300 300 0.6 1.3 ns ns μs μs 0.9 100 100 0 2.5 μs ns ns μs μs 5 1 ms ms Parameter Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power-up to Ready Mode Min 4 4.7 4 4.7 0 250 Max 100 1000 300 4 4.7 3.5 100 100 0 2.5 5 1 A.C. TEST CONDITIONS Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 x VCC to 0.8 x VCC ≤ 50 ns 0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF (V (V © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc No. 1118, Rev. A CAT24C164 POWER-ON RESET (POR) CAT24C164 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. A CAT24C164 device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR feature protects the device against ‘brown-out’ failure following a temporary loss of power. I2C BUS PROTOCOL The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the 2wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 1). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake-up’ call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. Device Addressing The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular Slave device it is requesting. The most significant bit of the 8-bit slave address is fixed as 1. (see Figure 2). The next three significant bits (A2, A1, A0) are the device address bits and define which device or which part of the device the Master is accessing (The A1 bit must be the compliment of the A1 input pin signal). Up to eight CAT24C164 devices may be individually addressed by the system. The next three bits are used as the three most significant bits of the data word address. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 3). The Slave will also acknowledge the address byte and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 4. PIN DESCRIPTION SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device address when cascading multiple devices. When not driven, these pins are pulled LOW internally. The CAT24C164 can be made compatible with the CAT24C16 by tying A2, A1 and A0 to VSS or by leaving A2, A1 and A0 float. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. When not driven, this pin is pulled LOW internally. FUNCTIONAL DESCRIPTION The CAT24C164 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24C164 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Doc. No. 1118, Rev. A 4 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C164 Figure 1. START/STOP Conditions SCL SDA START CONDITION STOP CONDITION Figure 2. Slave Address Bits 1 A2 A1 A0 a10 a9 a8 R/W CAT24C164 Figure 3. Acknowledge Timing BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 8 9 BUS RELEASE DELAY (RECEIVER) DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK DELAY (≤ tAA) ACK SETUP (≥ tSU:DAT) Figure 4. Bus Timing tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tHD:STA tHIGH tLOW tR tHD:DAT tSU:DAT tSU:STO tDH tBUF © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 1118, Rev. A CAT24C164 WRITE OPERATIONS Byte Write In Byte Write mode, the Master sends the START condition and the Slave address with the R/W bit set to zero set to zero to the Slave. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24C164. After receiving another acknowledge from the Slave, the Master transmits the data byte to be written into the addressed memory location. The CAT24C164 device will acknowledge the data byte and the Master generates the STOP condition, at which time the device begins its internal Write cycle to nonvolatile memory (Figure 5). While this internal cycle is in progress (tWR), the SDA output will be tri-stated and the CAT24C164 will not respond to any request from the Master device (Figure 6). Page Write The CAT24C164 writes up to 16 bytes of data in a single write cycle, using the Page Write operation (Figure 7). The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the data byte is transmitted, the Master is allowed to send up to fifteen additional bytes. After each byte has been transmitted the CAT24C164 will respond with an acknowledge and internally increments the four low order address bits. The high order bits that define the page address remain unchanged. If the Master transmits more than sixteen bytes prior to sending the STOP condition, the address counter ‘wraps around’ to the beginning of page and previously transmitted data will be overwritten. Once all sixteen bytes are received and the STOP condition has been sent by the Master, the internal Write cycle begins. At this point all received data is written to the CAT24C164 in a single write cycle. Acknowledge Polling The acknowledge (ACK) polling routine can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT24C164 initiates the internal write cycle. The ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24C164 is still busy with the write operation, NoACK will be returned. If the CAT24C164 has completed the internal write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C164. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 8). If the WP pin is HIGH during the strobe interval, the CAT24C164 will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24C164 is shipped erased, i.e., all bytes are FFh. Doc. No. 1118, Rev. A 6 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C164 Figure 5. Byte Write Sequence BUS ACTIVITY: MASTER S T A R T S SLAVE A C K A C K A C K S T O P P SLAVE ADDRESS ADDRESS BYTE a7 ÷ a 0 DATA BYTE d7 ÷ d0 Figure 6. Write Cycle Timing SCL SDA 8th Bit Byte n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Page Write Sequence BUS ACTIVITY: MASTER S T A R T S SLAVE n=1 P ≤ 15 A C K A C K A C K A C K A C K SLAVE ADDRESS ADDRESS BYTE DATA BYTE n DATA BYTE n+1 DATA BYTE n+P S T O P P Figure 8. WP Timing ADDRESS BYTE 1 SCL 8 9 1 DATA BYTE 8 SDA a7 a0 tSU:WP d7 d0 WP tHD:WP © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc No. 1118, Rev. A CAT24C164 READ OPERATIONS Immediate Read Upon receiving a Slave address with the R/W bit set to set to ‘1’, the CAT24C164 will interpret this as a request for data residing at the current byte address in memory. The CAT24C164 will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 9), the CAT24C164 returns to Standby mode. Selective Read Selective Read operations allow the Master device to select at random any memory location for a read operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24C164 acknowledges the byte address, the Master device resends the START condition and the slave slave address, this time with the R/W bit set to one. The set to one. The CAT24C164 then responds with its acknowledge and sends the requested data byte. The Master device does not acknowledge the data (NoACK) but will generate a STOP condition (Figure 10). Sequential Read If during a Read session, the Master acknowledges the 1st data byte, then the CAT24C164 will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 11). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap-around at end of memory (rather than end of page). Doc. No. 1118, Rev. A 8 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C164 Figure 9. Immediate Read Sequence and Timing N O SLAVE ADDRESS BUS ACTIVITY: MASTER S T A R T S S AT CO KP P SLAVE A C K DATA BYTE SCL 8 9 SDA 8th Bit DATA OUT NO ACK STOP Figure 10. Selective Read Sequence BUS ACTIVITY: MASTER S T A R T S SLAVE ADDRESS ADDRESS BYTE S T A R T S N O SLAVE ADDRESS S AT CO KP P SLAVE A C K A C K A C K DATA BYTE Figure 11. Sequential Read Sequence BUS ACTIVITY: MASTER SLAVE ADDRESS A C K A C K A C K N O S AT CO KP P SLAVE A C K DATA BYTE n DATA BYTE n+1 DATA BYTE n+2 DATA BYTE n+x © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc No. 1118, Rev. A CAT24C164 8-LEAD 300 MIL WIDE PLASTIC DIP (L) E1 D E A2 A A1 L e b2 b eB SYMBOL A A1 A2 b b2 D E E1 e eB L MIN 0.38 3.05 0.36 1.14 9.02 7.62 6.09 7.87 0.115 NOM MAX 4.57 3.81 0.56 1.77 10.16 8.25 7.11 9.65 0.150 24C16_8-LEAD_DIP_(300P).eps 0.46 7.87 6.35 2.54 BSC 0.130 Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 Doc. No. 1118, Rev. A 10 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C164 8-LEAD 150 MIL WIDE SOIC (W) E1 E D A θ1 e b A1 h x 45 C L SYMBOL A1 A b C D E E1 e h L θ1 MIN 0.10 1.35 0.33 0.19 4.80 5.80 3.80 NOM MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00 1.27 BSC 0.25 0.40 0° 0.50 1.27 8° 24C16_8-LEAD_SOIC.eps For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012 dimensions. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc No. 1118, Rev. A CAT24C164 8-LEAD TSSOP (Y) D 8 5 SEE DETAIL A c E E1 E/2 1 4 GAGE PLANE PIN #1 IDENT. θ1 A2 L 0.25 SEATING PLANE SEE DETAIL A A e b A1 SYMBOL A A1 A2 b c D E E1 e L θ1 MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00 NOM MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00 0.90 3.00 6.4 4.40 0.65 BSC 0.60 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-153. Doc. No. 1118, Rev. A 12 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C164 8-PAD TDFN 2X3 PACKAGE (VP2) A E PIN 1 INDEX AREA D A1 A2 A3 D2 SYMBOL A A1 A2 A3 b D D2 E E2 e L MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20 NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30 MAX 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40 b e 3xe E2 PIN 1 ID L For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. TDFN2X3 (03).eps Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-229. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc No. 1118, Rev. A CAT24C164 PACKAGE MARKING 8-Lead PDIP 8-Lead SOIC 24C164LI FYYWWG 24C164WI FYYWWG CSI I YY WW G F = = = = = = Catalyst Semiconductor, Inc. Temperature Range Production Year Production Week Product Revision Lead Finish 4 = NiPdAu CSI I YY WW G F = = = = = = Catalyst Semiconductor, Inc. Temperature Range Production Year Production Week Product Revision Lead Finish 4 = NiPdAu 8-Lead TSSOP 8-Pad TDFN YMGF 24164I XXN NNN YM Y M G I F = = = = = Production Year Production Month Die Revision Temperature Range Lead Finish 4 = NiPdAu XX = Device Code FR = NiPdAu N = Traceable Code Y = Production Year M = Production Month Notes: (1) The circle on the package marking indicates the location of Pin 1. (2) For TDFN package, the Product Revision marking is included in the Device Code (XX). Doc. No. 1118, Rev. A 14 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C164 EXAMPLE OF ORDERING INFORMATION Prefix CAT Device # 24C164 Suffix Y I – G T3 Company ID Product Number 24C164 Temperature Range I = Industrial (-40°C to +85°C) T: Tape & Reel 3: 3000/Reel L: W: Y: VP2: Notes: Package PDIP SOIC, JEDEC TSSOP TDFN Lead Finish G: NiPdAu (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT24C164YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel). (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 15 Doc No. 1118, Rev. A REVISION HISTORY Date 08/11/06 Revision Comments A Inital Release Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ MiniPot™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. 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Products with data sheets labeled “Advance Information” or “Preliminary” and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: 1118 A 08/11/06