CAT24C64LIT3

CAT24C64 FEATURES 64-Kb I2C CMOS Serial EEPROM DEVICE DESCRIPTION The CAT24C64 is a 64-Kb CMOS Serial EEPROM devices, internally organized as 128 pages of 64 bytes each. It features a 32-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. External address pins make it possible to address up to eight CAT24C64 devices on the same bus. ■ Supports Standard and Fast I2C Protocol ■ 1.8 V to 5.5 V Supply Voltage Range ■ 32-Byte Page Write Buffer(1) ■ Hardware Write Protection for entire memory ■ Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA). ■ Low power CMOS technology ■ 1,000,000 program/erase cycles ■ 100 year data retention ■ Industrial temperature range ■ RoHS-compliant 8-pin PDIP, SOIC, TSSOP and TDFN packages Note: (1) CAT24C64 Rev. D (Not Recommended for New Designs) has 64-Byte Page Write Buffer. For Ordering Information details, see page 15. PIN CONFIGURATION PDIP (L) SOIC (W) TSSOP (Y) TDFN (ZD2, VP2) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA FUNCTIONAL SYMBOL VCC SCL A2, A1, A0 WP CAT24C64 SDA For the location of Pin 1, please consult the corresponding package drawing. PIN FUNCTIONS A0, A1, A2 SDA SCL WP VCC VSS Device Address Serial Data Serial Clock Write Protect Power Supply Ground VSS * The Green & Gold seal identifies RoHS-compliant packaging, using NiPdAu pre-plated lead frames. © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1102, Rev. H CAT24C64 ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature Voltage on Any Pin with Respect to Ground(2) RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years -65°C to +150°C -0.5 V to +6.5 V D.C. OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. ed. Symbol ICCR ICCW ISB IL VIL VIH VOL1 VOL2 Parameter Read Current Write Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA VCC < 2.5 V, IOL = 1.0 mA Test Conditions Read, fSCL = 400 kHz Write, fSCL = 400 kHz All I/O Pins at GND or VCC Pin at GND or VCC -0.5 Min Max 1 1 1 1 VCC x 0.3 Units mA mA μA μA V V V V VCC x 0.7 VCC + 0.5 0.4 0.2 PIN IMPEDANCE CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. ed. Symbol CIN(3) CIN(3) IWP(5) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current Conditions VIN = 0 V VIN = 0 V VIN < VIH VIN > VIH Note: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC = 5 V, 25°C (5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. Max 8 6 100 1 Units pF pF μA Doc. No. 1102, Rev. H 2 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C64 A.C. CHARACTERISTICS(1) VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C. Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF(2) tSU:STO tBUF tAA tDH Ti(2) tSU:WP tHD:WP tWR tPU(2, 3) Note: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands. Fast Min 0.6 1.3 0.6 0.6 0 100 Max 400 Units kHz μs μs μs μs μs ns 300 300 0.6 1.3 ns ns μs μs 0.9 100 100 0 2.5 μs ns ns μs μs 5 1 ms ms Parameter Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power-up to Ready Mode Min 4 4.7 4 4.7 0 250 Max 100 1000 300 4 4.7 3.5 100 100 0 2.5 5 1 A.C. TEST CONDITIONS Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 x VCC to 0.8 x VCC ≤ 50 ns 0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF (V (V © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc No. 1102, Rev. H CAT24C64 POWER-ON RESET (POR) Each CAT24C64 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against ‘brown-out’ failure following a temporary loss of power. FUNCTIONAL DESCRIPTION The CAT24C64 supports the Inter-Integrated Circuit (I2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The CAT24C64 operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles. I2C BUS PROTOCOL The 2-wire I2C bus consists of two lines, SCL and SDA, connected to the VCC supply via pull-up resistors. The Master provides the clock to the SCL line, and either the Master or the Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH. START/STOP Condition An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 1). The START consists of a HIGH to LOW SDA transition, while SCL is HIGH. Absent the START, a Slave will not respond to the Master. The STOP completes all commands, and consists of a LOW to HIGH SDA transition, while SCL is HIGH. Device Addressing The Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address. For the CAT24C64, the first four bits of the Slave address are set to 1010 (Ah); the next three bits, A2, A1 and A0, must match the logic state of the similarly named input pins. pins. The R/W bit tells the Slave whether the Master tells the Slave whether the Master intends to read (1) or write (0) data (Figure 2). Acknowledge During the 9th clock cycle following every byte sent to the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 3). Bus timing is illustrated in Figure 4. PIN DESCRIPTION SCL: The Serial Clock input pin accepts the clock signal generated by the Master. SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device address that must be matched by the corresponding Slave address bits. The Address inputs are hard-wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left floating, these pins are pulled LOW internally. WP: When pulled HIGH, the Write Protect input pin inhibits all write operations. When left floating, this pin is pulled LOW internally. Doc. No. 1102, Rev. H 4 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C64 Figure 1. Start/Stop Timing SCL SDA START CONDITION STOP CONDITION Figure 2. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W DEVICE ADDRESS Figure 3. Acknowledge Timing BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 8 9 BUS RELEASE DELAY (RECEIVER) DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK DELAY (≤ tAA) ACK SETUP (≥ tSU:DAT) Figure 4. Bus Timing tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tDH tBUF tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW tR © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 1102, Rev. H CAT24C64 WRITE OPERATIONS Byte Write To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘0’. The Master then sends set to ‘0’. The Master then sends two address bytes and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 5). The STOP starts the internal Write cycle, and while this operation is in progress (tWR), the SDA output is tri-stated and the Slave does not acknowledge the Master (Figure 6). Page Write The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 7). Up to 32(1) distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (tWR). Acknowledge Polling As soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum specified Write time (tWR) to elapse. Upon receiving a NoACK response from the Slave, the Master simply repeats the request until the Slave responds with ACK. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the 1st data byte (Figure 8). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24C64 is shipped erased, i.e., all bytes are FFh. Note: (1) CAT24C64 Rev. D (Not Recommended for New Designs) has 64-Byte Page Write Buffer. Doc. No. 1102, Rev. H 6 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C64 Figure 5. Byte Write Sequence BUS ACTIVITY: MASTER S T A R T S SLAVE A C K S T O P P A C K A C K A C K SLAVE ADDRESS ADDRESS BYTE a15 ÷ a8 DATA BYTE a7 ÷ a 0 DATA BYTE d7 ÷ d 0 ** * * a15 ÷ a13 are don't care bits. Figure 6. Write Cycle Timing SCL SDA 8th Bit Byte n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Page Write Sequence BUS ACTIVITY: MASTER S T A R T S SLAVE A C K A C K A C K A C K A C K A C K A C K SLAVE ADDRESS ADDRESS BYTE ADDRESS BYTE DATA BYTE n DATA BYTE n+1 DATA BYTE n+P S T O P P Figure 8. WP Timing ADDRESS BYTE 1 SCL 8 9 1 DATA BYTE 8 SDA a7 a0 tSU:WP d7 d0 WP tHD:WP © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc No. 1102, Rev. H CAT24C64 READ OPERATIONS Immediate Read To read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with set to ‘1’. The Slave responds with ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 9). The Slave then returns to Standby mode. Selective Read To read data residing at a specific address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to ‘0’ and then sends two address bytes to the Slave. Rather than completing the Byte Write sequence by sending data, the Master then creates a START condition and broadcasts broadcasts a Slave address with the R/W bit set to ‘1’. set to ‘1’. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 10). Sequential Read If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 11). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. Doc. No. 1102, Rev. H 8 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C64 Figure 9. Immediate Read Sequence and Timing N O SLAVE ADDRESS BUS ACTIVITY: MASTER S T A R T S S AT CO KP P SLAVE A C K DATA BYTE SCL 8 9 SDA 8th Bit DATA OUT NO ACK STOP Figure 10. Selective Read Sequence BUS ACTIVITY: MASTER S T A R T S SLAVE ADDRESS ADDRESS BYTE ADDRESS BYTE S T A R T S N O SLAVE ADDRESS S AT CO KP P SLAVE A C K A C K A C K A C K DATA BYTE Figure 11. Sequential Read Sequence BUS ACTIVITY: MASTER SLAVE ADDRESS A C K A C K A C K N O S AT CO KP P SLAVE A C K DATA BYTE n DATA BYTE n+1 DATA BYTE n+2 DATA BYTE n+x © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc No. 1102, Rev. H CAT24C64 8-LEAD 300 MIL WIDE PLASTIC DIP (L) E1 D E A2 A A1 L e b2 b eB SYMBOL A A1 A2 b b2 D E E1 e eB L MIN 0.38 3.05 0.36 1.14 9.02 7.62 6.09 7.87 0.115 NOM MAX 4.57 3.81 0.56 1.77 10.16 8.25 7.11 9.65 0.150 24C32_64_8-LEAD_DIP_(300P).eps 0.46 7.87 6.35 2.54 BSC 0.130 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 Doc. No. 1102, Rev. H 10 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C64 8-LEAD 150 MIL WIDE SOIC (W) E1 E D A θ1 e b A1 h x 45 C L SYMBOL A1 A b C D E E1 e h L θ1 MIN 0.10 1.35 0.33 0.19 4.80 5.80 3.80 NOM MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00 1.27 BSC 0.25 0.40 0° 0.50 1.27 8° 24C32_64_8-LEAD_SOIC.eps For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012 dimensions. © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc No. 1102, Rev. H CAT24C64 8-LEAD TSSOP (Y) D 8 5 SEE DETAIL A c E E1 E/2 1 4 GAGE PLANE PIN #1 IDENT. θ1 A2 L 0.25 SEATING PLANE SEE DETAIL A A e b A1 SYMBOL A A1 A2 b c D E E1 e L θ1 MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00 NOM MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00 0.90 3.00 6.4 4.40 0.65 BSC 0.60 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-153. Doc. No. 1102, Rev. H 12 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C64 8-LEAD TDFN 3X4.9 PACKAGE (ZD2) SYMBOL A A1 A2 A3 b D D2 E E2 e L MIN 0 . 70 0 . 00 0 . 45 NOM 0 . 75 0 . 02 0 . 55 0 . 20 R E F M AX 0 . 80 0 . 05 0 . 65 0 . 25 2 . 90 0 . 90 4 . 80 0 . 90 0 . 30 3 . 00 1 . 00 4 . 90 1 . 00 0 . 65 T Y P 0 . 35 3 . 10 1 . 10 5 . 00 1 . 10 0 . 50 0 . 60 0 . 70 Notes: (1) All dimensions are in millimeters. Angles in degree. For current Tape and (2) Complies with JEDEC MO-229. Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. Angles in degree. 2. Complies with JEDEC MO-229. © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc No. 1102, Rev. H CAT24C64 CAT4004 8-LEAD TDFN 2x3 (VP2) PACKAGE OUTLINES 8 LEAD TDFN (VP2) 2mm x 3mm A E PIN 1 INDEX AREA D A1 A2 A3 D2 SYMB OL A A1 A2 A3 b D D2 E E2 e L MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20 NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30 MA X 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40 b 3xe E2 PIN 1 ID L e For current Tape & Reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters, angles in degrees. Notes: (2) Complies with JEDEC Standard 1. All dimensions are in millimeters, angles in degrees. 2. Complies with JEDEC Standard MO-229. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 1102, Rev. H 9 Doc. No. 5024 Rev. A © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 14 CAT24C64 EXAMPLE OF ORDERING INFORMATION Prefix CAT Device # 24C64 Y Suffix I – G T3 Company ID Product Number 24C64 Temperature Range I = Industrial (-40°C to +85°C) T: Tape & Reel 2: 2000/Reel 3: 3000/Reel L: W: Y: ZD2: VP2: Notes: Package PDIP SOIC, JEDEC TSSOP TDFN (3x4.9)(5) TDFN (2x3) Lead Finish G: NiPdAu (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu on pre-plated (PPF) lead frames. (3) The device used in the above example is a CAT24C64YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel). (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. (5) TDFN, ZD2 is only available in 2000 pcs/reel, i.e., CAT24C64ZD2I-T2. The TDFN (3x4.9) package is not recommended for new designs. © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 15 Doc No. 1102, Rev. H CAT24C64 REVISION HISTORY Date 10/07/05 11/16/05 Revision Comments A B Initial Issue Update Ordering Information Add Tape and Reel Specifications 02/02/06 08/23/06 C D Update Ordering Information Updated device description, supporting text and figures, package outlines, package marking and ordering information. Updated and re-formatted D.C. Characteristics presentation. Updated and re-formatted A.C. Characteristics presentation to reflect Standard (100 kHz) and Fast (400 kHz) operation over the full voltage range. 09/08/06 02/13/07 03/20/07 03/29/07 E F G H Remove Package Marking Update TDFN 8 Lead (3x4.9mm) package Add TDFN 8 Lead (2x3mm) package Update Page Write Buffer to 32-Bytes (for CAT24C64 Rev. E) Doc. No. 1102, Rev. H 16 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C64 Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Beyond Memory ™, DPP ™, EZDim ™, MiniPot™, and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled “Advance Information” or “Preliminary” and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 17 Doc No. 1102, Rev. H Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: 1102 H 03/29/07