CDB42528

CS42526 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver Features ! Six 24-bit D/A, two 24-bit A/D Converters ! 114 dB DAC / 114 dB ADC Dynamic Range ! -100 dB THD+N ! System Sampling Rates up to 192 kHz ! S/PDIF Receiver Compatible with EIAJ General Description The CS42526 codec provides two analog-to-digital and six digital-to-analog delta-sigma converters, as well as an integrated S/PDIF receiver. The CS42526 integrated S/PDIF receiver supports up to eight inputs, clock recovery circuitry and format autodetection. The internal stereo ADC is capable of independent channel gain control for single-ended or differential analog inputs. All six channels of DAC provide digital volume control and differential analog outputs. The general-purpose outputs may be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators. The CS42526 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, digital speaker and automotive audio systems. The CS42526 is available in a 64-pin LQFP package in both Commercial (-10° to 70° C) and Automotive (-40° to 85° C) grades. The CDB42528 Customer Demonstration board is also available for device evaluation. Refer to “Ordering Information” on page 91. DGND DGND VD VD INT C&U Bit Data Buffer Format Detector Control Port RST AD0/CS AD1/CDIN SDA/CDOUT SCL/CCLK VLC OMCK Internal MCLK Ref DEM Mult/Div Serial Audio Interface Port RMCK SAI_LRCK SAI_SCLK SAI_SDOUT VLS ADC Serial Data ADCIN1 ADCIN2 CX_SDOUT CX_LRCK CX_SCLK DAC#2 Volume Control Analog Filter Digital Filter DAC#3 DAC#4 DAC#5 DAC#6 CODEC Serial Port CX_SDIN1 CX_SDIN2 CX_SDIN3 CP1201 and IEC-60958 ! Recovered S/PDIF Clock or System Clock Selection ! 8:2 S/PDIF Input MUX ! ADC High-Pass Filter for DC Offset Calibration ! Expandable ADC Channels and One-Line Mode Support ! Digital Output Volume Control with Soft Ramp ! Digital +/-15 dB Input Gain Adjust for ADC ! Differential Analog Architecture ! Supports Logic Levels between 1.8 V and 5 V TXP RXP0 RXP1/GPO1 RXP2/GPO2 RXP3/GPO3 RXP4/GPO4 RXP5/GPO5 RXP6/GPO6 RXP7/GPO7 VARX AGND LPFLT Rx Clock/Data Recovery S/PDIF Decoder GPO MUTEC FILT+ VQ REFGND VA AGND AINL+ AINLAINR+ AINRAOUTA1+ AOUTA1AOUTB1+ AOUTB1AOUTA2+ AOUTA2AOUTB2+ AOUTB2AOUTA3+ AOUTA3AOUTB3+ AOUTB3MUTE ADC#1 ADC#2 Digital Filter Gain & Clip Gain & Clip Digital Filter DAC#1 http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) NOVEMBER '05 DS585F1 CS42526 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7 SPECIFIED OPERATING CONDITIONS ............................................................................................... 7 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 7 ANALOG INPUT CHARACTERISTICS .................................................................................................. 8 A/D DIGITAL FILTER CHARACTERISTICS .......................................................................................... 9 ANALOG OUTPUT CHARACTERISTICS ............................................................................................ 10 D/A DIGITAL FILTER CHARACTERISTICS ........................................................................................ 11 SWITCHING CHARACTERISTICS ...................................................................................................... 12 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT .............................................. 13 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT .......................................... 14 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 15 DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 16 2. PIN DESCRIPTIONS ............................................................................................................................ 17 3. TYPICAL CONNECTION DIAGRAM ............................................................................................. 20 4. APPLICATIONS ................................................................................................................................... 21 4.1 Overview ......................................................................................................................................... 21 4.2 Analog Inputs .................................................................................................................................. 21 4.2.1 Line-Level Inputs ................................................................................................................... 21 4.2.2 High-Pass Filter and DC Offset Calibration ........................................................................... 22 4.3 Analog Outputs ............................................................................................................................... 22 4.3.1 Line-Level Outputs and Filtering ........................................................................................... 22 4.3.2 Interpolation Filter .................................................................................................................. 22 4.3.3 Digital Volume and Mute Control ........................................................................................... 23 4.3.4 ATAPI Specification ............................................................................................................... 23 4.4 S/PDIF Receiver ............................................................................................................................. 24 4.4.1 8:2 S/PDIF Input Multiplexer ................................................................................................. 24 4.4.2 Error Reporting and Hold Function ........................................................................................ 24 4.4.3 Channel Status Data Handling .............................................................................................. 24 4.4.4 User Data Handling ............................................................................................................... 24 4.4.5 Non-Audio Auto-Detection ..................................................................................................... 24 4.5 Clock Generation ............................................................................................................................ 25 4.5.1 PLL and Jitter Attenuation ..................................................................................................... 25 4.5.2 OMCK System Clock Mode ................................................................................................... 26 4.5.3 Master Mode ......................................................................................................................... 26 4.5.4 Slave Mode ........................................................................................................................... 26 4.6 Digital Interfaces ............................................................................................................................. 27 4.6.1 Serial Audio Interface Signals ............................................................................................... 27 4.6.2 Serial Audio Interface Formats .............................................................................................. 29 4.6.3 ADCIN1/ADCIN2 Serial Data Format .................................................................................... 32 4.6.4 One-Line Mode (OLM) Configurations .................................................................................. 33 4.6.4.1 OLM Config #1 ........................................................................................................... 33 4.6.4.2 OLM Config #2 ........................................................................................................... 34 4.6.4.3 OLM Config #3 ........................................................................................................... 35 4.6.4.4 OLM Config #4 ........................................................................................................... 36 4.6.4.5 OLM Config #5 ........................................................................................................... 37 4.7 Control Port Description and Timing ............................................................................................... 38 4.7.1 SPI Mode ............................................................................................................................... 38 4.7.2 I²C Mode ................................................................................................................................ 39 4.8 Interrupts ........................................................................................................................................ 40 4.9 Reset and Power-Up ...................................................................................................................... 40 4.10 Power Supply, Grounding, and PCB Layout ................................................................................ 41 5. REGISTER QUICK REFERENCE ........................................................................................................ 42 2 DS585F1 CS42526 6. REGISTER DESCRIPTION .................................................................................................................. 46 6.1 Memory Address Pointer (MAP) ..................................................................................................... 46 6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 46 6.3 Power Control (address 02h) .......................................................................................................... 47 6.4 Functional Mode (address 03h) ...................................................................................................... 48 6.5 Interface Formats (address 04h) .................................................................................................... 50 6.6 Misc Control (address 05h) ............................................................................................................ 51 6.7 Clock Control (address 06h) ........................................................................................................... 53 6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ....................................................................... 54 6.9 RVCR Status (address 08h) (Read Only) ....................................................................................... 54 6.10 Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only) ........................................ 56 6.11 Volume Transition Control (address 0Dh) .................................................................................... 57 6.12 Channel Mute (address 0Eh) ........................................................................................................ 59 6.13 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h) ...................................................... 59 6.14 Channel Invert (address 17h) ....................................................................................................... 59 6.15 Mixing Control Pair 1 (Channels A1 & B1)(address 18h) Mixing Control Pair 2 (Channels A2 & B2)(address 19h) Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah) ............................................................. 60 6.16 ADC Left Channel Gain (address 1Ch) ........................................................................................ 62 6.17 ADC Right Channel Gain (address 1Dh) ...................................................................................... 62 6.18 Receiver Mode Control (address 1Eh) ......................................................................................... 62 6.19 Receiver Mode Control 2 (address 1Fh) ...................................................................................... 64 6.20 Interrupt Status (address 20h) (Read Only) ................................................................................. 64 6.21 Interrupt Mask (address 21h) ....................................................................................................... 65 6.22 Interrupt Mode MSB (address 22h) Interrupt Mode LSB (address 23h) ............................................................................................... 66 6.23 Channel Status Data Buffer Control (address 24h) ...................................................................... 66 6.24 Receiver Channel Status (address 25h) (Read Only) .................................................................. 67 6.25 Receiver Errors (address 26h) (Read Only) ................................................................................. 68 6.26 Receiver Errors Mask (address 27h) ............................................................................................ 69 6.27 Mutec Pin Control (address 28h) .................................................................................................. 70 6.28 RXP/General-Purpose Pin Control (addresses 29h to 2Fh) ......................................................... 70 6.29 Q-Channel Subcode Bytes 0 to 9 (addresses 30h to 39h) (Read Only) ....................................... 72 6.30 C-Bit or U-Bit Data Buffer (addresses 3Ah to 51h) (Read Only) .................................................. 72 7. PARAMETER DEFINITIONS ................................................................................................................ 73 8. APPENDIX A: EXTERNAL FILTERS ................................................................................................... 74 8.1 ADC Input Filter .............................................................................................................................. 74 8.2 DAC Output Filter ........................................................................................................................... 74 9. APPENDIX B: S/PDIF RECEIVER ....................................................................................................... 75 9.1 Error Reporting and Hold Function ................................................................................................. 75 9.2 Channel Status Data Handling ....................................................................................................... 75 9.2.1 Channel Status Data E Buffer Access ................................................................................... 76 9.2.1.1 One-Byte Mode .......................................................................................................... 76 9.2.1.2 Two-Byte Mode .......................................................................................................... 76 9.2.2 Serial Copy Management System (SCMS) ........................................................................... 77 9.3 User (U) Data E Buffer Access ....................................................................................................... 77 9.3.1 Non-Audio Auto-Detection ..................................................................................................... 77 9.3.1.1 Format Detection ....................................................................................................... 77 10. APPENDIX C: PLL FILTER ................................................................................................................ 78 10.1 External Filter Components .......................................................................................................... 78 10.1.1 General ................................................................................................................................ 78 10.1.2 Jitter Attenuation ................................................................................................................. 80 10.1.3 Capacitor Selection ............................................................................................................. 81 10.1.4 Circuit Board Layout ............................................................................................................ 82 DS585F1 3 CS42526 11. APPENDIX D: EXTERNAL AES3-S/PDIF-IEC60958 RECEIVER COMPONENTS .......................... 83 11.1 AES3 Receiver External Components .......................................................................................... 83 12. APPENDIX E: ADC FILTER PLOTS .................................................................................................. 84 13. APPENDIX F: DAC FILTER PLOTS .................................................................................................. 86 14. PACKAGE DIMENSIONS ............................................................................................................... 90 THERMAL CHARACTERISTICS .......................................................................................................... 90 15. ORDERING INFORMATION .............................................................................................................. 91 16. REFERENCES .................................................................................................................................... 91 17. REVISION HISTORY ......................................................................................................................... 92 LIST OF FIGURES Figure 1.Serial Audio Port Master Mode Timing ....................................................................................... 12 Figure 2.Serial Audio Port Slave Mode Timing ......................................................................................... 12 Figure 3.Control Port Timing - I²C Format ................................................................................................. 13 Figure 4.Control Port Timing - SPI Format ................................................................................................ 14 Figure 5.Typical Connection Diagram ....................................................................................................... 20 Figure 6.Full-Scale Analog Input ............................................................................................................... 21 Figure 7.Full-Scale Output ........................................................................................................................ 22 Figure 8.ATAPI Block Diagram (x = channel pair 1, 2, or 3) ..................................................................... 23 Figure 9.CS42526 Clock Generation ........................................................................................................ 25 Figure 10.I²S Serial Audio Formats ........................................................................................................... 29 Figure 11.Left-Justified Serial Audio Formats ........................................................................................... 30 Figure 12.Right-Justified Serial Audio Formats ......................................................................................... 30 Figure 13.One Line Mode #1 Serial Audio Format .................................................................................... 31 Figure 14.One Line Mode #2 Serial Audio Format .................................................................................... 31 Figure 15.ADCIN1/ADCIN2 Serial Audio Format ...................................................................................... 32 Figure 16.OLM Configuration #1 ............................................................................................................... 33 Figure 17.OLM Configuration #2 ............................................................................................................... 34 Figure 18.OLM Configuration #3 ............................................................................................................... 35 Figure 19.OLM Configuration #4 ............................................................................................................... 36 Figure 20.OLM Configuration #5 ............................................................................................................... 37 Figure 21.Control Port Timing in SPI Mode .............................................................................................. 38 Figure 22.Control Port Timing, I²C Write ................................................................................................... 39 Figure 23.Control Port Timing, I²C Read ................................................................................................... 39 Figure 24.Recommended Analog Input Buffer .......................................................................................... 74 Figure 25.Recommended Analog Output Buffer ....................................................................................... 74 Figure 26.Channel Status Data Buffer Structure ....................................................................................... 76 Figure 27.PLL Block Diagram ................................................................................................................... 78 Figure 28.Jitter-Attenuation Characteristics of PLL - Configurations 1 & 2 ............................................... 80 Figure 29.Jitter-Attenuation Characteristics of PLL - Configuration 3 ....................................................... 80 Figure 30.Recommended Layout Example ............................................................................................... 82 Figure 31.Consumer Input Circuit ............................................................................................................. 83 Figure 32.S/PDIF MUX Input Circuit ......................................................................................................... 83 Figure 33.TTL/CMOS Input Circuit ............................................................................................................ 83 Figure 34.Single-Speed Mode Stopband Rejection .................................................................................. 84 Figure 35.Single-Speed Mode Transition Band ........................................................................................ 84 Figure 36.Single-Speed Mode Transition Band (Detail) ............................................................................ 84 Figure 37.Single-Speed Mode Passband Ripple ...................................................................................... 84 Figure 38.Double-Speed Mode Stopband Rejection ................................................................................. 84 Figure 39.Double-Speed Mode Transition Band ....................................................................................... 84 Figure 40.Double-Speed Mode Transition Band (Detail) .......................................................................... 85 Figure 41.Double-Speed Mode Passband Ripple ..................................................................................... 85 Figure 42.Quad-Speed Mode Stopband Rejection ................................................................................... 85 4 DS585F1 CS42526 Figure 43.Quad-Speed Mode Transition Band ......................................................................................... 85 Figure 44.Quad-Speed Mode Transition Band (Detail) ............................................................................. 85 Figure 45.Quad-Speed Mode Passband Ripple ....................................................................................... 85 Figure 46.Single-Speed (fast) Stopband Rejection ................................................................................... 86 Figure 47.Single-Speed (fast) Transition Band ......................................................................................... 86 Figure 48.Single-Speed (fast) Transition Band (detail) ............................................................................. 86 Figure 49.Single-Speed (fast) Passband Ripple ....................................................................................... 86 Figure 50.Single-Speed (slow) Stopband Rejection ................................................................................. 86 Figure 51.Single-Speed (slow) Transition Band ........................................................................................ 86 Figure 52.Single-Speed (slow) Transition Band (detail) ............................................................................ 87 Figure 53.Single-Speed (slow) Passband Ripple ...................................................................................... 87 Figure 54.Double-Speed (fast) Stopband Rejection ................................................................................. 87 Figure 55.Double-Speed (fast) Transition Band ........................................................................................ 87 Figure 56.Double-Speed (fast) Transition Band (detail) ............................................................................ 87 Figure 57.Double-Speed (fast) Passband Ripple ...................................................................................... 87 Figure 58.Double-Speed (slow) Stopband Rejection ................................................................................ 88 Figure 59.Double-Speed (slow) Transition Band ...................................................................................... 88 Figure 60.Double-Speed (slow) Transition Band (detail) .......................................................................... 88 Figure 61.Double-Speed (slow) Passband Ripple .................................................................................... 88 Figure 62.Quad-Speed (fast) Stopband Rejection .................................................................................... 88 Figure 63.Quad-Speed (fast) Transition Band .......................................................................................... 88 Figure 64.Quad-Speed (fast) Transition Band (detail) .............................................................................. 89 Figure 65.Quad-Speed (fast) Passband Ripple ........................................................................................ 89 Figure 66.Quad-Speed (slow) Stopband Rejection ................................................................................... 89 Figure 67.Quad-Speed (slow) Transition Band ......................................................................................... 89 Figure 68.Quad-Speed (slow) Transition Band (detail) ............................................................................. 89 Figure 69.Quad-Speed (slow) Passband Ripple ....................................................................................... 89 DS585F1 5 CS42526 LIST OF TABLES Table 1. Common OMCK Clock Frequencies ............................................................................................ 26 Table 2. Common PLL Output Clock Frequencies..................................................................................... 26 Table 3. Slave Mode Clock Ratios ............................................................................................................. 27 Table 4. Serial Audio Port Channel Allocations ......................................................................................... 28 Table 5. DAC De-Emphasis ....................................................................................................................... 49 Table 6. Receiver De-Emphasis ................................................................................................................ 49 Table 7. Digital Interface Formats .............................................................................................................. 50 Table 8. ADC One-Line Mode.................................................................................................................... 50 Table 9. DAC One-Line Mode.................................................................................................................... 50 Table 10. RMCK Divider Settings .............................................................................................................. 53 Table 11. OMCK Frequency Settings ........................................................................................................ 53 Table 12. Master Clock Source Select....................................................................................................... 54 Table 13. AES Format Detection ............................................................................................................... 55 Table 14. Receiver Clock Frequency Detection......................................................................................... 56 Table 15. Example Digital Volume Settings ............................................................................................... 59 Table 16. ATAPI Decode ........................................................................................................................... 61 Table 17. Example ADC Input Gain Settings ............................................................................................. 62 Table 18. TXP Output Selection................................................................................................................. 64 Table 19. Receiver Input Selection ............................................................................................................ 64 Table 20. Auxiliary Data Width Selection ................................................................................................... 67 Table 21. External PLL Component Values & Locking Modes .................................................................. 78 6 DS585F1 CS42526 1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode) Parameter DC Power Supply Symbol Min 4.75 3.13 1.8 1.8 -10 -40 Typ 5.0 3.3 5.0 5.0 - Max 5.25 5.25 5.25 5.25 +70 +85 Units V V V V °C °C Analog VA / VARX Digital VD Serial Port Interface VLS Control Port Interface VLC Ambient Operating Temperature (power applied) CS42526-CQZ TA CS42526-DQZ ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Analog Digital Serial Port Interface Control Port Interface (Note 1) (Note 2) Symbol VA / VARX VD VLS VLC Iin Min -0.3 -0.3 -0.3 -0.3 - Max 6.0 6.0 6.0 6.0 ±10 Units V V V V mA Input Current Analog Input Voltage Digital Input Voltage (Note 2) VIN VIND-S VIND-C VIND-SP TA TA Tstg AGND-0.7 -0.3 -0.3 -0.3 -20 -50 -65 VA+0.7 VLS+ 0.4 VLC+ 0.4 VARX+0.4 +85 +95 +150 V V V V °C °C °C Serial Port Interface Control Port Interface S/PDIF interface Ambient Operating Temperature(power applied) CS42526-CQZ CS42526-DQZ Storage Temperature WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 2. The maximum over/under voltage is limited by the input current. DS585F1 7 CS42526 ANALOG INPUT CHARACTERISTICS (TA = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Full-scale input sine wave, 997 Hz.; PDN_RCVR = 1; SW_CTRL[1:0] = ‘01’; OMCK = 12.288 MHz; Single-Speed Mode CX_SCLK = 3.072 MHz; Double-Speed Mode CX_SCLK = 6.144 MHz; Quad-Speed Mode CX_SCLK = 12.288 MHz.) CS42526-CQZ Typ Max 114 111 -100 -91 -51 114 111 108 -100 -91 -51 -97 114 111 108 -100 -91 -51 -97 110 0.0001 0.1 +/-100 0 100 1.10 VA 82 -94 -94 -94 1.16 VA - Parameter (Fs=48 kHz) A-weighted unweighted Total Harmonic Distortion + Noise (Note 3) -1 dB -20 dB -60 dB Double-Speed Mode (Fs=96 kHz) Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 3) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Quad-Speed Mode (Fs=192 kHz) Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion+ Noise (Note 3) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Single-Speed Mode Dynamic Range Symbol Min 108 105 Min 106 103 106 103 106 103 - CS42526-DQZ Typ Max 114 111 -100 -91 -51 114 111 108 -100 -91 -51 -97 114 111 108 -100 -91 -51 -97 110 0.0001 0.1 +/-100 0 100 1.10 VA 82 -92 -92 -92 1.21 VA - Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Degree dB ppm/°C LSB LSB Vpp kΩ dB THD+N 108 105 108 105 1.05 VA 17 - THD+N THD+N Dynamic Performance for All Modes Interchannel Isolation Interchannel Phase Deviation DC Accuracy Interchannel Gain Mismatch Gain Drift Offset Error HPF_FREEZE disabled HPF_FREEZE enabled Analog Input Full-scale Differential Input Voltage Input Impedance (Differential) (Note 4) Common Mode Rejection Ratio 0.99 VA 17 - CMRR Notes: 3. Referred to the typical full-scale voltage. 4. Measured between AIN+ and AIN- 8 DS585F1 CS42526 A/D DIGITAL FILTER CHARACTERISTICS Parameter Single-Speed Mode (2 to 50 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency tgd ∆tgd (Note 5) (Note 5) tgd ∆tgd (Note 5) (Note 5) tgd ∆tgd (Note 5) (-0.1 dB) (Note 5) 0 0.58 -95 0 0.68 -92 0 0.78 -97 (Note 6) (Note 6) 12/Fs 9/Fs 5/Fs 1 20 10 105/Fs 0.47 ±0.035 0.0 0.45 ±0.035 0.0 0.24 ±0.035 0.0 0 Fs dB Fs dB s µs Fs dB Fs dB s µs Fs dB Fs dB s µs Hz Hz Deg dB s Symbol Min Typ Max Unit Double-Speed Mode (50 to 100 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency (-0.1 dB) Quad-Speed Mode (100 to 192 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency (-0.1 dB) High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Setting Time -3.0 dB -0.13 dB @ 20 Hz Notes: 5. The filter frequency response scales precisely with Fs. 6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. DS585F1 9 CS42526 ANALOG OUTPUT CHARACTERISTICS (TA = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measurement Bandwidth 10 Hz to 20 kHz unless otherwise specified.; Full-scale output 997 Hz sine wave, Test load RL = 3 kΩ, CL = 30 pF; PDN_RCVR = 1; SW_CTRL[1:0] = ‘01’; OMCK = 12.288 MHz; Single-Speed Mode, CX_SCLK = 3.072 MHz; Double-Speed Mode, CX_SCLK = 6.144 MHz; Quad-Speed Mode, CX_SCLK = 12.288 MHz.) CS42526-CQZ Typ Max CS42526-DQZ Typ Max Parameter Symbol Dynamic performance for all modes Dynamic Range (Note 7) 24-bit A-Weighted unweighted 16-bit A-Weighted (Note 8) unweighted Total Harmonic Distortion + Noise 24-bit 0 dB -20 dB -60 dB 16-bit 0 dB (Note 8) -20 dB -60 dB Idle Channel Noise/Signal-to-Noise Ratio (A-Weighted) Interchannel Isolation (1 kHz) Unloaded Full-Scale Differential Output Voltage Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance Min Min Unit 108 105 - 114 111 97 94 -100 -91 -51 -94 -74 -34 114 90 -94 - 106 103 - 114 111 97 94 -100 -91 -51 -94 -74 -34 114 90 -92 - dB dB dB dB dB dB dB dB dB dB dB dB THD+N Analog Output Characteristics for all modes VFS .89 VA 3 .94 VA 0.1 300 150 .99 VA 30 .84 VA 3 .94 VA 0.1 300 150 1.04 VA 30 Vpp dB ppm/°C Ω kΩ pF ZOUT RL CL Notes: 7. One-half LSB of triangular PDF dither is added to data. 8. Performance limited by 16-bit quantization noise. 10 DS585F1 CS42526 D/A DIGITAL FILTER CHARACTERISTICS Fast Roll-Off Slow Roll-Off Parameter Min Typ Max Min Typ Max Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz to -0.01 dB corner 0 to -3 dB corner 0 Frequency Response 10 Hz to 20 kHz -0.01 StopBand 0.5465 StopBand Attenuation (Note 10) 90 Group Delay Passband Group Delay Deviation 0 - 20 kHz De-emphasis Error (Note 11) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz to -0.01 dB corner 0 to -3 dB corner 0 Frequency Response 10 Hz to 20 kHz -0.01 StopBand 0.5834 StopBand Attenuation (Note 10) 80 Group Delay Passband Group Delay Deviation 0 - 20 kHz to -0.01 dB corner 0 to -3 dB corner 0 Frequency Response 10 Hz to 20 kHz -0.01 StopBand 0.6355 StopBand Attenuation (Note 10) 90 Group Delay Passband Group Delay Deviation 0 - 20 kHz Passband (Note 9) Passband (Note 9) Passband (Note 9) 12/Fs 4.6/Fs 4.7/Fs 0.4535 0.4998 +0.01 ±0.41/Fs ±0.23 ±0.14 ±0.09 0.4166 0.4998 0.01 ±0.03/Fs 0.1046 0.4897 0.01 ±0.01/Fs 0 0 -0.01 0.5834 64 0 0 -0.01 0.7917 70 6.5/Fs 3.9/Fs 4.2/Fs 0.4166 0.4998 +0.01 ±0.14/Fs ±0.23 ±0.14 ±0.09 0.2083 0.4998 0.01 ±0.01/Fs 0.1042 0.4813 0.01 ±0.01/Fs Unit Fs Fs dB Fs dB s s dB dB dB Fs Fs dB Fs dB s s Fs Fs dB Fs dB s s Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz 0 0 -0.01 0.8683 75 - Notes: 9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 46 to 69) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 10. Single- and Double-Speed Mode Measurement Bandwidth is from stopband to 3 Fs. Quad-Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs. 11. De-emphasis is available only in Single-Speed Mode. DS585F1 11 CS42526 SWITCHING CHARACTERISTICS (For CQZ, TA = -10 to +70° C; For DQZ, TA = -40 to +85° C; VA=VARX = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, CL = 30 pF) Parameters RST Pin Low Pulse Width PLL Clock Recovery Sample Rate Range RMCK Output Jitter RMCK Output Duty Cycle OMCK Frequency OMCK Duty Cycle CX_SCLK, SAI_SCLK Duty Cycle CX_LRCK, SAI_LRCK Duty Cycle (Note 14) (Note 15) (Note 13) (Note 13) (Note 12) Symbol Min 1 30 45 1.024 40 45 45 Typ 200 50 50 50 50 - Max 200 55 25.600 60 55 55 15 15 Units ms kHz ps RMS % MHz % % % ns ns Master Mode RMCK to CX_SCLK, SAI_SCLK active edge delay RMCK to CX_LRCK, SAI_LRCK delay tsmd tlmd 0 0 Slave Mode CX_SCLK, SAI_SCLK Falling Edge to CX_SDOUT, SAI_SDOUT Output Valid CX_LRCK, SAI_LRCK Edge to MSB Valid CX_SDIN Setup Time Before CX_SCLK Rising Edge CX_SDIN Hold Time After CX_SCLK Rising Edge CX_SCLK, SAI_SCLK High Time CX_SCLK, SAI_SCLK Low Time CX_SCLK, SAI_SCLK falling to CX_LRCK, SAI_LRCK Edge tdpd tlrpd tds tdh tsckh tsckl tlrck 10 30 20 20 -25 (Note 16) 26.5 +25 ns ns ns ns ns ns ns Notes: 12. After powering-up the CS42526, RST should be held low after the power supplies and clocks are settled. 13. See Table 1 on page 26 for suggested OMCK frequencies 14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz. 15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 53 is set to Multiply by 2. 16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode. CX_LRCK SAI_LRCK (input) CX_SCLK SAI_SCLK (output) CX_LRCK SAI_LRCK (output) t lrck t sckh t sckl CX_SCLK SAI_SCLK (input) t smd t lmd CX_SDINx t lrpd t ds t dh MSB RMCK t dpd MSB-1 CX_SDOUT SAI_SDOUT Figure 1. Serial Audio Port Master Mode Timing Figure 2. Serial Audio Port Slave Mode Timing 12 DS585F1 CS42526 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (For CQZ, TA = -10 to +70° C; For DQZ, TA = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CL = 30 pF) Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 18) (Note 17) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 - Max 100 1 300 (Note 19) Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns Notes: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed. 19. 15 15 15 -------------------- for Single-Speed Mode, -------------------- for Double-Speed Mode, ----------------- for Quad-Speed Mode 256 × Fs 128 × Fs 64 × Fs RST t Stop irs Start R e p e a te d Sta rt t rd t fd Stop SDA t buf t hdst t high t hdst t fc t susp SCL t t t sud t ack t sust t rc lo w hdd Figure 3. Control Port Timing - I²C Format DS585F1 13 CS42526 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT (For CQZ, TA = -10 to +70° C; For DQZ, TA = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CL = 30 pF) Parameter CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 22) (Note 22) (Note 21) (Note 20) Symbol fsck tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2 Min 0 1.0 20 66 66 40 15 - Typ - Max 6.0 50 25 25 100 100 Units MHz µs ns ns ns ns ns ns ns ns ns ns Notes: 20. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dictated by the timing requirements necessary to access the Channel Status and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should be safe for all possible conditions. 21. Data must be held for sufficient time to bridge the transition time of CCLK. 22. For fsck