CY24207ZC-1T

CY24207 MediaClock™ PDP Clock Generator Features • • • • Integrated phase-locked loop (PLL) Low-jitter, high-accuracy outputs VCXO with Analog Adjust 3.3V operation Benefits • Internal PLL with up to 400-MHz internal operation • Meets critical timing requirements in complex system designs • Large ±200-ppm range, better linearity • Enables application compatibility Output Frequency Range Two copies of 27-MHz reference clock output, two copies of 54/53.946053/67.425/67.357642 MHz (frequency selectable) Two copies of 27-MHz reference clock output, two copies of 54/53.946053/67.425/68.400599 MHz (frequency selectable) Part Number CY24207-1 CY24207-2 Outputs 4 4 Input Frequency 27-MHz Crystal Input 27-MHz Crystal Input Block Diagram XIN XOUT VCXO P Φ VCO OUTPUT MULTIPLEXER AND DIVIDERS CLK1 CLK2 REFCLK1 REFCLK2 Pin Configuration 16-pin TSSOP XIN VDD AVDD VCXO AVSS VSSL REFCLK2 REFCLK1 1 2 16 15 XOUT OE FS1 VSS CLK1 VDDL FS0 CLK2 OSC. Q 24207-1,-2 3 4 5 6 7 8 14 13 12 11 10 9 PLL FS0 FS1 OE VDDL VDD AVDD AVSS VSS VSSL Frequency Select Options OE 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CLK1/CLK2 (-1)[1] off off off off 54 53.946053 (–1 ppm) 67.425 67.357642 (3.8 ppm) CLK1/CLK2 (-2)[1] off off off off 54 53.946053 (–1 ppm) 67.425 68.400599(–8.8 ppm) REFCLK 1/2 27 27 27 27 27 27 27 27 Unit MHz MHz MHz MHz MHz MHz MHz MHz Note: 1. “off” = output is driven high. Cypress Semiconductor Corporation Document #: 38-07553 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 31, 2003 CY24207 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 9 10 11 12 12 13 14 15 16 XIN VDD AVDD VCXO AVSS VSSL REFCLK2 REFCLK1 CLK1 (–1) CLK1 (–2) FS0 VDDL CLK2 (–1) CLK2 (–2) VSS FS1 OE XOUT Name Reference crystal input Voltage supply Analog voltage supply Input analog control for VCXO Analog ground CLK ground Reference clock output Reference clock output 54/53.946053/67.425/67.357642 MHz clock output (frequency selectable) 54/53.946053/67.425/68.400599 MHz clock output (frequency selectable) Frequency Select 0, weak internal pull-up CLK voltage supply 54/53.946053/67.425/67.357642 MHz clock output (frequency selectable) 54/53.946053/67.425/68.400599 MHz clock output (frequency selectable) Ground Frequency Select 1, weak internal pull-up Output Enable, weak internal pull-up Reference crystal output Description Document #: 38-07553 Rev. *A Page 2 of 6 CY24207 Absolute Maximum Conditions Supply Voltage (VDD, AVDDL, VDDL)..................–0.5 to +7.0V DC Input Voltage........................................ –0.5V to VDD+0.5 Storage Temperature (Non-condensing).....–55°C to +125°C Junction Temperature ................................ –40°C to +125°C Data Retention @ Tj = 125°C................................> 10 years Package Power Dissipation...................................... 350 mW ESD (Human Body Model) MIL-STD-883.................... 2000V (Above which the useful life may be impaired. For user guidelines, not tested.) Pullable Crystal Specifications Parameter FNOM CLNOM R1 R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Description Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Ratio of third overtone mode ESR to fundamental mode ESR Crystal drive level Fundamental mode Ratio used because typical R1 values are much less than the maximum spec No external series resistor assumed 300 –150 7 180 14.4 18 250 21.6 fF 3 0.5 2 mW ppm ppm pF Conditions Parallel resonance, fundamental mode, AT cut Min. Typ. 27.0 14 25 Max. Units MHz pF Ω Third overtone separation from 3*FNOM High side Third overtone separation from 3*FNOM Low side Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance Recommended Operating Conditions Parameter VDD/AVDDL/VDDL TA CLOAD tPU Operating Voltage Ambient Temperature Max. Load Capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min. 3.135 0 Typ. 3.3 Max. 3.465 70 15 500 Unit V °C pF ms DC Electrical Specifications Parameter2 IOH IOL VIH VIL IVDD IVDDL CIN f∆XO VVCXO RUP Name Output High Current Output Low Current Input High Voltage Input Low Voltage Supply Current Supply Current Input Capacitance VCXO pullability range VCXO input range Pull-up resistor on inputs VDD = 3.14 to 3.47V, measured at VIN = 0V 0 100 Description VOH = VDD – 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V CMOS levels, 70% of VDD CMOS levels, 30% of VDD AVDD/VDD Current VDDL Current (VDDL = 3.47V) excluding XIN and XOUT ±200 VDD 150 Min. 12 12 0.7 0.3 25 20 7 Typ. 24 24 Max. Unit mA mA VDD VDD mA mA pF ppm V kΩ Document #: 38-07553 Rev. *A Page 3 of 6 CY24207 AC Electrical Specifications Parameter[2] DC ER EF t9 t10 Name Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. CLK1, CLK2 Peak-Peak period jitter Min. 45 0.8 0.8 Typ. 50 1.4 1.4 120 3 Max. 55 Unit % V/ns V/ns ps ms Test and Measurement Set-up VDDs 0.1 µF DUT Outputs CLOAD GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD 20% of V DD 0V Clock Output Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Note: 2. Not 100% tested. Document #: 38-07553 Rev. *A Page 4 of 6 CY24207 Ordering Information Ordering Code CY24207ZC-1 CY24207ZC-1T CY24207ZC-2 CY24207ZC-2T Package Type 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP Operating Range Commercial Commercial Commercial Commercial Operating Voltage 3.3V 3.3V 3.3V 3.3V Package Drawing and Dimensions 16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 51-85091-** MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders Document #: 38-07553 Rev. *A Page 5 of 6 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY24207 Document History Page Document Title: CY24207 MediaClock™ PDP Clock Generator Document Number: 38-07553 REV. *.* *A ECN NO. 127230 128248 Issue Date 06/26/03 07/31/03 Orig. of Change RGL New Data Sheet Description of Change IJATMP Added -2 part number Added CLK1/CLK2 (-2) column to Frequency Select Options Added new definitions for Pins 9 and 12 in Pin Description table Document #: 38-07553 Rev. *A Page 6 of 6