CY2DP814ZC

ComLink™ Series CY2DP814 1:4 Clock Fanout Buffer Features Low voltage operation VDD = 3.3V 1:4 fanout Single-input configurable for LVDS, LVPECL, or LVTTL Four differential pairs of LVPECL outputs Drives 50-ohm load Low input capacitance Low output skew Low propagation delay — Typical (tpd < 4 ns) • Industrial versions available • Available packages include TSSOP, SOIC • • • • • • • • • Description The Cypress CY2 series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. The Cypress CY2DP814 fanout buffer features a single LVDSor a single LVPECL-compatible input and four LVPECL output pairs. Designed for data communications clock management applications, the fanout from a single input reduces loading on the input clock. The CY2DP814 is ideal for both level translations from single-ended to LVPECL and/or for the distribution of LVDS-based clock signals. The Cypress CY2DP814 has configurable input between logic families. The input can be selectable for an LVPECL/LVTTL or LVDS signal, while the output drivers support LVPECL capable of driving 50-ohm lines. Block Diagram Pin Configuration EN1 1 EN2 8 16 Q1A 15 Q1B EN1 CONFIG VDD VDD GND IN+ IN- IN+ 6 IN- 7 LVDS / LVPECL / LVTTL CONFIG 2 14 Q2A 13 Q2B 12 Q3A 11 Q3B EN2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B 10 Q4A 9 Q4B 16 pin TSSOP / SOIC OUTPUT LVPECL Cypress Semiconductor Corporation Document #: 38-07060 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 15, 2002 CY2DP814 ComLink™ Series CY2DP814 Pin Description Pin Number 6, 7 2 Pin Name IN+, IN– CONFIG Pin Standard Interface Configurable LVTTL/LVCMOS Description Differential input pair or single line. LVPECL default. See CONFIG below. Converts inputs from the default LVPECL/LVDS (logic = 0) to LVTTL/LVCMOS (logic = 1). See Figure 6 and Figure 7 for additional information Enable/disable logic. See Function Table below for details. Differential outputs. 1, 8 16, 15, 14, 13, 12, 11, 10, 9 EN1, EN2 Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B VDD GND LVTTL/LVCMOS LVPECL 3, 4 5 POWER POWER Positive supply voltage. Ground. Document #: 38-07060 Rev. *B Page 2 of 9 ComLink™ Series CY2DP814 Maximum Ratings[1][2] Storage Temperature: ................................. –65°C to +150°C Ambient Temperature:................................... –40°C to +85°C Supply Voltage to Ground Potential (Inputs and VCC only)....................................... –0.3V to 4.6V Supply Voltage to Ground Potential Table 1. EN1 EN2 Function Table Enable Logic EN1 H H L L EN2 H L L H IN+ H H H X Input IN– L L L X QnA H H H Z Outputs QnB L L L Z (Outputs only) ........................................ –0.3V to VDD + 0.3V DC Input Voltage ................................... –0.3V to VDD + 0.3V DC Output Voltage................................. –0.3V to VDD + 0.9V Power Dissipation........................................................ 0.75W Table 2. Input Receiver Configuration for Differential or LVTTL/LVCMOS CONFIG Pin 2 Binary Value 1 0 Input Receiver Family LVTTL in LVCMOS LVDS LVPECL Input Receiver Type Single ended, non-inverting, inverting, void of bias resistors. Low voltage differential signaling Low voltage pseudo (positive) emitter coupled logic Table 3. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal LVTTL/LVCMOS INPUT LOGIC Input Condition Ground VCC Ground VCC IN- Pin 7 IN+ Pin 6 IN- Pin 7 IN+ Pin 6 IN+ Pin 6 IN- Pin 7 IN+ Pin 6 Input Test Conditions True Min. Typ. Max. 1.5 90 2.0 100 Unit mA/MHz mA IN- Pin 7 Table 4. Power Supply Characteristics Parameter ICCD IC Description Input Invert Input Invert Input True Input Logic Output Logic Q pins Dynamic Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Loaded Total Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Loaded, fL= 100 MHz Table 5. D.C. Electrical Characteristics: 3.3V–LVDS Input Parameter VID VIC IIH IIL II Description Magnitude of Differential Input Voltage Common-Mode of Differential Input Voltage IVIDI (min. and max.) Input High Current Input Low Current Input High Current VDD = Max. VDD = Max. VDD = Max., VIN = VDD(max.) VIN = VDD VIN = VSS Conditions Min. Typ. Max. Unit 100 IVIDI /2 600 mV 2.4– (IVIDI /2) ±10 ±0 ±20 ±20 ±20 V uA uA uA Notes: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07060 Rev. *B Page 3 of 9 ComLink™ Series CY2DP814 Table 6. D.C. Electrical Characteristics: 3.3V–LVPECL Input Parameter I VID I Description Differential Input Voltage p-p Common-mode Voltage Input High Current Input Low Current Input High Current VDD = Max. VDD = Max. Condition Guaranteed Logic High Level VIN = VDD VIN = VSS Min. 400 1650 Typ. Max. 2600 2250 Unit mV mV uA uA uA VCM IIH IIL II ±10 ±10 ±20 ±20 ±20 VDD = Max., VIN = VDD(max.) Table 7. D.C Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input Parameter VIH VIL IIH IIL II VIK VH Description Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Input Hysteresis Condition Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(max.) VDD = Min., IIN = –18 mA –0.7 80 VIN = 2.7V VIN = 0.5V Min. 2 0.8 1 –1 20 –1.2 Typ. Max. Unit V V uA uA uA V mV Table 8. D.C Electrical Characteristics: 3.3V–LVPECL Output Parameter I VOD I I VOC I Description Driver Differential Output Voltage p-p Driver common-mode p-p Differential 20% to 80% Output High Voltage Output Low Voltage Short Circuit Current Condition VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL CL–10 pF RL and CL to GND Min. RL = 50 ohm RL = 50 ohm RL = 50 ohm IOH = –12 mA 300 2.1 –125 1000 Typ. Max. Unit 3600 226 800 3.0 –150 mV mV pS V V mA Rise Time Fall Time VOH VOL IOS VDD = Min., VIN = VIH or VIL User-defined (see Figure 1) VDD = Max., VOUT = GND Table 9. AC Switching Characteristics @ 3.3V VDD = 3.3V ±5%, Temperature = –40°C to +85°C Parameter IN [+,-] to Q[A,B] Data & Clock Speed tPLH tPHL tPD tPE Tpd tSK(0) tSK(p) tSK(t) Propagation Delay–Low to High Propagation Delay–High to Low Propagation Delay Enable (EN) to functional operation Functional operation to Disable Output Skew: Skew between outputs of the same package (in phase) Pulse Skew: Skew between opposite transitions of the same output (tPHL–tPLH) Package Skew: Skew between outputs of different packages at the VID = 100 mV same power supply voltage, temperature and package type. Same input signal level and output load. 0.2 1 VOD = 100 mV 3 3 3 4 4 4 5 5 5 6 5 0.2 nS nS ns nS nS nS nS nS Description Conditions Min. Typ. Max. Unit EN [1,2] to Q[A,B] Control Speed Document #: 38-07060 Rev. *B Page 4 of 9 ComLink™ Series CY2DP814 VDD - 2V VDD Q Q Device concept User Defined VTT & RTT Figure 1. Differential PECL Output Table 10. High-frequency Parametrics Parameter Fmax Description Maximum Frequency VDD = 3.3V Maximum Frequency VDD = 3.3V Minimum Pulse VDD = 3.3V A P u lse G e ne ra to r Conditions 50% Duty Cycle tW(50–50) Standard Load Circuit 20% Duty Cycle tW(20–80) LVPECL Input Vin = VIH(Max.)/VIL(Min.) Vout = VOH(Min.)/VOL (Max.) (Limit) LVPECL Input Vin = VIH(Max.)/VIL(Min.) F = 100 MHz Vout = VOH(Min.)/VOL(Max.).(Limit) TPA Min. Typ. Max. 450 Unit MHz Fmax(20) 175 MHz TW 900 pS 150 10pF B 150 GND 50 T PC V D D -2V 50 TP B En1 En2 S tand ard Te rm in ation V1A 1 .2 V C M 1.4 V 0 V D if f e re n tia l V1B V 0Y 1 .2 V C M 1.0 V 1.4 V 0 V D if f e re n tia l V 0Z T P LH T PHL 1.0 V 80% 0 V D if f e r e n tia l V0Y V0Z t R t F 20% Figure 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3, 4, 5, 6, 7] Notes: 3. RL = 50 ohm ± 1%; Zline = 50 ohm 6 = Ó. 4. CL includes instrumentation and fixture capacitance within 6 mm of the UT. 5. TPA and B are used for prop delay and rise/fall measurements. TPC is used for VOC measurements only and otherwise connected to VDD – 2. 6. When measuring Tr/Tf, tpd, VOD point TPC is held at VDD – 2.0V. 7. LVCMOS/LVTTL single-ended input value. Ground either input: when on the B side, non-inversion takes place. If A side is grounded, the signal becomes the complement of the input on B side. See Table 3. Document #: 38-07060 Rev. *B Page 5 of 9 ComLink™ Series CY2DP814 A P u ls e G e n e ra to r TPA 150 B 150 GND 50 TPC 50 TPB En1 En2 VOC VOD S ta n d a rd T e rm in a tio n V I(A ) V I(B ) 1 .4 V 1 .0 V V o c (p p ) VDD V o c (s s ) Figure 3. Test Circuit & Voltage Definitions for the Driver Common-mode Output Voltage[3, 4, 5, 7, 8] A Pulse Generator TPA 150 10pF B 150 GND 50 TPC VDD-2V 50 TPB En1 En2 Standard Termination VI(A) VI(B) 1.4V 1.0V 100% 80% 0.0V 20% 0% tF tR Figure 4. Test Circuit & Voltage Definitions for the Differential Output Signal [3, 4, 5, 6, 7] P ulse G enerator P ulse G enerator VOC TPA 50 TPC VDD-2V 50 TPB En1 En2 + DE Parallel Termination Q tpd tpe Figure 5. Test Circuit & Voltage Definitions for the Driver Common-Mode Output Voltage[3, 4, 5, 8, 9] Notes: 8. VOC measurement requires equipment with a 3-dB bandwidth of at least 300 MHz. 9. All input pulses are supplied by a frequency generator with the following characteristics: TR and tF ≤ 1 nS; pulse re-rate = 50 Mpps; pulse width = 10 ± 0.2 nS. Document #: 38-07060 Rev. *B Page 6 of 9 ComLink™ Series CY2DP814 INPUT A LVCM OS / LVTTL INPUT B GND LVPECL & LVDS In C o n fig InConfig 0 1 L V D S /L V P E C L LVTTL/LVCMOS Figure 6. [7] Figure 7. [10] Package Type 16-pin TSSOP 16-pin TSSOP–Tape and Reel 16-pin SOIC 16-pin SOIC–Tape and Reel 16-pin TSSOP 16-pin TSSOP–Tape and Reel 16-pin SOIC 16-pin SOIC–Tape and Reel Product Flow Industrial, –40°C to 85°C Industrial, –40°C to 85°C Industrial, –40°C to 85°C Industrial, –40°C to 85°C Commercial, 0°C to 70 °C Commercial, 0°C to 70 °C Commercial, 0°C to 70 °C Commercial, 0°C to 70 °C Ordering Information Part Number CY2DP814ZI CY2DP814ZIT CY2DP814SI CY2DP814SIT CY2DP814ZC CY2DP814ZCT CY2DP814SC CY2DP814SCT Package Drawing and Dimensions 16-lead (150-mil) Molded SOIC S16 51-85068-A Note: 10. LVPECL or LVDS differential input value. Document #: 38-07060 Rev. *B Page 7 of 9 ComLink™ Series CY2DP814 Package Drawings and Dimensions (continued) 16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 51-85091 All product and company names mentioned in this document are the trademarks of their respective holders.cv Document #: 38-07060 Rev. *B Page 8 of 9 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. ComLink™ Series CY2DP814 Document Title: ComLink™Series CY2DP814 1:4 Clock Fanout Buffer Document Number: 38-07060 REV. ** *A *B ECN No. 10785 115610 122746 Issue Date 06/07/01 07/02/02 12/15/02 Orig. of Change IKA CTK RBI Range of VCM Added power-up requirements to maximum ratings information. Description of Change Convert from IMI to Cypress Document #: 38-07060 Rev. *B Page 9 of 9