CY2DP818ZC-2T

PRELIMINARY CY2DP818-2 1:8 Clock Fanout Buffer Features • Low-voltage operation VDD = 3.3V • 1:8 fanout • Single-input-configurable for LVDS, LVPECL, or LVTTL • 8 pairs of LVPECL outputs with enable/disable • Drives a 50-ohm load • Low input capacitance • Low output skew • Low propagation delay Typical (tpd < 4 ns) • Industrial versions available • Package available include: TSSOP • Does not exceed Bellcore 802.3 standards • Operation up to 350 MHz/700 Mbps Description This Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. The Cypress CY2DP818-2 fanout buffer features a single LVDS or a single-ended LVTTL-compatible input and eight LVPECL output pairs. Designed for data-communications clock-management applications, the large fanout from a single input reduces loading on the input clock. The CY2DP818-2 is ideal for both level translations from single-ended to LVPECL and/or for the distribution of LVPECL-based clock signals. The Cypress CY2DP818-2 has configurable input functions. The input is user-configurable via the Inconfig pin for single ended or differential input. Block Diagram EN1 Q1A Q1B EN2 Q2A Q2B EN3 Pin Configuration INPUT (LVPECL / LVDS / LVTTL) Q3A Q3B Q4A GND VDD EN1 EN2 EN3 EN4 InConfig VDD GND INPUT A INPUT B GND VDD EN5 EN6 EN7 VDD GND GND EN4 INPUT A INPUT B EN5 Q5A Q4B InConfig EN6 Q5B Q6A Q6B EN7 Q7A Q7B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 GND Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B VDD Q5A Q5B Q6A Q6B Q7A Q7B Q8A Q8B GND Q8A Q8B 38-pin TSSOP CY2DP818-2 OUTPUT (LVPECL) Cypress Semiconductor Corporation Document #: 38-07588 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 5, 2003 PRELIMINARY Pin Description Pin Number 2,8,13,29,17 3,4,5,6,14,15,16 VDD EN(1:7) Pin Name Pin Standard Interface POWER POWER LVTTL/LVCMOS Ground Power Supply CY2DP818-2 Description 1, 9,12,18,19,20,38 GND The respective outputs are enabled when these pins are pulled high. Outputs are disabled when connected to GND. EN7 controls both Q7(A,B) and Q8(A,B) Differential input pair or single line. LVPECL/LVDS default. See InConfig, below. Differential Outputs 10,11 Input A, Input B Default: LVPECL/LDVS Optional: LVTTL/LVCMOS single pin LVPECL 37, 36,35,34, 33,32,31, 30, 28,27,26,25, 24,23,22,21 7 Q1(A,B), Q2(A,B) Q3(A,B), Q4(A,B) Q5(A,B), Q6(A,B) Q7(A,B), Q8(A,B) InConfig LVTTL/LVCMOS Converts inputs from the default LVPECL/LVDS (logic = 0) to LVTTL/LVCMOS (logic = 1) See Input Receiver Configuration for Differential or LVTTL/LVCMOS table (below), Figure 5 and Figure 6 for additional Information Power Supply Characteristics Parameter ICCD IC Description Dynamic Power Supply Current Total Power Supply Current Test Conditions VDD = Max. Input toggling 50% Duty Cycle, Outputs Open VDD = Max. Input toggling 50% Duty Cycle, Outputs 50 ohms, fL=100 MHz Min. Typ. Max. 1.5 2.0 350 Unit mA/ MHz mA IC Core Core current when output loads are VDD = Max. Input toggling 50% Duty Cycle, Outputs Disabled, disabled not connected to VTT fL = 100 MHz 50 mA Input Receiver Configuration for Differential or LVTTL/LVCMOS INCONFIG Pin 7 Binary Value 1 0 Input Receiver Family LVTTL in LVCMOS LVDS LVPECL Input Receiver Type Single-ended, non-inverting, inverting, void of bias resistors Low-voltage differential signaling Low-voltage pseudo (positive) emitter coupled logic Function Control of the TTL Input Logic used to Accept or Invert the Input Signal LVTTL/LVCMOS Input Logic Input Condition Ground VDD Ground VDD Input B (–) Pin 11 Input A (+) Pin 10 Input B (–) Pin 11 Input A (+) Pin 10 Input A (+) Pin 10 Input B (–) Pin 11 Input A (+) Pin 10 Input B (–) Pin 11 Input True Input Invert Input Invert Input True Input Logic Output Logic Q Pins, Q1A or Q1 Document #: 38-07588 Rev. ** Page 2 of 8 PRELIMINARY Absolute Maximum Conditions Parameter VDD VDD VIN VOUT VTT TS TA Description DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Temperature, Storage Temperature, Operating Ambient Commercial Industrial Non-functional Functional Functional Outputs Relative to VSS, with or VDD applied Relative to VSS Condition Inputs and VCC CY2DP818-2 Min. –0.3 –0.3 –0.3 –0.3 – –65 0 –40 Max. 4.6 VDD + 0.3 VDD + 0.3 VDD + 0.9 VDD ÷ 2 +150 70 +85 Unit V V V V V °C °C Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications (3.3V – LVDS Input @ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) Parameter VID VIC IIH IIL Description Magnitude of Differential Input Voltage Common-mode of Differential Input VoltageIVIDI (min. and max.) Input High Current Input Low Current VDD = Max. VDD = Max. VIN = VDD VIN = VSS Conditions Min. 100 Typ. Max. 600 Unit mV V µA µA IVIDI/2 2.4–(IVIDI/2) – – ±10 ±10 ± 20 ± 20 DC Electrical Specifications (3.3V – LVPECL Input @ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) Parameter VID VIH VIL IIH IIL VCM Description Differential Input Voltage p-p Input High Voltage Input Low Voltage Input High Current Input Low Current Common-mode Voltage Conditions Guaranteed Logic High Level Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VIN = VDD VIN = VSS Min. 400 2.15 1.5 – – 1650 Typ. – – – ±10 ±10 – Max. 2600 2.4 1.8 ±20 ±20 2250 Unit mV V V µA µA mV DC Electrical Specifications (3.3V – LVTTL/LVCMOS Input @ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) Parameter VIH VIL IIH IIL II VIK VH Description Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Input Hysteresis[1] Conditions Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max VDD = Max VDD = Max., VIN = VDD (Max.) VDD = Min., IIN = –18 mA – – –0.7 80 –1.2 V mV VIN = 2.7V VIN = 0.5V Min. 2 – – – Typ. – – – – Max. – 0.8 1 –1 Units V V µA µA DC Electrical Specifications (3.3V – LVPECL Output @ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) Parameter VOD ∆VOC Description Conditions RL = 50 ohm RL = 50 ohm Min. 1000 – Typ. – – Max. 3600 300 Unit mV mV Driver Differential Output VDD = Min., VIN = VIH or VIL voltage p-p Driver common-mode variation p-p VDD = Min., VIN = VIH or VIL Note: 1. Guaranteed but not tested. Document #: 38-07588 Rev. ** Page 3 of 8 PRELIMINARY Parameter Rise Time Fall Time VOH VOL IOS Output High Voltage Output Low Voltage Short Circuit Current VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL User-defined by VTT RTT. VDD = Max, VOUT = GND IOH = –12 mA 2.1 0.8 – Description Differential 20% to 80% Conditions CL–10 pF RL and CL to GND RL = 50 ohm Min. 300 CY2DP818-2 Typ. Max. 1200 – – – 3.0 1.3 –150 Unit ps V V mA DC Electrical Specifications (3.3V – LVPECL Output @ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) (continued) AC Switching Characteristics (@ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) Parameter tPLH tPHL TPE TPD tSK(0) tSK(p) tSK(t) Description Propagation Delay – Low to High Propagation Delay – High to Low Enable (EN) to functional operation Functional operation to Disable Output Skew: Skew between outputs of the same package (in phase) Pulse Skew: Skew between opposite transitions of the same output (tPHL–tPLH) Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. Same input signal level and output load. VID = 100 mV Conditions VOD = 100 mV Min. 3 3 – – – – – Typ. Max. Unit 4 4 – – – 0.2 – 1 5 5 6 5 0.2 ns ns ns ns ns ns ns High-frequency Parametrics Parameter Fmax Description Maximum frequency VDD = 3.3V Conditions 45%–55% duty cycle Standard load circuit Min. – Typ. – Max. 350 Unit MHz Figure 1. Driver Design Document #: 38-07588 Rev. ** Page 4 of 8 PRELIMINARY A Pulse Generator TPA CY2DP818-2 50 TPC VDD-2V 150 10pF B 150 GND 50 TPB Standard Termination INA 1.2 V CM 1.4 V 0V Differential INB QXA 1.2 V CM 1.0 V 1.4 V 0V Differential QXB T PLH T PHL 1.0 V 80% 0V Differential QXA - QXB 20% tR tF Figure 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time[2,3,4,5] A Pulse Generator TPA 150 B 150 GND 50 TPC 50 TPB VOC VOD Standard Termination VI(A) VI(B) 2.0V 1.6V Next Device Figure 3. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[2,3,4,5] Notes: 2. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF ≤ 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns. 3. RL = 50 ohm ± 1%; Zline = 50 ohm 6”. 4. CL includes instrumentation and fixture capacitance within 6” of the DUT. 5. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD – 2. Document #: 38-07588 Rev. ** Page 5 of 8 PRELIMINARY A Pulse Generator TPA CY2DP818-2 50 TPC VDD-2V 150 10pF B 150 GND 50 TPB Standard Termination VI(A) VI(B) 1.4V 1.0V 100% 80% 0.0V 20% 0% tF tR Figure 4. Test Circuit and Voltage Definitions for the Differential Output Signal[2,3,4,5] INPUT A LVCM OS / LVTTL INPUT B GND LVPECL & LVDS In C o n fig InConfig 1 LVTTL/LVCMOS Figure 5. [7] 0 L V D S /L V P E C L Figure 6. [7] Ordering Information Part Number CY2DP818ZI-2 CY2DP818ZI-2T CY2DP818ZC-2 CY2DP818ZC-2T Notes: 6. See Table . 7. LVPECL or LVDS differential input value. Package Type 38-pin TSSOP 38-pin TSSOP–Tape and Reel 38-pin TSSOP 38-pin TSSOP–Tape and Reel Product Flow Industrial, –40° to 85°C Industrial, –40° to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Document #: 38-07588 Rev. ** Page 6 of 8 PRELIMINARY Package Drawing and Dimensions 38-lead TSSOP (4.40 mm Body) Z38 CY2DP818-2 51-85151-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07588 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY Document History Page Document Title: CY2DP818-2 1:8 Clock Fanout Buffer Document Number: 38-07588 REV. ** ECN NO. 129879 Issue Date 11/07/03 Orig. of Change RGL New Data Sheet Description of Change CY2DP818-2 Document #: 38-07588 Rev. ** Page 8 of 8