CY62128DV30LL-70ZRI

CY62128DV30 MoBL 1 Mb (128K x 8) Static RAM Features • • • • Very high speed: 55 and 70 ns Wide voltage range: 2.2V to 3.6V Pin compatible with CY62128V Ultra-low active power — Typical active current: 0.85 mA @ f = 1 MHz — Typical active current: 5 mA @ f = fMAX Ultra-low standby power Easy memory expansion with CE1, CE2, and OE features Automatic power-down when deselected Packages offered in a 32-lead SOIC, a 32-lead TSOP, a 32-lead Short TSOP, and a 32-lead Reverse TSOP power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and Write Enable(WE) LOW. Data on the eight I/O pins is then written into the location specified on the Address pin (A0 thro. A16). Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/Oo through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH) or during a write operation (CE1 LOW, CE2 HIGH), and WE LOW). • • • • Functional Description[1] The CY62128DV30 is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces Logic Block Diagram Data in Drivers A0 A1 A2 A3 A4 A5 A 6 A7 A8 A 9 A10 A11 ROW DECODER I/O0 I/O1 SENSE AMPS I/O 2 I/O 3 I/O 4 I/O 5 128K x 8 ARRAY CE1 CE2 WE COLUMN DECODER Powerdown I/O 6 I/O 7 A 12 A 13 A 14 OE Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. A 15 A 16 Cypress Semiconductor Corporation Document #: 38-05231 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised August 29, 2003 CY62128DV30 MoBL Pin Configuration[2] Top View SOIC NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP I Top View (not to scale) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 25 26 27 26 28 29 30 31 32 1 2 3 4 5 6 7 8 STSOP Top View (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CE2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reverse TSOP I Top View (not to scale) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE1 A10 OE Note: 2. NC pins are not connected to the die. Document #: 38-05231 Rev. *C Page 2 of 11 CY62128DV30 MoBL Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential .......................................................... −0.3V to 3.9V DC Voltage Applied to Outputs in High-Z State[3] .................................... −0.3V to VCC + 0.3V DC Input Voltage[3] ................................ −0.3V to VCC + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Operating Range Range Industrial Ambient Temperature (TA) −40°C to +85°C VCC[4] 2.2V to 3.6V Product Portfolio Power Dissipation Operating, Icc (mA) VCC Range (V) Product CY62128DV30L CY62128DV30LL Min. 2.2 Typ. 3.0 Max. 3.6 Speed (ns) 55/70 55/70 f = 1 MHz Typ.[5] 0.85 0.85 Max. 1.5 1.5 5 5 f = fMAX Typ.[5] Max. 10 10 Standby, ISB2 (µA) Typ.[5] 1.5 1.5 Max. 5 4 DC Electrical Characteristics (Over the Operating Range) CY62128DV30-55/70 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current − CMOS Inputs Test Conditions 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz Vcc = 3.6V, IOUT = 0mA, CMOS level IOH = −0.1 mA IOH = −1.0 mA IOL = 0.1 mA IOL = 2.1 mA 1.8 2.2 −0.3 −0.3 −1 −1 5 0.85 1.5 1.5 1.5 1.5 Min. 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 10 1.5 5 4 5 4 µA µA µA µA mA V V V Typ.[5] Max. Unit V ISB1 CE1 > VCC − 0.2V, CE2 < 0.2V, L VIN > VCC − 0.2V, VIN < 0.2V, LL f = fMAX (Address and Data Only), f = 0 (OE, WE,) CE1 > VCC − 0.2V, CE2 < 0.2V, VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC=3.6V L LL ISB2 Automatic CE Power-down Current − CMOS Inputs Capacitance[6] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. 8 8 Unit pF pF Notes: 3. VIL(min.) = −2.0V for pulse durations less than 20 ns., VIH(max.) = Vcc+0.75V for pulse durations less than 20 ns. 4. Full device operation requires linear ramp of Vcc from 0V to Vcc(min) and Vcc must be stable at Vcc(min) for 500 µ s. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 6. Tested initially and after any design or proces changes that may affect these parameters. Document #: 38-05231 Rev. *C Page 3 of 11 CY62128DV30 MoBL Thermal Resistance Parameter θJA θJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case)[6] [6] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board SOIC TSOP I STSOP Unit 69 34 93 17 65 15 °C/W °C/W AC Test Loads and Waveforms R1 VCC OUTPUT CL = 50 pF INCLUDING JIG AND SCOPE Equivalent to: RTH OUTPUT VTH R2 ALL INPUT PULSES VCC Typ 10% GND Rise Time: 1 V/ns 90% 90% 10% Fall Time: 1 V/ns TH ÉVENIN EQUIVALENT Parameters R 1 R 2 RTH VTH 2.5V (2.2 – 2.7V) 16600 15400 8000 1.2 3.0V (2.7 – 3.6V) 1103 1554 645 1.75 Unit Ω Ω Ω V Data Retention Characteristics Parameter VDR ICCDR tCDR[5] tR [7] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions VCC = 1.5V, CE1 > VCC − 0.2V, CE2 < 0.2V, L VIN > VCC − 0.2V or VIN < 0.2V LL Min. 1.5 Typ.[5] Max. Unit V 4 3 µA ns µs 0 100 Data Retention Waveform DATA RETENTION MODE VCC CE1 V CC(min.) tCDR VD R > 1.5V VCC(min.) tR or CE 2 Note: 7. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 us. Document #: 38-05231 Rev. *C Page 4 of 11 CY62128DV30 MoBL Switching Characteristics (Over the Operating Range)[8] CY62128DV30-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[11] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW or CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High Z[9,10] WE HIGH to Low Z[9] 10 55 40 40 0 0 40 25 0 20 10 70 60 60 0 0 50 30 0 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW or CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[9] OE HIGH to High Z[9,10] CE1 LOW or CE2 HIGH to Low Z[9] CE1 HIGH or CE2 LOW to High Z[9,10] CE1 LOW or CE2 HIGH to Power-up CE1 HIGH or CE2 LOW to Power-down 0 55 10 20 0 70 5 20 10 25 10 55 25 5 25 55 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. CY62128DV30-70 Min. Max. Unit Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 8. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t. 10. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 11. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals. 12. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 13. WE is HIGH for Read cycle. Document #: 38-05231 Rev. *C Page 5 of 11 CY62128DV30 MoBL Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[10, 13, 14] ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% ISB tHZOE tHZCE HIGH IMPEDANCE ICC Write Cycle No. 1 (WE Controlled) [11, 15, 16, 17] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE t SD DATA I/O DATA VALID tHD tHA Notes: 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 15. Data I/O is high-impedance if OE = VIH. 16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05231 Rev. *C Page 6 of 11 CY62128DV30 MoBL Switching Waveforms (continued) Write Cycle No. 2 (CE1 or CE2 Controlled) [11, 15, 16, 17] t WC ADDRESS t SCE CE 1 t SA CE 2 t AW t PWE WE t HA OE t SD DATA I/O DATA IN VALID t HD Write Cycle No. 3 (WE Controlled, OE LOW)[10, 16, 17] t WC ADDRESS t SCE CE 1 CE 2 t SCE t AW t SA WE t PWE t HA tSD DATA I/O t HD DON'T CARE t HZWE DATA VALID t LZWE Truth Table CE 1 H X L L L CE 2 X L H H H WE X X H H L OE X X L H X I/O0–I/O7 High Z High Z Data Out High Z Data In Mode Deselect/Power-down Deselect/Power-down Read Output Disabled Write Power Standby (I SB ) Standby (I SB ) Active (I CC) Active (I CC) Active (I CC) Document #: 38-05231 Rev. *C Page 7 of 11 CY62128DV30 MoBL Ordering Information Speed (ns) 55 Ordering Code CY62128DV30L-55SI CY62128DV30LL-55SI CY62128DV30L-55ZI CY62128DV30LL-55ZI CY62128DV30L-55ZAI CY62128DV30LL-55ZAI CY62128DV30L-55ZRI CY62128DV30LL-55ZRI 70 CY62128DV30L-70SI CY62128DV30LL-70SI CY62128DV30L-70ZI CY62128DV30LL-70ZI CY62128DV30L-70ZAI CY62128DV30LL-70ZAI CY62128DV30L-70ZRI CY62128DV30LL-70ZRI Package Name S34 S34 Z32 Z32 ZA32 ZA32 ZR32 ZR32 S34 S34 Z32 Z32 ZA32 ZA32 ZR32 ZR32 32-lead SOIC 32-lead SOIC 32-lead TSOP Type 1 32-lead TSOP Type 1 32-lead Short TSOP Type 1 32-lead Short TSOP Type 1 32-lead Reverse TSOP Type 1 32-lead Reverse TSOP Type 1 32-lead SOIC 32-lead SOIC 32-lead TSOP Type 1 32-lead TSOP Type 1 32-lead Short TSOP Type 1 32-lead Short TSOP Type 1 32-lead Reverse TSOP Type 1 32-lead Reverse TSOP Type 1 Industrial Package Type Operating Range Industrial Package Diagrams 32-Lead (450 MIL) Molded SOIC S34 51-85081-*A Document #: 38-05231 Rev. *C Page 8 of 11 CY62128DV30 MoBL 32-Lead Thin Small Outline Package Type I (8 x 20 mm) Z32 51-85056-*D 32-Lead Shrunk Thin Small Outline Package (8 x 13.4 mm) ZA32 51-85094-*D Document #: 38-05231 Rev. *C Page 9 of 11 CY62128DV30 MoBL 32-Lead Reverse Thin Small Outline Package ZR32 51-85089-*C MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05231 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62128DV30 MoBL Document History Page Document Title: CY62128DV30 MoBL® 1 Mb (128K x 8) Static RAM Document Number: 38-05231 REV. ** *A ECN NO. Issue Date 117691 127314 08/27/02 5/27/03 Orig. of Change JUI MPR New Data Sheet Changed from Advance Information to Preliminary Changed Isb2 to 5 uA (L), 4 uA (LL) Changed Iccdr to 4 uA (L), 3 uA (LL) Changed Cin from 6 pF to 8 pF Changed from Preliminary to Final Add 70-ns speed, updated ordering information Changed Icc 1 MHz typ from 0.5 mA to 0.85 mA Description of Change *B *C 128342 129002 07/23/03 08/29/03 JUI CDY Document #: 38-05231 Rev. *C Page 11 of 11