CY62128DV30LL-70ZXIT

CY62128DV30 1-Mb (128K x 8) Static RAM Features also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) LOW). • Very high speed: 55 and 70 ns • Wide voltage range: 2.2V to 3.6V • Pin compatible with CY62128V • Ultra-low active power — Typical active current: 0.85 mA @ f = 1 MHz — Typical active current: 5 mA @ f = fMAX • Ultra-low standby power Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and Write Enable (WE) LOW. Data on the eight I/O pins is then written into the location specified on the Address pin (A0 through A16). • Easy memory expansion with CE1, CE2, and OE features • Automatic power-down when deselected Functional Description[1] Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The CY62128DV30 is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device The eight input/output pins (I/Oo through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH) or during a write operation (CE1 LOW, CE2 HIGH), and WE LOW). • Available in Pb-free and non Pb-free 32-lead SOIC, 32-lead TSOP and 32-lead Small TSOP, non Pb-free 32-lead Reverse TSOP packages Logic Block Diagram I/O0 Data in Drivers I/O1 I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 128K x 8 ARRAY I/O3 I/O4 I/O5 CE1 CE2 COLUMN DECODER Powerdown I/O6 I/O7 OE A 15 A 16 A 12 A 13 A 14 WE Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05231 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 19, 2006 CY62128DV30 Pin Configurations[2] Top View SOIC DNU A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 A11 A9 A8 A13 WE CE2 A15 VCC DNU A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TSOP I Top View (not to scale) A4 A5 A6 A7 A12 A14 A16 DNU VCC A15 CE2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A11 A9 A8 A13 WE CE2 A15 VCC DNU A16 A14 A12 A7 A6 A5 A4 25 26 27 26 28 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 STSOP Top View (not to scale) A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE1 A10 OE 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Reverse TSOP I Top View (not to scale) OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Product Portfolio Power Dissipation Operating, ICC (mA) VCC Range (V) Product CY62128DV30L f = 1 MHz f = fMAX Standby, ISB2 (µA) Min. Typ. Max. Speed (ns) 2.2 3.0 3.6 55/70 0.85 1.5 5 10 1.5 5 55/70 0.85 1.5 5 10 1.5 4 CY62128DV30LL Typ.[4] Max. Typ.[4] Max. Typ.[4] Max. Notes: 2. NC pins are not connected to the die. 3. DNU pins have to be left floating or tied to Vss to ensure proper application. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 38-05231 Rev. *H Page 2 of 11 CY62128DV30 Maximum Ratings DC Input Voltage[5] ................................ −0.3V to VCC + 0.3V (Above which the useful life may be impaired. For user guidelines, not tested.) Output Current into Outputs (LOW)............................. 20 mA Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage to Ground Potential .......................................................... −0.3V to 3.9V DC Voltage Applied to Outputs in High-Z State[5] ....................................−0.3V to VCC + 0.3V Range Ambient Temperature (TA) VCC[6] Industrial −40°C to +85°C 2.2V to 3.6V DC Electrical Characteristics (Over the Operating Range) CY62128DV30-55/70 Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions IOH = −0.1 mA 2.0 2.7 < VCC < 3.6 IOH = −1.0 mA 2.4 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 2.7 < VCC < 3.6 IOL = 2.1 mA 0.4 Input HIGH Voltage 2.2 < VCC < 2.7 VIL Input LOW Voltage V V 1.8 VCC + 0.3 2.7 < VCC < 3.6 2.2 VCC + 0.3 2.2 < VCC < 2.7 −0.3 0.6 2.7 < VCC < 3.6 −0.3 0.8 −1 +1 IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current f = fMAX = 1/tRC ISB2 Unit Max. 2.2 < VCC < 2.7 VIH ISB1 Typ.[4] Min. f = 1 MHz −1 V V µA +1 µA 5 10 mA 0.85 1.5 1.5 5 1.5 4 L 1.5 5 LL 1.5 4 VCC = 3.6V, IOUT = 0mA, CMOS level Automatic CE Power-down Current − CMOS Inputs CE1 > VCC − 0.2V, CE2 < 0.2V, L VIN > VCC − 0.2V, VIN < 0.2V, LL f = fMAX (Address and Data Only), f = 0 (OE, WE,) Automatic CE Power-down Current − CMOS Inputs CE1 > VCC − 0.2V, CE2 < 0.2V, VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC=3.6V µA µA Capacitance[7] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. Unit 8 pF 8 pF Thermal Resistance[7] Parameter θJA θJC Description Thermal Resistance (Junction to Ambient) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit Thermal Resistance (Junction to Case) board SOIC TSOP I RTSOP STSOP Unit 69 93 93 65 °C/W 34 17 17 15 °C/W Notes: 5. VIL(min.) = −2.0V for pulse durations less than 20 ns. VIH(max.) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device operation requires linear ramp of VCC from 0V to VCC(min) and VCC must be stable at VCC(min) for 500 µ s. 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05231 Rev. *H Page 3 of 11 CY62128DV30 AC Test Loads and Waveforms[8] R1 VCC OUTPUT VCC 10% GND Rise Time = 1 V/ns R2 50 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Parameters 2.5V (2.2V - 2.7V) 3.0V (2.7V - 3.6V) Unit R1 16600 1103 Ω R2 15400 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current Conditions Min. Typ.[4] Max. Unit 1.5 VCC = 1.5V, CE1 > VCC − 0.2V, CE2 < 0.2V, L VIN > VCC − 0.2V or VIN < 0.2V LL tCDR[4] Chip Deselect to Data Retention Time tR[8] Operation Recovery Time V 4 µA 3 0 ns 100 µs Data Retention Waveform DATA RETENTION MODE VCC V CC(min.) tCDR VDR > 1.5V VCC(min.) tR CE1 or CE 2 Note: 8. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs. Document #: 38-05231 Rev. *H Page 4 of 11 CY62128DV30 Switching Characteristics (Over the Operating Range)[9] CY62128DV30-55 Parameter Description Min. Max. CY62128DV30-70 Min. Max. Unit Read Cycle tRC Read Cycle Time 55 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW or CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns 25 ns 55 10 [10] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[10, 11] tLZCE CE1 LOW or CE2 HIGH to Low Z[10] 70 10 CE1 HIGH or CE2 LOW to High tPU CE1 LOW or CE2 HIGH to Power-up tPD CE1 HIGH or CE2 LOW to Power-down ns 10 20 0 ns 25 0 55 ns ns 5 20 Z[10, 11] ns 10 5 tHZCE Write Cycle 70 ns ns 70 ns [12] tWC Write Cycle Time 55 70 ns tSCE CE1 LOW or CE2 HIGH to Write End 40 60 ns tAW Address Set-up to Write End 40 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 40 50 ns tSD Data Set-up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns tHZWE tLZWE WE LOW to High Z[10, 11] WE HIGH to Low Z[10] 20 10 25 10 ns ns Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 9. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals. 13. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 14. WE is HIGH for Read cycle. Document #: 38-05231 Rev. *H Page 5 of 11 CY62128DV30 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[11, 14, 15] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE ICC 50% 50% ISB Write Cycle No. 1 (WE Controlled)[12, 16, 17, 18] ADDRESS tSCE CE1 CE2 tSCE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 18 tHD DATAIN VALID Notes: 15. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 16. Data I/O is high-impedance if OE = VIH. 17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05231 Rev. *H Page 6 of 11 CY62128DV30 Switching Waveforms (continued) Write Cycle No. 2 (CE1 or CE2 Controlled)[12, 16, 17, 18] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tHA tPWE WE t SD DATA I/O tHD DATA VALID Write Cycle No. 3 (WE Controlled, OE LOW)[10, 16, 17] t WC ADDRESS t SCE CE 1 CE 2 t SCE t AW t SA t HA t PWE WE tSD DATA I/O DON'T CARE t HD DATA VALID t LZWE t HZWE Truth Table CE1 CE2 WE OE I/O0-I/O7 MOde Power H X X X High Z Deselet/Power-down Standby (ISB) X L X X High Z Deselet/Power-down Standby (ISB) L H H L Data out Read Active (ICC) L H H H High Z Output Disabled Active (ICC) L H L X Data In Write Active (ICC) Document #: 38-05231 Rev. *H Page 7 of 11 CY62128DV30 Ordering Information Speed (ns) 55 70 Ordering Code Package Diagram Package Type CY62128DV30L-55SI 51-85081 32-lead SOIC CY62128DV30LL-55SI 51-85081 32-lead SOIC CY62128DV30LL-55SXI 51-85081 32-lead SOIC (Pb-Free) CY62128DV30L-55ZI 51-85056 32-lead TSOP Type 1 CY62128DV30LL-55ZI 51-85056 32-lead TSOP Type 1 CY62128DV30LL-55ZXI 51-85056 32-lead TSOP Type 1 (Pb-Free) CY62128DV30L-55ZAI 51-85094 32-lead Small TSOP CY62128DV30LL-55ZAI 51-85094 32-lead Small TSOP CY62128DV30LL-55ZAXI 51-85094 32-lead Small TSOP (Pb-Free) CY62128DV30L-55ZRI 51-85089 32-lead Reverse TSOP CY62128DV30LL-55ZRI 51-85089 32-lead Reverse TSOP CY62128DV30LL-55ZRXI 51-85089 32-lead Reverse TSOP CY62128DV30L-70SI 51-85081 32-lead SOIC CY62128DV30LL-70SI 51-85081 32-lead SOIC CY62128DV30LL-70SXI 51-85081 32-lead SOIC (Pb-Free) CY62128DV30L-70ZI 51-85056 32-lead TSOP Type 1 CY62128DV30LL-70ZI 51-85056 32-lead TSOP Type 1 CY62128DV30LL-70ZXI 51-85056 32-lead TSOP Type 1 (Pb-Free) CY62128DV30L-70ZAI 51-85094 32-lead Small TSOP CY62128DV30LL-70ZAI 51-85094 32-lead Small TSOP CY62128DV30LL-70ZAXI 51-85094 32-lead Small TSOP (Pb-Free) CY62128DV30L-70ZRI 51-85089 32-lead Reverse TSOP CY62128DV30LL-70ZRI 51-85089 32-lead Reverse TSOP Document #: 38-05231 Rev. *H Operating Range Industrial Page 8 of 11 CY62128DV30 Package Diagrams 32 LD (450 Mil) SOIC32-Lead (450-Mil) SOIC (51-85081) 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] MIN. MAX. DIMENSIONS IN INCHES[MM] PACKAGE WEIGHT 1.42gms PART # S32.45 STANDARD PKG. SZ32.45 LEAD FREE PKG. 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] SEATING PLANE 51-85081-*B 32-Lead TSOP Type I (8 x 20 mm) (51-85056) 51-85056-*D Document #: 38-05231 Rev. *H Page 9 of 11 CY62128DV30 Package Diagrams (continued) 32-Lead STSOP (8 x 13.4 mm) (51-85094) 51-85094-*D 32-Lead RTSOP (51-85089) 51-85089-*C MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05231 Rev. *H Page 10 of 11 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62128DV30 Document History Page Document Title: CY62128DV30 1-Mb (128K x 8) Static RAM Document Number: 38-05231 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 117691 08/27/02 JUI New Data Sheet *A 127314 5/27/03 MPR *B 128342 07/23/03 JUI Changed from Preliminary to Final Add 70-ns speed, updated ordering information Changed from Advance Information to Preliminary Changed Isb2 to 5 µA (L), 4 µA (LL) Changed Iccdr to 4 µA (L), 3 µA (LL) Changed Cin from 6 pF to 8 pF *C 129002 08/29/03 CDY Changed Icc 1 MHz typ from 0.5 mA to 0.85 mA *D 347394 See ECN PCI Added Lead-Free Packages in Ordering Information Table *E 395936 See ECN SYT Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Corrected CE1 and CE2 waveforms on Write Cycle No.1 on Page# 6. Edited the Write Cycle No.1 switching waveform Data I/O to include Don’t Care Condition on Page# 6 Updated the ordering information on Page # 8 *F 428906 See ECN AJU Added Thermal Resistance numbers for RTSOP package Updated Ordering Information table by replacing Package Name column with Package Diagram *G 464721 See ECN NXR Updated the Block Diagram on page # 1 *H 470383 See ECN NXR Changed pin# 1 of SOIC and STSOP I, pin # 9 of TSOP I and RTSOP I from NC to DNU and added footnote# 3 Document #: 38-05231 Rev. *H Page 11 of 11