CY62256

CY62256 256K (32K x 8) Static RAM Features • Temperature Ranges — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C • • • • • • • • • — Automotive: –40°C to 125°C High speed: 55 ns and 70 ns Voltage range: 4.5V–5.5V operation Low active power (70 ns, LL version, Com’l and Ind’l) — 275 mW (max.) Low standby power (70 ns, LL version, Com’l and Ind’l) — 28 µW (max.) Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow SOIC, 28-lead TSOP-1, 28-lead reverse TSOP-1, and 600-mil 28-lead PDIP packages Functional Description[1] The CY62256 is a high-performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. Logic Block Diagram INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE A14 A13 A12 A11 A1 A0 ROW DECODER I/O0 I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5 512 x 512 Y ARRA COLUMN DECODER POWER DOWN I/O6 I/O7 Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05248 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised June 25, 2004 CY62256 Product Portfolio Power Dissipation VCC Range (V) Product CY62256 CY62256L CY62256LL CY62256LL CY62256LL Commercial Com’l / Ind’l Commercial Industrial Automotive Min. 4.5 Typ.[2] 5.0 Max. 5.5 Speed (ns) 70 55/70 70 55/70 55 Operating, ICC (mA) Typ.[2] 28 25 25 25 25 Max. 55 50 50 50 50 Standby, ISB2 (µA) Typ.[2] 1 2 0.1 0.1 0.1 Max. 5 50 5 10 15 Pin Configurations OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Narrow SOIC Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND DIP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 TSOP I Top View (not to scale) A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE 7 6 5 4 3 2 1 28 27 26 25 24 23 22 8 9 TSOP I Reverse Pinout Top View (not to scale) 10 11 12 13 14 15 16 17 18 19 20 21 A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0 Pin Definitions Pin Number 1-10, 21, 23-26 11-13, 15-19, 27 20 22 Type Input Input/Output Input/Control Input/Control Input/Control A0-A14. Address Inputs I/O0-I/O7. Data lines. Used as input or output lines depending on operation WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted CE. When LOW, selects the chip. When HIGH, deselects the chip OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins GND. Ground for the device Description 14 28 Ground Power Supply Vcc. Power supply for the device Notes: 2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. Document #: 38-05248 Rev. *C Page 2 of 12 CY62256 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied..............................................-55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[3] ....................................–0.5V to VCC + 0.5V DC Input Voltage .................................–0.5V to VCC + 0.5V [3] Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Commercial Industrial Automotive Ambient Temperature (TA)[4] 0°C to +70°C –40°C to +85°C –40°C to +125°C VCC 5V ± 10% 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range CY62256−55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current VCC Operating Supply Current GND < VI < VCC VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC L LL ISB1 Automatic CE Power-down Current— TTL Inputs Automatic CE Power-down Current— CMOS Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX L LL Output Leakage Current GND < VO < VCC, Output Disabled Test Conditions VCC = Min., IOH = −1.0 mA VCC = Min., IOL = 2.1 mA 2.2 –0.5 –0.5 –0.5 28 25 25 0.5 0.4 0.3 1 2 0.1 0.1 0.1 Min. Typ.[2] 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 55 50 50 2 0.6 0.5 5 50 5 10 15 2.2 –0.5 –0.5 –0.5 28 25 25 0.5 0.4 0.3 1 2 0.1 0.1 Max. 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 55 50 50 2 0.6 0.5 5 50 5 10 CY62256−70 Min. Typ.[2] Max. Unit V V V V µA µA mA mA mA mA mA mA mA µA µA µA µA ISB2 Max. VCC, CE > VCC − 0.3V VIN > VCC − 0.3V, or VIN < L 0.3V, f = 0 LL LL - Ind’l LL Auto Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 6 8 Unit pF pF Notes: 3. VIL (min.) = −2.0V for pulse durations of less than 20 ns. 4. TA is the “Instant-On” case temperature. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05248 Rev. *C Page 3 of 12 CY62256 Thermal Resistance Description Thermal Resistance (Junction to Ambient)[5] Thermal Resistance (Junction to Case)[5] Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Symbol ΘJA ΘJC DIP 75.61 43.12 SOIC 76.56 36.07 TSOP 93.89 24.64 RTSOP 93.89 24.64 Unit °C/W °C/W AC Test Loads and Waveforms 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE R2 990Ω R1 1800 Ω R1 1800 Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE Equivalent to: R2 990Ω 3.0V GND 10% ALL INPUT PULSES 90% 90% 10% < 5 ns < 5 ns (a) (b) THÉ VENIN EQUIVALENT 639Ω OUTPUT 1.77V Data Retention Characteristics Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current L LL LL - Ind’l LL - Auto tCDR[5] tR[5] Chip Deselect to Data Retention Time Operation Recovery Time 0 tRC VCC = 3.0V, CE > VCC − 0.3V, VIN > VCC − 0.3V, or VIN < 0.3V Conditions[6] Min. 2.0 2 0.1 0.1 0.1 50 5 10 10 Typ.[2] Max. Unit V µA µA µA µA ns ns Data Retention Waveform DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR Notes: 6. No input may exceed VCC + 0.5V. Document #: 38-05248 Rev. *C Page 4 of 12 CY62256 Switching Characteristics Over the Operating Range[7] CY62256−55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[10, 11] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[8, 9] WE HIGH to Low-Z[8] 5 55 45 45 0 0 40 25 0 20 5 70 60 60 0 0 50 30 0 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[8] OE HIGH to High-Z[8, 9] CE LOW to Low-Z[8] CE HIGH to High-Z[8, 9] 0 55 CE LOW to Power-up CE HIGH to Power-down 5 20 0 70 5 20 5 25 5 55 25 5 25 55 55 5 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. CY62256−70 Min. Max. Unit Switching Waveforms Read Cycle No. 1 [12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for Read cycle. Document #: 38-05248 Rev. *C Page 5 of 12 CY62256 Switching Waveforms (continued) Read Cycle No. 2 [13, 14] CE tACE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% DATA VALID tPD ICC 50% ISB tHZOE tHZCE tRC HIGH IMPEDANCE Write Cycle No. 1 (WE Controlled) ADDRESS [10, 15, 16] tWC CE tAW WE tSA tPWE tHA OE tSD DATA I/O NOTE 17 tHZOE [10, 15, 16] tHD DATAIN VALID Write Cycle No. 2 (CE Controlled) ADDRESS CE tWC tSCE tSA tAW tHA WE tSD DATA I/O DATA VALID IN tHD Notes: 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05248 Rev. *C Page 6 of 12 CY62256 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [11, 16] tWC ADDRESS CE tAW WE tSA tHA tSD DATA I/O NOTE 17 tHZWE DATA VALID IN tHD tLZWE Document #: 38-05248 Rev. *C Page 7 of 12 CY62256 Typical DC and AC Characteristics 1.4 SB NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 ICC 1.2 NORMALIZED I CC 1.0 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC 3.0 2.5 2.0 ISB2 µA 1.5 1.0 0.5 0.0 125 STANDBY CURRENT vs. AMBIENT TEMPERATURE 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN =5.0V TA =25°C NORMALIZED I, I CC ISB 0.8 0.6 0.4 0.2 0.0 −55 25 VCC =5.0V VIN =5.0V VCC =5.0V VIN =5.0V 25 105 AMBIENT TEMPERATURE (°C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE -0.5 −55 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA AA AMBIENT TEMPERATURE (°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 1.0 VCC =5.0V 0.8 0.6 −55 OUTPUT SINK CURRENT (mA) 140 120 100 80 60 40 20 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA =25°C NORMALIZED t VCC =5.0V TA =25°C 25 125 0 0.0 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT (mA) AMBIENT TEMPERATURE (°C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Document #: 38-05248 Rev. *C Page 8 of 12 CY62256 Typical DC and AC Characteristics (continued) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 DELTA tAA (ns) PO TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 NORMALIZED ICC 25.0 20.0 15.0 10.0 5.0 VCC =4.5V TA =25°C 1.25 NORMALIZED I CC vs.CYCLE TIME 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 NORMALIZED I 1.00 VCC =5.0V TA =25°C VIN =0.5V 0.75 0.0 0 200 400 600 800 1000 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Truth Table CE H L L L WE X H L H OE X L X H Inputs/Outputs High-Z Data Out Data In High-Z Read Write Output Disabled Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 55 Ordering Code CY62256LL−55SNI CY62256LL−55ZI CY62256LL−55SNE CY62256LL−55ZE CY62256LL−55ZRE 70 CY62256−70SNC CY62256L−70SNC CY62256LL−70SNC CY62256L–70SNI CY62256LL−70SNI CY62256LL−70ZC CY62256LL−70ZI CY62256−70PC CY62256L−70PC CY62256LL−70PC CY62256LL−70ZRI Z28 Z28 P15 P15 P15 ZR28 28-lead Reverse Thin Small Outline Package Industrial 28-lead (600-Mil) Molded DIP 28-lead Thin Small Outline Package Commercial Industrial Commercial Industrial Package Name SN28 Z28 SN28 Z28 ZR28 SN28 Package Type 28-lead (300-Mil Narrow Body) Narrow SOIC 28-lead Thin Small Outline Package 28-lead (300-Mil Narrow Body) Narrow SOIC 28-lead Thin Small Outline Package 28-lead Reverse Thin Small Outline Package 28-lead (300-Mil Narrow Body) Narrow SOIC Commercial Automotive Operating Range Industrial Document #: 38-05248 Rev. *C Page 9 of 12 CY62256 Package Diagrams 28-lead (600-mil) Molded DIP P15 51-85017-A 28-lead (300-mil) SNC (Narrow Body) SN28 51-85092-*B Document #: 38-05248 Rev. *C Page 10 of 12 CY62256 Package Diagrams (continued) 28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28 51-85071-*G 28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28 51-85074-*F All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05248 Rev. *C Page 11 of 12 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62256 Document Title: CY62256 256K (32K x 8) Static RAM Document Number: 38-05248 REV. ** *A *B *C ECN NO. 113454 115227 116506 238448 Issue Date 03/06/02 05/23/02 09/04/02 See ECN Orig. of Change MGN GBI GBI AJU Description of Change Change from Spec number: 38-00455 to 38-05248 Remove obsolete parts from ordering info, standardize format Changed SN Package Diagram Added footnote 1. Corrected package description in Ordering Information table Added Automotive product information Document #: 38-05248 Rev. *C Page 12 of 12