CY62256EV18LL-70SNXIT

CY62256EV18 MoBL® 256-Kbit (32 K × 8) Static RAM 256-Kbit (32 K × 8) Static RAM Features Functional Description ■ Very high speed: 70 ns The CY62256EV18 is a high performance CMOS static RAM module organized as 32 K words by 8-bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or a write operation is in progress (CE LOW and WE LOW). ■ Temperature ranges: ❐ Industrial: –40 °C to +85 °C ■ Wide voltage range: 1.65 V to 2.25 V ■ Pin compatible with CY62256N ■ Ultra low standby power ❐ Typical standby current: 1 µA ❐ Maximum standby current: 4 µA ■ Ultra low active power ❐ Typical active current: 1.3 mA at f = 1 MHz ■ Easy memory expansion with CE and OE features ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Offered in Pb-free 28-pin Narrow SOIC package To write to the device, take chip enable (CE) LOW and write enable (WE) LOW. Data on the eight I/O pins is then written into the location specified on the address pin (A0 through A14). To read from the device, take chip enable (CE LOW) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. For a complete list of related documentation, click here. Logic Block Diagram I/O0 INPUTBUFFER I/O1 32K x 8 ARRAY I/O2 SENSE AMPS ROW DECODER A10 A9 A8 A7 A6 A5 A4 A3 A2 I/O3 I/O4 I/O5 CE WE COLUMN DECODER I/O6 POWER DOWN I/O7 Cypress Semiconductor Corporation Document Number: 001-69650 Rev. *D • A12 A11 A1 A0 A13 A14 OE 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 21, 2015 CY62256EV18 MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 10 Document Number: 001-69650 Rev. *D Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC® Solutions ...................................................... 15 Cypress Developer Community ................................. 15 Technical Support ..................................................... 15 Page 2 of 15 CY62256EV18 MoBL® Pin Configuration Figure 1. 28-pin Narrow SOIC pinout Product Portfolio Power Dissipation Product Range Speed (ns) VCC Range (V) Operating ICC (mA) f = 1 MHz CY62256EV18LL Industrial Min Typ [1] Max 1.65 1.8 2.25 70 f = fmax Standby ISB2 (µA) Typ [1] Max Typ [1] Max Typ [1] Max 1.3 2.0 11 16 1 4 Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document Number: 001-69650 Rev. *D Page 3 of 15 CY62256EV18 MoBL® DC input voltage [2, 3] ...................................–0.2 V to 2.45 V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Supply voltage to ground potential .......................................................–0.2 V to 2.45 V DC voltage applied to outputs in high Z State [2, 3] ......................................–0.2 V to 2.45 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (MIL-STD-883, method 3015) ................................ > 2001 V Latch-up current .................................................... > 200 mA Operating Range Device Range Ambient Temperature VCC[4] CY62256EV18LL Industrial –40 °C to +85 °C 1.65 V to 2.25 V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions IOH = –0.1 mA 70 ns Unit Min Typ [5] Max 1.4 – – V VOH Output HIGH voltage VOL Output LOW voltage IOL = 0.1 mA – – 0.2 V VIH Input HIGH voltage VCC = 1.65 V to 2.25 V 1.4 – VCC + 0.2 V V VIL Input LOW voltage VCC = 1.65 V to 2.25 V –0.2 – 0.4 V IIX Input leakage current GND < VI < VCC –1 – +1 µA IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 µA ICC VCC operating supply current f = fmax = 1/tRC – 11 16 mA – 1.3 2.0 mA f = 1 MHz VCC = 2.25 V IOUT = 0 mA CMOS levels ISB1 Automatic CE power-down current — CMOS inputs CE > VCC0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V f = fmax (address and data only), f = 0 (OE and WE), VCC = 2.25 V – 1 4 µA ISB2 [6] Automatic CE power-down current — CMOS inputs CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 2.25 V – 1 4 µA Notes 2. VIL(min) = –2.0 V for pulse durations less than 20 ns. 3. VIH(max) = VCC + 0.5 V for pulse durations less than 20 ns. 4. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 6. Chip enables (CE) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 001-69650 Rev. *D Page 4 of 15 CY62256EV18 MoBL® Capacitance Parameter [7] Description CIN Input capacitance COUT Output capacitance Test Conditions Max Unit 10 pF 10 pF Test Conditions 28-pin SOIC Unit Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 76.56 °C/W 36.07 °C/W TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance Parameter [7] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES VCC 10% R2 30 pF INCLUDING JIG AND SCOPE 90% 10% 90% GND Rise Time = 1 V/ns Equivalent to: Fall Time = 1 V/ns THEVENIN EQUIVALENT OUTPUT RTH VTH Parameters 1.8 V Unit R1 13500  R2 10800  RTH 6000  VTH 0.8 V Note 7. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-69650 Rev. *D Page 5 of 15 CY62256EV18 MoBL® Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR Description Conditions VCC for data retention [9] VCC = 1.0 V, CE > VCC 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Data retention current Min Typ [8] Max Unit 1.0 – – V – – 3 µA tCDR [10] Chip deselect to data retention time 0 – – ns tR [11] Operation recovery time 70 – – ns Data Retention Waveform Figure 3. Data Retention Waveform [12] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.0 V VCC(min) tR CE Notes 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 9. Chip enables (CE) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 10. Tested initially and after any design or process changes that may affect these parameters. 11. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min)  100 µs. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. Document Number: 001-69650 Rev. *D Page 6 of 15 CY62256EV18 MoBL® Switching Characteristics Over the Operating Range Parameter [13] Description 70 ns Min Max Unit Read Cycle tRC Read cycle time 70 – ns tAA Address to data valid – 70 ns tOHA Data hold from address change 5 – ns tACE CE LOW to data valid – 70 ns tDOE OE LOW to data valid – 35 ns 5 – ns – 25 ns tLZOE tHZOE OE LOW to low Z [14] OE HIGH to high Z [14, 15] [14] tLZCE CE LOW to low Z 5 – ns tHZCE CE HIGH to high Z [14, 15] – 25 ns tPU CE LOW to power-up 0 – ns CE HIGH to power-down – 70 ns tPD Write Cycle [16, 17] tWC Write cycle time 70 – ns tSCE CE LOW to write end 60 – ns tAW Address setup to write end 60 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 50 – ns tSD Data setup to write end 30 – ns tHD Data hold from write end 0 – ns tHZWE WE LOW to high Z [14, 15] – 25 ns 5 – ns tLZWE WE HIGH to low Z [14] Notes 13. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5. 14. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 15. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 16. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 17. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE low) should be equal to the sum of tSD and tHZWE. Document Number: 001-69650 Rev. *D Page 7 of 15 CY62256EV18 MoBL® Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [18, 19] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [19, 20] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA OUT DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% ICC ISB Figure 6. Write Cycle No. 1 (WE Controlled) [21, 22, 23] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O NOTE 24 tHD DATA VALID tHZOE Notes 18. The device is continuously selected. OE, CE = VIL. 19. WE is HIGH for read cycle. 20. Address valid before or similar to CE transition LOW. 21. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 22. Data I/O is high impedance if OE = VIH. 23. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 24. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-69650 Rev. *D Page 8 of 15 CY62256EV18 MoBL® Switching Waveforms (continued) Figure 7. Write Cycle No. 2 (CE Controlled) [25, 26, 27] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [27] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 28 tHD DATA VALID tHZWE tLZWE Notes 25. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 26. Data I/O is high impedance if OE = VIH. 27. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 28. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-69650 Rev. *D Page 9 of 15 CY62256EV18 MoBL® Truth Table CE H L WE X [29] OE X [29] Inputs/Outputs Mode Power High Z Deselect/power-down Standby (ISB) H L Data out Read Active (ICC) L L [29] Data in Write Active (ICC) L H H High Z Selected, outputs disabled Active (ICC) X Note 29. The ‘X’ (Don’t care) state for the CE / OE / WE in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document Number: 001-69650 Rev. *D Page 10 of 15 CY62256EV18 MoBL® Ordering Information Speed (ns) 70 Package Diagram Ordering Code CY62256EV18LL-70SNXI Package Type 51-85092 28-pin (300-Mil) Narrow SOIC (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 62 256 E V18 LL - 70 SN X I Temperature Grade: I = Industrial = –40 °C to +85 °C Pb-free Package Type: SN = 28-pin Narrow SOIC Speed Grade: 70 ns Low Power V18 = 1.8 V Process Technology: E = 90 nm Density: 256 Kbit MoBL SRAM family Company ID: CY = Cypress Document Number: 001-69650 Rev. *D Page 11 of 15 CY62256EV18 MoBL® Package Diagrams Figure 9. 28-pin SNC (300 Mils) SN28.3 (Narrow Body) Package Outline, 51-85092 51-85092 *E Document Number: 001-69650 Rev. *D Page 12 of 15 CY62256EV18 MoBL® Acronyms Acronym Document Conventions Description Units of Measure CMOS Complementary Metal Oxide Semiconductor CE Chip Enable °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static Random Access Memory µs microsecond SOIC Small Outline Integrated Circuit mA milliampere WE Write Enable ns nanosecond  ohm pF picofarad V volt W watt Document Number: 001-69650 Rev. *D Symbol Unit of Measure Page 13 of 15 CY62256EV18 MoBL® Document History Page Document Title: CY62256EV18 MoBL®, 256-Kbit (32 K × 8) Static RAM Document Number: 001-69650 Revision ECN Submission Date Orig. of Change Description of Change ** 3334904 09/07/2011 RAME New data sheet. *A 3413173 10/18/2011 RAME Changed status from Preliminary to Final. *B 3733339 09/04/2012 JISH Fixed typo errors. Completing Sunset Review. *C 4573121 11/18/2014 JISH Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *D 4928585 09/21/2015 VINI Updated Switching Characteristics: Added Note 17 and referred the same note in “Write Cycle”. Updated to new template. Completing Sunset Review. Document Number: 001-69650 Rev. *D Page 14 of 15 CY62256EV18 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2011-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-69650 Rev. *D Revised September 21, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 15 of 15