CY62256NL-70SNI

CY62256N 256K (32K x 8) Static RAM Features ■ Functional Description The CY62256N[1] is a high performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tristate drivers. This device has an automatic power down feature, reducing the power consumption by 99.9 percent when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. Temperature Ranges ❐ Commercial: 0°C to 70°C ❐ Industrial: –40°C to 85°C ❐ Automotive-A: –40°C to 85°C ❐ Automotive-E: –40°C to 125°C High Speed: 55 ns Voltage Range: 4.5V to 5.5V Operation Low Active Power ❐ 275 mW (max) Low Standby Power (LL version) ❐ 82.5 μW (max) Easy Memory Expansion with CE and OE Features TTL-Compatible Inputs and Outputs Automatic Power Down when Deselected CMOS for Optimum Speed and Power Available in Pb-free and Non Pb-free 28-Pin (600-mil) PDIP, 28-Pin (300-mil) Narrow SOIC, 28-Pin TSOP-I, and 28-Pin Reverse TSOP-I Packages ■ ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE A14 A13 A12 A11 A1 A0 ROW DECODER I/O0 I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5 32K x 8 Y ARRA COLUMN DECODER POWER DOWN I/O6 I/O7 Note 1. For best practice recommendations, do refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com Cypress Semiconductor Corporation Document #: 001-06511 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 03, 2009 [+] Feedback CY62256N Product Portfolio Product CY62256NL CY62256NLL CY62256NLL CY62256NLL CY62256NLL Commercial / Industrial Commercial Industrial Automotive-A Automotive-E Min 4.5 VCC Range (V) Typ[2] 5.0 Max 5.5 Speed (ns) 70 70 55/70 55/70 55 Power Dissipation Operating, ICC Standby, ISB2 (μA) (mA) [2] Typ Max Typ[2] Max 25 50 2 50 25 25 25 25 50 50 50 50 0.1 0.1 0.1 0.1 5 10 10 15 Pin Configurations Figure 1. 28-Pin DIP and Narrow SOIC Figure 2. 28-Pin TSOP I and Reverse TSOP I Table 1. Pin Definitions Pin Number 1–10, 21, 23–26 11–13, 15–19, 27 20 22 14 28 Type Input Input/Output Input/Control Input/Control Input/Control Ground Power Supply Description A0–A14. Address Inputs I/O0–I/O7. Data lines. Used as input or output lines depending on operation WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted CE. When LOW, selects the chip. When HIGH, deselects the chip OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins GND. Ground for the device VCC. Power supply for the device Note 2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. Document #: 001-06511 Rev. *B Page 2 of 14 [+] Feedback CY62256N Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................. -55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14)............................................–0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[3] .................................... –0.5V to VCC + 0.5V DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V Output Current into Outputs (LOW) ............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch up Current.................................................... > 200 mA Operating Range Range Commercial Industrial Automotive-A Automotive-E Ambient Temperature (TA)[4] 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +125°C VCC 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current VCC Operating Supply Current GND < VI < VCC VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC L-Commercial/ Industrial LL-Commercial LL - Industrial LL - Auto-A LL - Auto-E ISB1 Automatic CE Power down Current— TTL Inputs Max. VCC, CE > VIH, L VIN > VIH or VIN < VIL, LL-Commercial f = fMAX LL - Industrial LL - Auto-A LL - Auto-E ISB2 Automatic CE Power down Current— CMOS Inputs Max. VCC, L CE > VCC − 0.3V LL-Commercial VIN > VCC − 0.3V, or LL - Industrial VIN < 0.3V, f = 0 LL - Auto-A LL - Auto-E 25 25 25 50 50 50 0.4 0.3 0.3 0.3 0.3 0.5 0.5 0.5 2 0.1 0.1 0.1 0.1 10 10 15 0.1 0.1 50 5 10 10 0.3 0.3 0.6 0.5 0.5 0.5 Output Leakage Current GND < VO < VCC, Output Disabled Test Conditions VCC = Min., IOH = −1.0 mA VCC = Min., IOL = 2.1 mA 2.2 –0.5 –0.5 –0.5 -55 Min 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 2.2 –0.5 –0.5 –0.5 25 25 25 25 Typ[2] Max Min 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 50 50 50 50 -70 Typ[2] Max Unit V V V V μA μA mA mA mA mA mA mA mA mA mA mA μA μA μA μA μA Capacitance Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions[5] TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 6 8 Unit pF pF Notes 3. VIL (min.) = −2.0V for pulse durations of less than 20 ns. 4. TA is the “Instant-On” case temperature. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06511 Rev. *B Page 3 of 14 [+] Feedback CY62256N Thermal Resistance Parameter ΘJA ΘJC Description[5] Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board DIP 75.61 43.12 SOIC 76.56 36.07 TSOP 93.89 24.64 RTSOP 93.89 24.64 Unit °C/W °C/W Figure 3. AC Test Loads and Waveforms 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE R2 990Ω R1 1800Ω R1 1800Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 990Ω 3.0V GND 10% ALL INPUT PULSES 90% 90% 10% < 5 ns < 5 ns (a) (b) Equivalent to: THÉ VENIN EQUIVALENT 639Ω OUTPUT 1.77V Data Retention Characteristics Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current L LL-Commercial LL - Industrial/Auto-A LL - Auto-E tCDR[8] tR [8] Conditions[6] VCC = 2.0V, CE > VCC − 0.3V, VIN > VCC − 0.3V, or VIN < 0.3V Min 2.0 Typ[2] 2 0.1 0.1 0.1 Max 50 5 10 10 Unit V μA μA μA μA ns ns Chip Deselect to Data Retention Time Operation Recovery Time 0 tRC Figure 4. Data Retention Waveform DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR Note 6. No input may exceed VCC + 0.5V. Document #: 001-06511 Rev. *B Page 4 of 14 [+] Feedback CY62256N Switching Characteristics Over the Operating Range[7] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z [8] [8, 9] Description CY62256N-55 Min 55 55 5 55 25 5 20 5 20 0 55 55 45 45 0 0 40 25 0 20 5 5 0 5 5 5 Max CY62256N-70 Min 70 70 70 35 25 25 70 70 60 60 0 0 50 30 0 25 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns OE HIGH to High-Z CE HIGH to CE LOW to Low-Z[8] High-Z[8, 9] CE LOW to Power up CE HIGH to Power down Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to WE HIGH to High-Z[8, 9] Low-Z[8] Write Cycle[10, 11] Switching Waveforms Figure 5. Read Cycle No. 1[12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 8. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for Read cycle. Document #: 001-06511 Rev. *B Page 5 of 14 [+] Feedback CY62256N Switching Waveforms (continued) Figure 6. Read Cycle No. 2[13, 14] CE tACE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tRC tHZOE tHZCE DATA VALID tPD HIGH IMPEDANCE ICC 50% ISB Figure 7. Write Cycle No. 1 (WE Controlled)[10, 15, 16] tWC ADDRESS CE tAW WE tSA tPWE tHA OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD Figure 8. Write Cycle No. 2 (CE Controlled)[10, 15, 16] tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATA VALID IN tHD tHA tSCE Notes 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. Document #: 001-06511 Rev. *B Page 6 of 14 [+] Feedback CY62256N Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16] tWC ADDRESS CE tAW WE tSA tHA tSD DATA I/O NOTE 17 tHZWE DATA VALID IN tHD tLZWE Document #: 001-06511 Rev. *B Page 7 of 14 [+] Feedback CY62256N Typical DC and AC Characteristics 1.4 NORMALIZED ICC, ISB 1.2 NORMALIZED ICC 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN = 5.0V TA = 25°C ICC NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 1.0 ISB2 μA 0.8 0.6 0.4 0.2 0.0 −55 25 125 VCC = 5.0V VIN = 5.0V NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC 3.0 2.5 2.0 1.5 1.0 0.5 0.0 –0.5 −55 25 VCC = 5.0V VIN = 5.0V 105 AMBIENT TEMPERATURE (°C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE ISB STANDBY CURRENT vs. AMBIENT TEMPERATURE SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 T A = 2 5° C AMBIENT TEMPERATURE (°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE OUTPUT SINK CURRENT (mA) 1.6 1.4 1.2 1.0 0.8 140 120 100 80 60 40 20 VCC = 5.0V VCC = 5.0V T A = 2 5° C 0.6 −55 25 125 0 0.0 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE OUTPUT VOLTAGE (V) OUTPUT SOURCE CURRENT (mA) 120 100 80 60 40 20 VCC = 5.0V TA = 25°C 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) Document #: 001-06511 Rev. *B Page 8 of 14 [+] Feedback CY62256N Typical DC and AC Characteristics TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED IPO DELTA tAA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 (continued) NORMALIZED ICC vs. CYCLE TIME TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED ICC 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC = 4.5V TA = 25°C 1.00 VCC = 5.0V TA = 25°C VIN = 5.0V 0.75 600 800 1000 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Truth Table CE H L L L WE X H L H OE X L X H Inputs/Outputs High-Z Data Out Data In High-Z Read Write Output Disabled Mode Deselect/Power down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Document #: 001-06511 Rev. *B Page 9 of 14 [+] Feedback CY62256N Ordering Information Speed (ns) 55 Ordering Code CY62256NLL−55SNI CY62256NLL−55SNXI CY62256NLL−55ZI CY62256NLL−55ZXI CY62256NLL−55ZXA CY62256NLL−55SNXE CY62256NLL−55ZXE CY62256NLL−55ZRXE 70 CY62256NL−70PC CY62256NL−70PXC CY62256NLL−70PC CY62256NLL−70PXC CY62256NL−70SNC CY62256NL−70SNXC CY62256NLL−70SNC CY62256NLL−70SNXC CY62256NLL−70ZC CY62256NLL−70ZXC CY62256NL–70SNI CY62256NL–70SNXI CY62256NLL−70SNI CY62256NLL−70SNXI CY62256NLL−70ZI CY62256NLL−70ZXI CY62256NLL−70ZRI CY62256NLL−70ZRXI CY62256NLL−70SNXA Package Diagram Package Type 28-Pin (300-Mil) Narrow SOIC (Pb-Free) 51-85071 28-Pin TSOP I 28-Pin TSOP I (Pb-Free) 51-85071 28-Pin TSOP I (Pb-Free) 51-85092 28-Pin (300-Mil) Narrow SOIC (Pb-Free) 51-85071 28-Pin TSOP I (Pb-Free) 51-85074 28-Pin Reverse TSOP I (Pb-Free) 51-85017 28-Pin (600-Mil) Molded DIP 28-Pin (600-Mil) Molded DIP (Pb-Free) 28-Pin (600-Mil) Molded DIP 28-Pin (600-Mil) Molded DIP (Pb-Free) 51-85092 28-Pin (300-Mil) Narrow SOIC 28-Pin (300-Mil) Narrow SOIC (Pb-Free) 28-Pin (300-Mil) Narrow SOIC 28-Pin (300-Mil) Narrow SOIC (Pb-Free) 51-85071 28-Pin TSOP I 28-Pin TSOP I (Pb-Free) 51-85092 28-Pin (300-Mil) Narrow SOIC 28-Pin (300-Mil) Narrow SOIC (Pb-Free) 28-Pin (300-Mil) Narrow SOIC 28-Pin (300-Mil) Narrow SOIC (Pb-Free) 51-85071 28-Pin TSOP I 28-Pin TSOP I (Pb-Free) 51-85074 28-Pin Reverse TSOP I 28-Pin Reverse TSOP I (Pb-Free) 51-85092 28-Pin (300-Mil) Narrow SOIC (Pb-Free) Automotive-A Industrial Commercial Automotive-A Automotive-E Operating Range Industrial 51-85092 28-Pin (300-Mil) Narrow SOIC Do contact your local Cypress sales representative for availability of these parts Document #: 001-06511 Rev. *B Page 10 of 14 [+] Feedback CY62256N Package Diagrams Figure 10. 28-Pin (600-Mil) Molded DIP (51-85017) 51-85017-*C Figure 11. 28-Pin (300-mil) SNC (Narrow Body) (51-85092) 51-85092-*B Document #: 001-06511 Rev. *B Page 11 of 14 [+] Feedback CY62256N Figure 12. 28-Pin TSOP I (8 x 13.4 mm) (51-85071) 51-85071-*G Document #: 001-06511 Rev. *B Page 12 of 14 [+] Feedback CY62256N Figure 13. 28-Pin TSOP I (8 x 13.4 mm) (51-85074) 51-85074-*F Document #: 001-06511 Rev. *B Page 13 of 14 [+] Feedback CY62256N Document History Page Document Title: CY62256N 256K (32K x 8) Static RAM Document Number: 001- 06511 REV. ** *A *B ECN NO. Submission Date 426504 488954 2715270 See ECN See ECN 06/05/2009 Orig. of Change NXR NXR New Data Sheet Added Automotive product Updated ordering Information table Description of Change VKN/AESA Updated POD of 28-Pin (600-Mil) Molded DIP package (Spec# 51-85017) Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com © Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06511 Rev. *B All products and company names mentioned in this document may be the trademarks of their respective holders. Revised June 03, 2009 Page 14 of 14 [+] Feedback