CY62256N
256K (32K x 8) Static RAM
Features
Functional Description
The CY62256N[1] is a high performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and tristate drivers. This device has an
automatic power down feature, reducing the power consumption
by 99.9 percent when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location addressed
by the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
■
Temperature Ranges
❐ Commercial: 0°C to 70°C
❐ Industrial: –40°C to 85°C
❐ Automotive-A: –40°C to 85°C
❐ Automotive-E: –40°C to 125°C
■
High Speed: 55 ns
■
Voltage Range: 4.5V to 5.5V Operation
■
Low Active Power
❐ 275 mW (max)
■
Low Standby Power (LL version)
❐ 82.5 μW (max)
■
Easy Memory Expansion with CE and OE Features
■
TTL-Compatible Inputs and Outputs
■
Automatic Power Down when Deselected
■
CMOS for Optimum Speed and Power
■
Available in Pb-free and Non Pb-free 28-Pin (600-mil) PDIP,
28-Pin (300-mil) Narrow SOIC, 28-Pin TSOP-I, and 28-Pin
Reverse TSOP-I Packages
Logic Block Diagram
I/O0
INPUTBUFFER
I/O1
32K x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
I/O3
I/O4
I/O5
CE
WE
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
A12
A11
A1
A0
A13
A14
OE
Note
1. For best practice recommendations, do refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com
Cypress Semiconductor Corporation
Document #: 001-06511 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 03, 2009
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CY62256N
Product Portfolio
VCC Range (V)
Product
CY62256NL
CY62256NLL
CY62256NLL
CY62256NLL
CY62256NLL
Commercial /
Industrial
Commercial
Industrial
Automotive-A
Automotive-E
Min
4.5
Typ[2]
5.0
Speed
(ns)
Max
5.5
70
70
55/70
55/70
55
Power Dissipation
Operating, ICC
Standby, ISB2 (μA)
(mA)
[2]
Typ
Max
Typ[2]
Max
25
50
2
50
25
25
25
25
50
50
50
50
0.1
0.1
0.1
0.1
5
10
10
15
Pin Configurations
Figure 1. 28-Pin DIP and Narrow SOIC
Figure 2. 28-Pin TSOP I and Reverse TSOP I
Table 1. Pin Definitions
Pin Number
1–10, 21, 23–26
11–13, 15–19,
27
Type
Input
Input/Output
Input/Control
20
22
Input/Control
Input/Control
14
28
Ground
Power Supply
Description
A0–A14. Address Inputs
I/O0–I/O7. Data lines. Used as input or output lines depending on operation
WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
CE. When LOW, selects the chip. When HIGH, deselects the chip
OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input
data pins
GND. Ground for the device
VCC. Power supply for the device
Note
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA
= 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
Document #: 001-06511 Rev. *B
Page 2 of 14
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CY62256N
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied ............................................. -55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)............................................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[3] .................................... –0.5V to VCC + 0.5V
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Output Current into Outputs (LOW) ............................. 20 mA
Ambient Temperature (TA)[4]
Range
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
Automotive-A
–40°C to +85°C
5V ± 10%
Automotive-E
–40°C to +125°C
5V ± 10%
Commercial
Industrial
Electrical Characteristics Over the Operating Range
Parameter
Description
-55
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = −1.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
VIH
Input HIGH Voltage
Min
VIL
Input LOW Voltage
Input Leakage Current
IOZ
Output Leakage Current GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
Current
ISB2
Automatic CE
Power down Current—
TTL Inputs
Automatic CE
Power down Current—
CMOS Inputs
Typ[2]
Min
GND < VI < VCC
Max
Unit
2.4
V
0.4
0.4
V
VCC
+0.5V
V
VCC
+0.5V
2.2
–0.5
0.8
–0.5
0.8
V
–0.5
+0.5
–0.5
+0.5
μA
–0.5
+0.5
–0.5
2.2
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
-70
Max
2.4
IIX
ISB1
Typ[2]
+0.5
μA
L-Commercial/
Industrial
25
50
mA
LL-Commercial
25
50
mA
LL - Industrial
25
50
25
50
mA
LL - Auto-A
25
50
25
50
mA
LL - Auto-E
25
50
0.4
0.6
mA
Max. VCC, CE > VIH, L
VIN > VIH or VIN < VIL, LL-Commercial
f = fMAX
LL - Industrial
0.3
0.3
0.5
mA
0.5
0.3
0.5
mA
0.3
0.5
LL - Auto-A
0.3
0.5
LL - Auto-E
0.3
0.5
Max. VCC,
L
CE > VCC − 0.3V
LL-Commercial
VIN > VCC − 0.3V, or
LL - Industrial
VIN < 0.3V, f = 0
LL - Auto-A
LL - Auto-E
mA
mA
mA
2
50
μA
0.1
5
μA
0.1
10
0.1
10
μA
0.1
10
0.1
10
μA
0.1
15
μA
Capacitance
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions[5]
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
6
pF
8
pF
Notes
3. VIL (min.) = −2.0V for pulse durations of less than 20 ns.
4. TA is the “Instant-On” case temperature.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06511 Rev. *B
Page 3 of 14
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CY62256N
Thermal Resistance
Description[5]
Parameter
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
DIP
SOIC
TSOP
RTSOP
Unit
Still Air, soldered on a 4.25 x 1.125
inch, 4-layer printed circuit board
75.61
76.56
93.89
93.89
°C/W
43.12
36.07
24.64
24.64
°C/W
Figure 3. AC Test Loads and Waveforms
R1 1800Ω
R1 1800Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
990Ω
100 pF
INCLUDING
JIG AND
SCOPE
3.0V
INCLUDING
JIG AND
SCOPE
(a)
R2
990Ω
5 pF
GND
90%
10%
90%
10%
< 5 ns
< 5 ns
(b)
Equivalent to:
THÉVENIN EQUIVALENT
639Ω
OUTPUT
1.77V
Data Retention Characteristics
Parameter
Conditions[6]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Min
LL-Commercial
LL - Auto-E
tR
Chip Deselect to Data Retention Time
[8]
Max
Unit
2
50
μA
2.0
VCC = 2.0V, CE > VCC − 0.3V,
VIN > VCC − 0.3V, or VIN < 0.3V
L
LL - Industrial/Auto-A
tCDR[8]
Typ[2]
Operation Recovery Time
V
0.1
5
μA
0.1
10
μA
0.1
10
μA
0
ns
tRC
ns
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
tCDR
VDR > 2V
3.0V
tR
CE
Note
6. No input may exceed VCC + 0.5V.
Document #: 001-06511 Rev. *B
Page 4 of 14
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CY62256N
Switching Characteristics Over the Operating Range[7]
Parameter
CY62256N-55
Description
Min
Max
CY62256N-70
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to Low-Z
55
70
55
5
[8]
tHZOE
OE HIGH to High-Z
CE LOW to Low-Z[8]
70
5
5
20
5
tHZCE
CE HIGH to
tPU
CE LOW to Power up
tPD
CE HIGH to Power down
ns
25
5
High-Z[8, 9]
20
0
ns
ns
25
0
55
ns
ns
5
[8, 9]
tLZCE
ns
ns
ns
70
ns
Write Cycle[10, 11]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Setup to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Setup to Write Start
0
0
ns
tPWE
WE Pulse Width
40
50
ns
tSD
Data Setup to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
tLZWE
WE LOW to
High-Z[8, 9]
WE HIGH to
Low-Z[8]
20
5
25
5
ns
ns
Switching Waveforms
Figure 5. Read Cycle No. 1[12, 13]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
Notes
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for Read cycle.
Document #: 001-06511 Rev. *B
Page 5 of 14
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CY62256N
Switching Waveforms
(continued)
Figure 6. Read Cycle No. 2[13, 14]
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
Figure 7. Write Cycle No. 1 (WE Controlled)[10, 15, 16]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
OE
tSD
DATA I/O
NOTE 17
tHD
DATAIN VALID
tHZOE
Figure 8. Write Cycle No. 2 (CE Controlled)[10, 15, 16]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
tHD
DATAIN VALID
Notes
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 001-06511 Rev. *B
Page 6 of 14
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CY62256N
Switching Waveforms
(continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
tWC
ADDRESS
CE
tAW
WE
tHA
tSA
tSD
DATA I/O
NOTE 17
tHZWE
Document #: 001-06511 Rev. *B
tHD
DATAIN VALID
tLZWE
Page 7 of 14
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CY62256N
Typical DC and AC Characteristics
1.4
1.2
0.8
0.6
VIN = 5.0V
TA = 25°C
0.4
0.0
4.0
2.0
1.0
0.8
0.6
VCC = 5.0V
VIN = 5.0V
0.4
4.5
5.0
5.5
0.0
−55
6.0
25
SUPPLY VOLTAGE (V)
1.6
1.3
1.4
NORMALIZED tAA
NORMALIZED tAA
1.4
1.2
TA = 25°C
1.0
0.8
4.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.2
1.0
4.5
5.0
5.5
6.0
VCC = 5.0V
0.6
−55
25
125
OUTPUT SOURCE CURRENT (mA)
120
105
140
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
120
100
80
60
VCC = 5.0V
TA = 25°C
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
25
AMBIENT TEMPERATURE (°C)
0.8
0.9
VCC = 5.0V
VIN = 5.0V
–0.5
−55
125
AMBIENT TEMPERATURE (°C)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.1
1.0
0.0
0.2
ISB
ISB
1.5
0.5
OUTPUT SINK CURRENT (mA)
0.2
2.5
ISB2 μA
1.0
3.0
ICC
1.2
ICC
NORMALIZED ICC
NORMALIZED ICC, ISB
1.4
STANDBY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
100
80
VCC = 5.0V
TA = 25°C
60
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Document #: 001-06511 Rev. *B
Page 8 of 14
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CY62256N
Typical DC and AC Characteristics
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
2.5
25.0
2.0
1.5
1.0
0.5
0.0
0.0
1.25
20.0
15.0
VCC = 4.5V
TA = 25°C
10.0
5.0
1.0
2.0
3.0
4.0
5.0
0.0
0
SUPPLY VOLTAGE (V)
200
400
600
800 1000
CAPACITANCE (pF)
NORMALIZED ICC
3.0
DELTA tAA (ns)
NORMALIZED IPO
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
(continued)
NORMALIZED ICC vs. CYCLE TIME
1.00
VCC = 5.0V
TA = 25°C
VIN = 5.0V
0.75
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Truth Table
CE
WE
OE
H
X
X
High-Z
Inputs/Outputs
Deselect/Power down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High-Z
Output Disabled
Active (ICC)
Document #: 001-06511 Rev. *B
Mode
Power
Page 9 of 14
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CY62256N
Ordering Information
Speed
(ns)
55
Ordering Code
CY62256NLL−55SNI
CY62256NLL−55SNXI
CY62256NLL−55ZI
CY62256NLL−55ZXI
70
Package
Diagram
Package Type
51-85092 28-Pin (300-Mil) Narrow SOIC
Operating
Range
Industrial
28-Pin (300-Mil) Narrow SOIC (Pb-Free)
51-85071 28-Pin TSOP I
28-Pin TSOP I (Pb-Free)
CY62256NLL−55ZXA
51-85071 28-Pin TSOP I (Pb-Free)
Automotive-A
CY62256NLL−55SNXE
51-85092 28-Pin (300-Mil) Narrow SOIC (Pb-Free)
Automotive-E
CY62256NLL−55ZXE
51-85071 28-Pin TSOP I (Pb-Free)
CY62256NLL−55ZRXE
51-85074 28-Pin Reverse TSOP I (Pb-Free)
CY62256NL−70PC
51-85017 28-Pin (600-Mil) Molded DIP
CY62256NL−70PXC
28-Pin (600-Mil) Molded DIP (Pb-Free)
CY62256NLL−70PC
28-Pin (600-Mil) Molded DIP
CY62256NLL−70PXC
28-Pin (600-Mil) Molded DIP (Pb-Free)
CY62256NL−70SNC
CY62256NL−70SNXC
51-85092 28-Pin (300-Mil) Narrow SOIC
28-Pin (300-Mil) Narrow SOIC (Pb-Free)
CY62256NLL−70SNC
28-Pin (300-Mil) Narrow SOIC
CY62256NLL−70SNXC
28-Pin (300-Mil) Narrow SOIC (Pb-Free)
CY62256NLL−70ZC
CY62256NLL−70ZXC
CY62256NL–70SNI
CY62256NL–70SNXI
51-85071 28-Pin TSOP I
28-Pin TSOP I (Pb-Free)
51-85092 28-Pin (300-Mil) Narrow SOIC
CY62256NLL−70SNI
28-Pin (300-Mil) Narrow SOIC
28-Pin (300-Mil) Narrow SOIC (Pb-Free)
CY62256NLL−70ZI
CY62256NLL−70ZRI
CY62256NLL−70ZRXI
CY62256NLL−70SNXA
Industrial
28-Pin (300-Mil) Narrow SOIC (Pb-Free)
CY62256NLL−70SNXI
CY62256NLL−70ZXI
Commercial
51-85071 28-Pin TSOP I
28-Pin TSOP I (Pb-Free)
51-85074 28-Pin Reverse TSOP I
28-Pin Reverse TSOP I (Pb-Free)
51-85092 28-Pin (300-Mil) Narrow SOIC (Pb-Free)
Automotive-A
Do contact your local Cypress sales representative for availability of these parts
Document #: 001-06511 Rev. *B
Page 10 of 14
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CY62256N
Package Diagrams
Figure 10. 28-Pin (600-Mil) Molded DIP (51-85017)
51-85017-*C
Figure 11. 28-Pin (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
Document #: 001-06511 Rev. *B
Page 11 of 14
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CY62256N
Figure 12. 28-Pin TSOP I (8 x 13.4 mm) (51-85071)
51-85071-*G
Document #: 001-06511 Rev. *B
Page 12 of 14
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CY62256N
Figure 13. 28-Pin TSOP I (8 x 13.4 mm) (51-85074)
51-85074-*F
Document #: 001-06511 Rev. *B
Page 13 of 14
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CY62256N
Document History Page
Document Title: CY62256N 256K (32K x 8) Static RAM
Document Number: 001- 06511
REV.
ECN NO. Submission
Date
Orig. of
Change
Description of Change
**
426504
See ECN
NXR
New Data Sheet
*A
488954
See ECN
NXR
Added Automotive product
Updated ordering Information table
*B
2715270
06/05/2009
VKN/AESA Updated POD of 28-Pin (600-Mil) Molded DIP package (Spec# 51-85017)
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-06511 Rev. *B
Revised June 03, 2009
All products and company names mentioned in this document may be the trademarks of their respective holders.
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