CY7C1018CV33-15VXC

THIS SPEC IS OBSOLETE Spec No: 38-05131 Spec Title: CY7C1018CV33 128K X 8 STATIC RAM Sunset Owner: Prashanth Jnanendra (pras) Replaced by: NONE CY7C1018CV33 128K x 8 Static RAM Features • Pin- and function-compatible with CY7C1018BV33 • High speed — tAA = 10 ns • CMOS for optimum speed/power • Center power/ground pinout • Data retention at 2.0V • Automatic power-down when deselected • Easy memory expansion with CE and OE options • Available in Pb-free and non Pb-free 300-mil-wide 32-pin SOJ Functional Description[1] The CY7C1018CV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1018CV33 is available in a standard 300-mil-wide SOJ. Logic Block Diagram Pin Configurations SOJ Top View I/O0 INPUT BUFFER CE I/O2 128K x 8 ARRAY SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1 I/O3 I/O4 I/O5 COLUMN DECODER I/O6 POWER DOWN CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 I/O7 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 WE OE A0 A1 A2 A3 Note: 1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05131 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 13, 2010 [+] Feedback CY7C1018CV33 Selection Guide Maximum Access Time Maximum Operating Current Comm’l -10 -12 -15 10 12 15 ns 90 85 80 mA Ind’l Unit 85 Maximum Standby Current 5 mA 5 Maximum Ratings 5 mA Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .............................. –65 C to +150 C Ambient Temperature with Power Applied.......................................... –55 C to +125 C Supply Voltage on VCC Relative to GND[2] ... –0.5V to + 4.6V DC Voltage Applied to Outputs[6] in High-Z State .......................................–0.5V to VCC + 0.5V Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Range Ambient Temperature VCC 0 C to +70 C 3.3V  10% –40 C to +85 C 3.3V  10% Commercial Industrial DC Input Voltage[2] .................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range –10 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min.,  IOH = – 4.0 mA VOL Output LOW Voltage VCC = Min.,  IOL = 8.0 mA VIH Input HIGH Voltage Min. –12 Max. 2.4 Min. Max. Min. 2.4 0.4 Voltage[2] –15 Max. 2.4 0.4 Unit V 0.4 V 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V –0.3 0.8 –0.3 0.8 –0.3 0.8 V VIL Input LOW IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 –1 +1 A IOZ Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 –1 +1 –1 +1 A ICC VCC Operating  Supply Current VCC = Max.,  IOUT = 0 mA, f = fMAX = 1/tRC 80 mA ISB1 ISB2 Comm’l 90 Ind’l 85 85 Automatic CE  Max. VCC, CE > VIHComm’l Power-down Current VIN > VIH or  Ind’l — TTL Inputs VIN < VIL, f = fMAX 15 Automatic CE  Max. VCC,  Comm’l Power-down Current CE > VCC – 0.3V, Ind’l — CMOS Inputs VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 5 mA 15 15 mA 15 mA 5 5 mA 5 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3V Max. Unit 8 pF 8 pF Notes: 2. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05131 Rev. *E Page 2 of 7 [+] Feedback CY7C1018CV33 AC Test Loads and Waveforms[4] R 317 3.3V ALL INPUT PULSES 3.0V 90% OUTPUT R2 351 30 pF 3.3V GND 10% Rise Time: 1 V/ns (a) High-Z characteristics: 90% 10% Fall Time: 1 V/ns (b) R 317 OUTPUT R2 351 5 pF (c) Switching Characteristics Over the Operating Range[5] -10 Parameter Description Min. -12 Max. Min. -15 Max. Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 12 15 ns tDOE OE LOW to Data Valid 5 6 7 ns tLZOE OE LOW to Low-Z tHZOE OE HIGH to High-Z[6, 7] tLZCE CE LOW to Low-Z 10 10 3 [7] CE HIGH to High-Z tPU[8] tPD[8] CE LOW to Power-up 12 3 ns 3 0 10 ns 7 6 ns 7 ns 0 12 ns ns 0 3 0 CE HIGH to Power-down 15 6 5 ns 3 0 5 [6, 7] 15 3 0 tHZCE Write Cycle 12 ns 15 ns [9, 10] tWC Write Cycle Time 10 12 15 ns tSCE CE LOW to Write End 8 9 10 ns tAW Address Set-up to Write End 8 9 10 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns tPWE WE Pulse Width 7 8 10 ns tSD Data Set-up to Write End 5 6 8 ns tHD Data Hold from Write End 0 0 0 ns 3 3 3 ns tLZWE tHZWE WE HIGH to Low-Z[7] WE LOW to High-Z[6, 7] 5 6 7 ns Notes: 4. AC characteristics (except High-Z) for all speeds are tested using the Thèvenin load shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. This parameter is guaranteed by design and is not tested. 9. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05131 Rev. *E Page 3 of 7 [+] Feedback CY7C1018CV33 Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for Read cycle. 13. Address valid prior to or coincident with CE transition LOW. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05131 Rev. *E Page 4 of 7 [+] Feedback CY7C1018CV33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 16 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[10, 15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 16 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE OE WE I/O0–I/O7 Mode Power H X X High-Z Power-down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High-Z Selected, Outputs Disabled Active (ICC) Note: 16. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05131 Rev. *E Page 5 of 7 [+] Feedback CY7C1018CV33 Ordering Information Speed (ns) Ordering Code 10 CY7C1018CV33-10VC 12 15 Package Diagram 51-85041 Package Type Operating Range 32-lead 300-mil Molded SOJ Commercial CY7C1018CV33-12VC 32-lead 300-mil Molded SOJ Commercial CY7C1018CV33-12VXI 32-lead 300-mil Molded SOJ (Pb-Free) Industrial CY7C1018CV33-15VXC 32-lead 300-mil Molded SOJ (Pb-Free) Commercial Package Diagram 32-lead (300-mil) Molded SOJ (51-85041) 51-85041-*A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05131 Rev. *E Page 6 of 7 © Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1018CV33 Document History Page Document Title: CY7C1018CV33 128K x 8 Static RAM Document Number: 38-05131 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109426 12/14/01 HGK New Data Sheet *A 113432 04/10/02 NSL AC Test Loads split based on speed *B 115046 05/30/02 HGK ICC and ISB1 modified *C 116476 09/16/02 CEA Add applications foot note on data sheet, pg 1 *D 493543 See ECN NXR Added Industrial Operating Range Removed 8 ns speed bin from Product offering Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the Ordering Information Table *E 3057515 10/13/2010 PRAS Document #: 38-05131 Rev. *E Obsolete document Page 7 of 7 [+] Feedback