CY7C1019CV33-15VC

CY7C1019CV33 128K x 8 Static RAM Features • Pin and function compatible with CY7C1019BV33 • High speed — tAA = 10 ns • CMOS for optimum speed/power • Data retention at 2.0V • Center power/ground pinout • Automatic power-down when deselected • Easy memory expansion with CE and OE options • Available in Pb-free and non Pb-free 48-ball VFBGA, 32-pin TSOP II and 400-mil SOJ package device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1019CV33 is available in Standard 48-ball FBGA, 32-pin TSOP II and 400-mil-wide SOJ packages Functional Description The CY7C1019CV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This Logic Block Diagram Pin Configuration SOJ/TSOP II Top View A0 A1 A2 A3 CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 I/O INPUT BUFFER 0 A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O ROW DECODER 1 I/O SENSE AMPS 2 128K x 8 ARRAY I/O I/O I/O I/O I/O 3 4 5 CE WE OE COLUMN DECODER POWER DOWN 6 7 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 Cypress Semiconductor Corporation Document #: 38-05130 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 [+] [+] Feedback CY7C1019CV33 Pin Configuration[1] 48-ball VFBGA (Top View) 1 NC I/O0 I/O1 VSS VCC I/O2 I/O3 NC 2 OE NC NC NC NC NC NC A10 3 A2 A1 A0 NC NC A14 A15 A16 4 A6 A5 A4 A3 NC A11 A12 A13 5 A7 CE NC NC NC I/O4 WE A9 6 NC I/O7 I/O6 VCC VSS I/O5 A8 NC A B C D E F G H Selection Guide -10 Maximum Access Time Maximum Operating Current Maximum Standby Current Note: 1. NC pins are not connected on the die. -12 12 75 5 -15 15 70 5 Unit ns mA mA 10 80 5 Document #: 38-05130 Rev. *F Page 2 of 10 [+] [+] Feedback CY7C1019CV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................–0.5V to VCC + 0.5V DC Input Voltage[2] .................................–0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 10% 3.3V ± 10% Electrical Characteristics Over the Operating Range –10 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Test Conditions Min. 2.4 0.4 2.0 –0.3 –1 –1 GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 VCC + 0.3 0.8 +1 +1 80 2.0 –0.3 –1 –1 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 75 2.0 –0.3 –1 –1 Output HIGH Voltage VCC = Min., IOH = –4.0 mA Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current GND < VI < VCC Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current —TTL Inputs Automatic CE Power-down Current —CMOS Inputs VCC = Min., IOL = 8.0 mA –12 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 70 –15 Max. Unit V V V V µA µA mA ISB1 15 15 15 mA ISB2 5 5 5 mA Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF Notes: 2. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05130 Rev. *F Page 3 of 10 [+] [+] Feedback CY7C1019CV33 AC Test Loads and Waveforms[4] R 317 Ω 3.3V OUTPUT 30 pF R2 GND 351Ω Rise Time: 1 V/ns 3.0V 90% 10% ALL INPUT PULSES 90% 10% High-Z characteristics: R 317 Ω 3.3V OUTPUT 5 pF R2 351Ω (b) Fall Time: 1 V/ns (a) (c) Switching Characteristics Over the Operating Range[5] -10 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[8] tPD[8] Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE LOW to Low CE HIGH to High Z[6, 7] 3 5 0 10 10 8 8 0 0 7 5 0 3 5 12 9 9 0 0 8 6 0 3 6 0 12 15 10 10 0 0 10 8 0 3 7 Z[6, 7] Z[7] 0 5 3 6 0 15 3 10 5 0 6 3 7 10 10 3 12 6 0 7 12 12 3 15 7 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -12 Max. Min. -15 Max. Unit CE LOW to Power-Up CE HIGH to Power-Down Cycle[9, 10] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z [7] WE LOW to High Z[6, 7] Notes: 4. AC characteristics (except High-Z) for all speeds are tested using the Thevenin load shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. This parameter is guaranteed by design and is not tested. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05130 Rev. *F Page 4 of 10 [+] [+] Feedback CY7C1019CV33 Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS tSCE CE tSA tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05130 Rev. *F Page 5 of 10 [+] [+] Feedback CY7C1019CV33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 16 tHZOE DATAIN VALID tHD Write Cycle No. 3 (WE Controlled, OE LOW)[15] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 16 tHZWE DATA VALID tLZWE tHD tPWE tHA Truth Table CE H L L L OE X L X H WE X H L H High Z Data Out Data In High Z I/O0–I/O7 Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Note: 16. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05130 Rev. *F Page 6 of 10 [+] [+] Feedback CY7C1019CV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1019CV33-10VC CY7C1019CV33-10ZXC CY7C1019CV33-10ZXI 12 CY7C1019CV33-12VC CY7C1019CV33-12ZC CY7C1019CV33-12ZXC CY7C1019CV33-12VI CY7C1019CV33-12BVXI 15 CY7C1019CV33-15VC CY7C1019CV33-15VXC CY7C1019CV33-15ZXC CY7C1019CV33-15ZXI 51-85033 51-85150 51-85033 51-85033 51-85095 51-85095 51-85033 51-85095 Package Diagram 51-85033 51-85095 Package Type 32-pin 400-Mil Molded SOJ 32-pin TSOP II (Pb-Free) 32-pin TSOP II (Pb-Free) 32-pin 400-Mil Molded SOJ 32-pin TSOP II 32-pin TSOP II (Pb-Free) 32-pin 400-Mil Molded SOJ 48-ball VFBGA (Pb-Free) 32-pin 400-Mil Molded SOJ 32-pin 400-Mil Molded SOJ (Pb-Free) 32-pin TSOP II (Pb-Free) 32-pin TSOP II (Pb-Free) Industrial Commercial Industrial Industrial Commercial Operating Range Commercial Package Diagrams 32-pin (400-Mil) Molded SOJ (51-85033) 51-85033-*B Document #: 38-05130 Rev. *F Page 7 of 10 [+] [+] Feedback CY7C1019CV33 Package Diagrams (continued) 32-pin TSOP II (51-85095) 51-85095-** Document #: 38-05130 Rev. *F Page 8 of 10 [+] [+] Feedback CY7C1019CV33 Package Diagrams (continued) 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) TOP VIEW BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C 8.00±0.10 8.00±0.10 0.75 5.25 D E F G H A B C D E 2.625 F G H A B 6.00±0.10 A 1.875 0.75 3.75 B 6.00±0.10 0.55 MAX. 0.25 C 0.15(4X) 0.21±0.05 0.10 C 51-85150-*D SEATING PLANE 0.26 MAX. C 1.00 MAX All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05130 Rev. *F Page 9 of 10 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C1019CV33 Document History Page Document Title: CY7C1019CV33 128K x 8 Static RAM Document Number: 38-05130 REV. ** *A *B *C *D *E ECN NO. 109245 113431 115047 119796 123030 419983 Issue Date 12/16/01 04/10/02 08/01/02 10/11/02 12/17/02 See ECN Orig. of Change HGK NSL HGK DFP DFP NXR New Data Sheet AC Test Loads split based on speed Added TSOP II Package and I Temp. Improved ICC limits Updated standby current from 5 nA to 5 mA Updated Truth Table to reflect single Chip Enable option Added 48-ball VFBGA Package Added lead-free parts in Ordering Information Table Replaced Package Name column with Package Diagram in the Ordering Information Table Removed 8 ns speed bin from Product offering Added note #1 on page #2 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated Ordering Information Description of Change *F 493543 See ECN NXR Document #: 38-05130 Rev. *F Page 10 of 10 [+] [+] Feedback