CY7C1049BN

1CY7C1049BN CY7C1049BN 512K x 8 Static RAM Features • High speed — tAA = 12 ns • Low active power — 1320 mW (max.) • Low CMOS standby power (Commercial L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features Functional Description[1] The CY7C1049BN is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049BN is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout. Logic Block Diagram Pin Configuration SOJ Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 ROW DECODER I/O2 SENSE AMPS 512K x 8 ARRAY I/O3 I/O4 I/O5 CE WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 A 11 A 12 A 13 A14 A15 A16 A17 A18 Cypress Semiconductor Corporation Document #: 001-06501 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 2, 2006 [+] [+] Feedback CY7C1049BN Selection Guide 7C1049BN-12 7C1049BN-15 7C1049BN-17 7C1049BN-20 7C1049BN-25 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Com’l Com’l/Ind’l L Ind’l 12 240 8 15 220 8 17 195 8 0.5 20 185 8 0.5 9 25 180 8 0.5 9 Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[2] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ....................................–0.5V to VCC + 0.5V DC Input Voltage[2] .................................–0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 4.5V–5.5V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, Com’l CE > VCC – 0.3V, Com’l VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Ind’l Ind’l Note: 2. Minimum voltage is–2.0V for pulse durations of less than 20 ns. Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 7C1049B-12 Min. 2.4 0.4 2.2 –0.3 –1 –1 VCC+0.3 0.8 +1 +1 240 40 Max. 7C1049B-15 Min. 2.4 0.4 2.2 –0.3 –1 –1 VCC+0.3 0.8 +1 +1 220 40 Max. 7C1049B-17 Min. 2.4 0.4 2.2 –0.3 –1 –1 VCC+0.3 0.3 +1 +1 195 40 Max. Unit V V V V µA µA mA mA Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs ISB2 8 L L - 8 - 8 0.5 8 0.5 mA mA mA mA Document #: 001-06501 Rev. ** Page 2 of 10 [+] [+] Feedback CY7C1049BN Electrical Characteristics Over the Operating Range (continued) Test Conditions Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Com’l Com’l Ind’l Ind’l L L VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.3 –1 –1 7C1049B-20 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 185 40 2.2 –0.3 –1 –1 Max. 7C1049B-25 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 180 40 Max. Unit V V V V µA µA mA mA ISB2 8 0.5 8 0.5 8 0.5 8 0.5 mA mA mA mA Capacitance[3] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255Ω R1 481Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255Ω GND ≤ 3 ns R1 481Ω ALL INPUT PULSES 3.0V 90% 10% 90% 10% ≤ 3 ns Equivalent to: THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Note: 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06501 Rev. ** Page 3 of 10 [+] Feedback CY7C1049BN Switching Characteristics[4] Over the Operating Range 7C1049B-12 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE VCC(typical) to the First Access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[7] OE HIGH to High CE LOW to Low CE HIGH to High Z[6, 7] 3 6 0 12 12 10 10 0 0 10 7 0 3 6 15 12 12 0 0 12 8 0 3 7 0 15 17 12 12 0 0 12 8 0 3 8 Z[6, 7] Z[7] 0 6 3 7 0 17 3 12 6 0 7 3 7 1 12 12 3 15 7 0 7 1 15 15 3 17 8 1 17 17 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C1049B-15 Min. Max. 7C1049B-17 Min. Max. Unit CE LOW to Power-Up CE HIGH to Power-Down [8, 9] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[7] WE LOW to High Z[6, 7] Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-06501 Rev. ** Page 4 of 10 [+] [+] Feedback CY7C1049BN Switching Characteristics[4] Over the Operating Range (continued) 7C1049B-20 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Cycle[8] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[7] WE LOW to High Z[6, 7] 20 13 13 0 0 13 9 0 3 8 25 15 15 0 0 15 10 0 5 10 ns ns ns ns ns ns ns ns ns ns VCC(typical) to the First Access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[7] OE HIGH to High Z CE LOW to Low CE HIGH to High [6, 7] 7C1049B-25 Min. 1 25 Max. Unit 1 ns 25 5 25 10 0 10 5 10 0 25 ns ns ns ns ns ns ns ns ns ns Description Min. 1 20 Max. 20 3 20 8 0 8 3 8 0 20 Z[7] Z[6, 7] CE LOW to Power-Up CE HIGH to Power-Down Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR[3] tR [10] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Com’l Ind’l Conditions[11] L VCC = VDR = 3.0V, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V Min. 2.0 Max 200 1 Unit V µA mA ns ns 0 tRC Notes: 10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. 11. No input may exceed VCC + 0.5V. Document #: 001-06501 Rev. ** Page 5 of 10 [+] [+] Feedback CY7C1049BN Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 001-06501 Rev. ** Page 6 of 10 [+] [+] Feedback CY7C1049BN Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[15, 16] tWC ADDRESS tSCE CE tSA tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[15, 16] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 17 tHZOE Notes: 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 17. During this period the I/Os are in the output state and input signals should not be applied. tHD DATAIN VALID Document #: 001-06501 Rev. ** Page 7 of 10 [+] [+] Feedback CY7C1049BN Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[16] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 17 tHZWE DATA VALID tPWE tHA tHD tLZWE Truth Table CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Power-down Read Write Selected, Output disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 12 15 Ordering Code CY7C1049BN-12VC CY7C1049BN-12VXC CY7C1049BN-15VC CY7C1049BN-15VXC CY7C1049BN-15VI CY7C1049BN-15VXI 17 CY7C1049BN-17VC CY7C1049BNL-17VC CY7C1049BN-17VXC 20 CY7C1049BN-20VC CY7C1049BNL-20VC CY7C1049BN-20VXC CY7C1049BN-20VI CY7C1049BN-20VXI 25 CY7C1049BNL-25VC CY7C1049BN-25VI CY7C1049BN-25VXI Package Diagram 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 51-85090 Package Type 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ (Pb-free) 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ (Pb-free) 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ (Pb-free) 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ (Pb-free) 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ (Pb-free) 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ (Pb-free) 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ (Pb-free) Commercial Industrial Industrial Commercial Industrial Operating Range Commercial Please contact local sales representative regarding availability of these parts. Document #: 001-06501 Rev. ** Page 8 of 10 [+] [+] Feedback CY7C1049BN Package Diagram 36-Lead (400-Mil) Molded SOJ (51-85090) 51-85090-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06501 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C1049BN Document History Page Document Title: CY7C1049BN 512K x 8 Static RAM Document Number: 001-06501 REV. ** ECN NO. 424111 Issue Date See ECN Orig. of Change NXR New Data Sheet Description of Change Document #: 001-06501 Rev. ** Page 10 of 10 [+] [+] Feedback