CY7C128A-15PC

28A CY7C128A 2K x 8 Static RAM Features • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 660 mW (commercial) — 688 mW (military—20 ns) • Low standby power — 110 mW (20 ns) • TTL-compatible inputs and outputs • Capable of withstanding greater than 2001V electrostatic discharge • VIH of 2.2V provided by an active LOW Chip Enable (CE), and active LOW Output Enable (OE) and three-state drivers. The CY7C128A has an automatic power-down feature, reducing the power consumption by 83% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the eight I/O pins (I/O0 through I/O7) is written into the memory location specified on the address pins (A0 through A10). Reading the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the eight I/O pins. The I/O pins remain in high-impedance state when Chip Enable (CE) or Output Enable (OE) is HIGH or Write Enable (WE) is LOW. The CY7C128A utilizes a die coat to insure alpha immunity. Functional Description The CY7C128A is a high-performance CMOS static RAM organized as 2048 words by 8 bits. Easy memory expansion is Logic Block Diagram Pin Configurations DIP/SOJ/SOIC Top View A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 24 23 2 22 3 4 21 5 20 6 19 7C128A 18 7 17 8 9 16 10 15 11 14 12 13 VCC A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 C128A–2 INPUT BUFFER I/O0 I/O1 ROW DECODER A10 A9 A8 A7 A6 A5 A4 CE WE OE I/O2 SENSE AMPS 128 x 16 x 8 ARRAY I/O3 I/O4 I/O5 A4 A3 A2 A1 A0 I/O0 I/O1 LCC Top View A5 A6 A7 VCC A8 3 2 1 24 23 4 22 5 21 6 20 7 7C128A 19 8 18 9 17 10 16 11 12 13 14 15 I/O 2 GND I/O 3 I/O 4 I/O 5 COLUMN DECODER POWER DOWN I/O6 I/O7 A9 WE OE A10 CE I/O7 I/O6 C128A–3 A3 A2 A1 A0 C128A–1 Selection Guide Maximum Access Time (ns) Maximum Operating Commercial Current (mA) Military Maximum Standby Commercial Current (mA) Military 7C128A-15 15 120 40 7C128A-20 20 120 125 20 20 7C128A-25 25 120 125 20 20 7C128A-35 35 120 125 20 20 7C128A-45 45 120 125 20 20 Cypress Semiconductor Corporation Document #: 38-05028 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 24, 2001 CY7C128A Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V DC Input Voltage............................................ –3.0V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Military[1] Ambient Temperature 0°C to +70°C –55°C to +125°C VCC 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range[2] 7C128A-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] Input Load Current Output Leakage Current Output Short CircuitCurrent[4] VCC Operating Supply Current Automatic CE Power-Down Current Automatic CE Power-Down Current GND < VI < VCC GND < VI < VCC Output Disabled VCC = Max., VOUT = GND VCC = Max. IOUT = 0 mA Max. VCC, CE > VIH, Min. Duty Cycle = 100% Max. VCC, CE1 >VCC–0.3V, VIN > VCC–0.3V or VIN < 0.3V Com’l Mil Com’l Mil Com’l Mil Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.5 –10 –10 Min. 2.4 0.4 VCC 0.8 +10 +10 –300 120 40 40 2.2 –0.5 –10 –10 Max. 7C128A-20 Min. 2.4 0.4 VCC 0.8 +10 +10 –300 120 125 40 40 20 20 2.2 –0.5 –10 –10 Max. 7C128A-25 Min. 2.4 0.4 VCC 0.8 +10 +10 –300 120 125 20 40 20 20 2.2 –0.5 –10 –10 Max. 7C128A-35,45 Min. 2.4 0.4 VCC 0.8 +10 +10 –300 120 125 20 20 20 20 mA mA Max. Unit V V V V µA µA mA mA ISB2 Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. VIL (min.) = –3.0V for pulse durations less than 30 ns. 4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05028 Rev. ** Page 2 of 10 CY7C128A AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R2 255 Ω R1 481Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255 Ω R1 481Ω ALL INPUT PULSES 3.0V GND 10% 90% 90% 10% ≤ 5 ns ≤ 5 ns (a) (b) C128A–4 C128A–5 THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Switching Characteristics Over the Operating Range[2, 6] 7C128A-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z [7] 7C128A-20 Min. 20 Max. 7C128A-25 Min. 25 Max. 7C128A-35 Min. 35 Max. 7C128A-45 Min. 45 Max. Unit ns 45 5 45 20 3 15 5 15 0 25 40 30 30 0 0 20 15 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 5 ns ns Description Min. 15 Max. 15 5 15 10 3 8 5 8 0 15 15 12 12 0 0 12 10 0 7 5 5 20 15 15 0 0 15 10 0 0 5 3 5 20 5 20 10 3 8 5 8 0 20 20 20 20 0 0 15 10 0 7 5 25 5 25 12 3 10 5 10 0 20 25 25 25 0 0 20 15 0 7 5 35 35 15 12 15 20 CE LOW to Low Z[8] CE HIGH to High Z[7, 8] CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z [7] WRITE CYCLE[9] 10 WE HIGH to Low Z Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05028 Rev. ** Page 3 of 10 CY7C128A Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID C128A–6 Read Cycle No. 2[10, 12] CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB C128A–7 tRC tHZOE tHZCE DATA VALID HIGH IMPEDANCE DATA OUT Write Cycle No. 1 (WE Controlled)[9, ] tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATAIN VALID tHZWE DATA I/O DATA UNDEFINED C128A–8 tAW tPWE tHA tHD tLZWE HIGH IMPEDANCE Notes: 10. WE is HIGH for read cycle. 11. Device is continuously selected. OE, CE = VIL. 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write. Document #: 38-05028 Rev. ** Page 4 of 10 CY7C128A Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[9, 13, 14] tWC ADDRESS tSA CE tAW tPWE WE tSD DATA IN DATA IN VALID tHZWE DATA I/O HIGH IMPEDANCE DATA UNDEFINED C128A–9 tSCE tHA tHD Notes: 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 ISB 5.5 6.0 ICC NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 –55 ISB 25 125 VCC = 5.0V VIN = 5.0V ICC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA = 2 5°C) SUPPLY VOLTAGE(V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA = 25°C 1.6 1.4 1.2 1.0 AMBIENT TEMPERATURE(°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA = 25°C VCC = 5.0V 0.8 0.6 –55 25 125 SUPPLY VOLTAGE(V) AMBIENT TEMPERATURE(°C) OUTPUT SINK CURRENT (mA) OUTPUT VOLTAGE(V) Document #: 38-05028 Rev. ** Page 5 of 10 CY7C128A Typical DC and AC Characteristics (continued) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED IPO 2.5 DELTA t AA (ns) 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 NORMALIZED ICC 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC = 4.5V TA = 25°C TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0 10 20 30 40 VCC = 5.0V TA = 25°C VIN = 0.5V NORMALIZED I CC vs. CYCLE TIME 600 800 1000 SUPPLY VOLTAGE(V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Ordering Information Speed (ns) 15 Ordering Code CY7C128A-15PC CY7C128A-15VC CY7C128A-15SC CY7C128A-20PC CY7C128A-20VC CY7C128A-20SC CY7C128A-20DMB CY7C128A-20LMB CY7C128A-25PC CY7C128A-25VC CY7C128A-25SC CY7C128A-25DMB CY7C128A-35PC CY7C128A-35VC CY7C128A-35SC CY7C128A-35DMB CY7C128A-45PC CY7C128A-45VC CY7C128A-45SC CY7C128A-45DMB CY7C128A-45LMB Package Name P13 V13 S13 P13 V13 S13 D14 L53 P13 V13 S13 D14 P13 V13 S13 D14 P13 V13 S13 D14 L53 Package Type 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) CerDIP 24-Pin Rectangular Leadless Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) CerDIP 24-Pin Rectangular Leadless Chip Carrier Operating Range Commercial 20 Commercial Military Commercial 25 35 Military Commercial 45 Military Commercial Military Document #: 38-05028 Rev. ** Page 6 of 10 CY7C128A MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL Max. IIX IOZ ICC ISB Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Switching Characteristics Parameter READ CYCLE tRC tAA tOHA tACE tDOE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Subgroups Document #: 38-05028 Rev. ** Page 7 of 10 CY7C128A Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9 Config.A 51-80031 24-Pin Rectangular Leadless Chip Carrier L53 51-80066 Document #: 38-05028 Rev. ** Page 8 of 10 CY7C128A Package Diagrams (continued) 24-Lead (300-Mil) Molded DIP P13/P13A 51-85013-A 24-Lead (300-Mil) Molded SOJ V13 51-85030-A Document #: 38-05028 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C128A Document Title: CY7C128A 2K x 8 Static RAM Document Number: 38-05028 REV. ** ECN NO. 106814 Issue Date 09/10/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00094 to 38-05028 Document #: 38-05028 Rev. ** Page 10 of 10 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.