CY7C1308CV25-100BZC

PRELIMINARY CY7C1308CV25 9-Mbit 4-Word Burst SRAM with DDR-I Architecture Features • 9-Mbit density (256 Kbit x 36) • 167-MHz clock for high bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 333 MHz @ 167 MHz) • Two input clocks (K and K) for precise DDR timing—SRAM uses rising edges only • Two output clocks (C and C) account for clock skew and flight time mismatching • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 2.5V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–1.9V) • 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11 x 15 matrix) • JTAG 1149.1 compatible test access port Functional Description The CY7C1308CV25 is a 2.5V Synchronous Pipelined SRAM equipped with DDR-I (Double Data Rate) architecture. The DDR-I architecture consists of an SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Every Read or Write operation is associated with four words that burst sequentially into or out of the device. The burst counter takes in the least two significant bits of the external address and bursts four 36-bit words. Depth expansion is accomplished with Port Selects for each port. Port Selects allow each port to operate independently. Asynchronous inputs include impedance match (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) are also provided for maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Configuration CY7C1308CV25 – 256K x 36 Logic Block Diagram (CY7C1308CV25) A(1:0) 18 A(17:0) 16 Burst Logic LD K K CLK Gen. Write Add. Decode Read Add. Decode Address A(17:2) Register Write Write Write Write Reg Reg Reg Reg 256K x 36 Array 36 Output Logic Control Read Data Reg. Vref R/W BWS[3:0] 144 Control Logic 72 72 Reg. Reg. 36 Reg. C C CQ CQ 36 DQ[35:0] Cypress Semiconductor Corporation Document #: 38-05502 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 1, 2004 PRELIMINARY Selection Guide 167 MHz Maximum Operating Frequency Maximum Operating Current 167 650 133 MHz 133 620 CY7C1308CV25 100 MHz 100 590 Unit MHz mA Pin Configuration CY7C1308CV25 (256K × 36) – 11 × 15 FBGA 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC NC NC NC NC NC NC NC TDO 2 DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 BWS1 BWS0 A1 VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI GND/144M NC/36M NC/18M GND/72M Pin Definitions Name DQ[35:0] I/O Input/OutputSynchronous Description Data Input/Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid Write operations. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When Read access is deselected, Q[35:0] are automatically three-stated. Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and Read/Write direction. All transactions operate on a burst of 4 data (two clock periods of bus activity). Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1308CV25 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27] All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. These address inputs are multiplexed for both Read and Write operations. A0 and A1 are the inputs to the burst counter. These are incremented in a linear fashion internally. 18 address inputs are needed to access the entire memory array. All the address inputs are ignored when the part is deselected. Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and hold times around edge of K. LD InputSynchronous InputSynchronous BWS0, BWS1, BWS2, BWS3 A, A0, A1 InputSynchronous R/W InputSynchronous Document #: 38-05502 Rev. *A Page 2 of 18 PRELIMINARY Pin Definitions (continued) Name C I/O Input-Clock Description CY7C1308CV25 Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[35:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[35:0] when in single clock mode. CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock (C) of the DDR-I. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC timing table. CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock (C) of the DDR-I. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC timing table. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ and Q[35:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Not connected to the die. Can be tied to any voltage level. Address expansion for 18M. This is not connected to the die. Address expansion for 36M. This is not connected to the die. Address expansion for 72M. This should be tied LOW. Address expansion for 144M. This should be tied LOW. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and outputs as well as AC measurement points. Power supply inputs to the core of the device. Ground for the device. Power supply inputs for the outputs of the device. All synchronous control (R/W, LD, BWS0, BWS1, BWS2, BWS3) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). Read Operations The CY7C1308CV25 is organized internally as an array of 256K x 36. Accesses are completed in a burst of four sequential 36-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the Positive Input Clock (K). The address presented to Address inputs are stored in the Read address register and the least two significant bits of the address are presented to the burst counter. The burst counter increments the address in a linear fashion. Following the next K clock rise the corresponding 36-bit word of data from this address location is driven onto the Q[35:0] using C as the output timing reference. On the subsequent rising edge of C the next 36-bit data word from the Page 3 of 18 C Input-Clock K Input-Clock K CQ Input-Clock Echo Clock CQ Echo Clock ZQ Input TDO TCK TDI TMS NC NC/18M NC/36M GND/72M GND/144M VREF VDD VSS VDDQ Output Input Input Input N/A N/A N/A Input Input InputReference Power Supply Ground Power Supply Introduction Functional Overview The CY7C1308CV25 is a synchronous pipelined Burst SRAM equipped with DDR interface. Accesses are initiated on the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of output clocks (C and C or K and K when in single clock mode). All synchronous data inputs (D[35:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[35:0]) pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single clock mode). Document #: 38-05502 Rev. *A PRELIMINARY address location generated by the burst counter is driven onto the Q[35:0]. This process continues until all four 36-bit data words have been driven out onto Q[35:0]. The requested data will be valid 3 ns from the rising edge of the output clock (C or C, 167-MHz device). In order to maintain the internal logic, each Read access must be allowed to complete. Each Read access consists of four 36-bit data words and takes two clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C or K and K when in single clock mode). When the read port is deselected, the CY7C1308CV25 will first complete the pending read transactions. Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to Address inputs are stored in the Write address register and the least two significant bits of the address are presented to the burst counter. The burst counter increments the address in a linear fashion. On the following K clock rise the data presented to D[35:0] is latched and stored into the 36-bit Write Data register provided BWS[3:0] are asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D[35:0] is also stored into the Write Data Register provided BWS[3:0] are asserted active. This process continues for one more cycle until four 36-bit words (a total of 144 bits) of data are stored in the SRAM. The 144 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the positive input clock (K). Doing so will pipeline the data flow such that 36-bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When deselected, the Write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1308CV25. A Write operation is initiated as described in the Write Operation section above. The bytes that are written are determined by BWS[3:0] which are sampled with each set of 36-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion CY7C1308CV25 of a Write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1308CV25 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-on. This function is a strap option and not alterable during device operation. DDR Operation The CY7C1308CV25 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. At slower frequencies, the CY7C1308CV25 requires a single No Operation (NOP) cycle when transitioning from a Read to a Write cycle. At higher frequencies, a second NOP cycle may be required to prevent bus contention. If a Read occurs after a Write cycle, address and data for the Write are stored in registers. The Write information must be stored because the SRAM can not perform the last word Write to the array without conflicting with the Read. The data stays in this register until the next Write cycle occurs. On the first Write cycle after the Read(s), the stored data from the earlier Write will be written into the SRAM array. This is called a Posted Write. Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Echo Clocks Echo clocks are provided on the DDR-I to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-I. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the DDR-I. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Programmable Impedance An external resistor, RQ must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ=1.5V. The output impedance is adjusted every 1024 cycles to adjust for drifts in supply voltage and temperature. Document #: 38-05502 Rev. *A Page 4 of 18 PRELIMINARY Application Example[1] DQ A ZQ CQ/CQ# LD# R/W# C C# K K# CY7C1308CV25 SRAM#1 R = 250ohms DQ A ZQ CQ/CQ# LD# R/W# C C# K K# SRAM#2 R = 250ohms DQ Addresses Cycle Start# R/W# Return CLK Source CLK Return CLK# Source CLK# Echo Clock1/Echo Clock#1 Echo Clock2/Echo Clock#2 BUS MASTER (CPU or ASIC) Vterm = 0.75V R = 50ohms Vterm = 0.75V Truth Table[2,3,4,5,6,7] Operation Write Cycle: Load address; wait one cycle; input write data on 2 consecutive K and K rising edges. Read Cycle: Load address; wait one cycle; read data on 2 consecutive C and C rising edges. NOP: No Operation Standby: Clock Stopped K L-H LD L R/W L[8] DQ D(A1)at K(t+1)↑ DQ D(A2) at K(t+1)↑ DQ D(A3) at K(t+2) ↑ DQ D(A4) at K(t+2) ↑ L-H L H[9] Q(A1) at C(t+1)↑ High-Z Q(A2) at C(t+1) ↑ High-Z Q(A3) at C(t+2)↑ High-Z) Q(A4) at C(t+2) ↑ High-Z L-H Stopped H X X X Previous State Previous State Previous State Previous State Linear Burst Address Table First Address (External) X..X00 X..X01 X..X10 X..X11 Second Address (Internal) X..X01 X..X10 X..X11 X..X00 Third Address (Internal) X..X10 X..X11 X..X00 X..X01 Fourth Address (Internal) X..X11 X..X00 X..X01 X..X10 Notes: 1. The above application shows 2 DDR-I being used. 2. X = “Don't Care“, H = Logic HIGH, L = Logic LOW, ↑represents rising edge. 3. Device will power-up deselected and the outputs in a three-state condition. 4. “A1” represents address location latched by the devices when transaction was initiated. A2, A3 and A4 represents the internal address sequence in the burst. 5. “t” represents the cycle at which a Read/Write operation is started. t+1 and t+2 are the first and second clock cycles succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. This signal was HIGH on previous K clock rise. Initiating consecutive Write operations on consecutive K clock rises is not permitted. The device will ignore the second Write request. 9. This signal was LOW on previous K clock rise. Initiating consecutive Read operations on consecutive K clock rises is not permitted.The device will ignore the second Read request. Document #: 38-05502 Rev. *A Page 5 of 18 PRELIMINARY Write Cycle Descriptions[2,10] BWS0 BWS1 BWS2 BWS3 L L L L H H H H H H H H L L H H L L H H H H H H L L H H H H L L H H H H L L H H H H H H L L H H K L-H L-H L-H L-H L-H L-H K Comments CY7C1308CV25 During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. No data is written into the device during this portion of a Write operation. L-H No data is written into the device during this portion of a Write operation. Note: 10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1, BWS2, BWS3 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved. Document #: 38-05502 Rev. *A Page 6 of 18 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied .................................................. −55°C to +125°C Supply Voltage on VDD Relative to GND .........−0.5V to +3.6V DC Applied to Outputs in High-Z...........−0.5V to VDDQ + 0.5V DC Input Voltage[12] ................................−0.5V to VDDQ + 0.5V CY7C1308CV25 Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... >2 001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Com’l Ambient Temperature (TA) 0°C to +70°C VDD[13] 2.5 ± 0.1V VDDQ[13] 1.4V to 1.9V Electrical Characteristics Over the Operating Range [14] DC Electrical Characteristics Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL VIN IX IOZ VREF IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[12] Input LOW Voltage[12,15] Clock Input Voltage Input Load Current Output Leakage Current VDD Operating Supply GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, 100 MHz f = fMAX = 1/tCYC 133 MHz 167 MHz ISB1 Automatic Power-Down Max. VDD, Both Ports 100 MHz Deselected, VIN ≥ VIH or 133 MHz VIN ≤ VIL f = fMAX = 1/tCYC, 167 MHz Inputs Static Test Conditions Min. VREF + 0.2 – Typ. – – Note 16 Note 17 IOH = –0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min. 2.4 1.4 VDDQ/2 – 0.12 VDDQ/2 – 0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.3 –0.3 –5 –5 0.68 0.75 Typ. 2.5 1.5 Max. 2.6 1.9 VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF – 0.1 VDDQ + 0.3 5 5 0.95 590 620 650 360 380 400 Max. – VREF – 0.2 Unit V V V V V V V V V µA µA V mA mA mA mA mA mA Unit V V Input Reference Voltage[18] Typical Value = 0.75V AC Input Requirements Parameter VIH VIL 11. Description Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Thermal Resistance[19] Parameter ΘJA ΘJC Description Test Conditions 165 FBGA Package Unit 16.7 2.5 °C/W °C/W Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for measuring Thermal Resistance (Junction to Case) thermal impedance, per EIA/JESD51. Notes: 12. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2). Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2). 13. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 14. All voltage referenced to ground. 15. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max.) = VREF – 0.2V. 16. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω