CY7C1340A-100AC

CY7C1340A 128K x 32 Synchronous-Pipelined RAM Features Functional Description • Fast access times: 5 and 7 ns • Fast clock speed: 100 and 66 MHz • Provides high-performance 3-1-1-1 access rate • Fast OE access times: 5 and 7 ns • Optimal for performance (two-cycle chip deselect, depth expansion without wait state) • Single +3.3V –5% and +10%power supply • Supports +2.5V I/O • 5V tolerant inputs except I/Os • Clamp diodes to VSSQ at all outputs • Common data inputs and outputs • Byte Write Enable and Global Write control • Three chip enables for depth expansion and address pipeline • Address, control, input, and output pipeline registers • Internally self-timed Write Cycle • Burst control pins (interleaved or linear burst sequence) • Automatic power-down for portable applications • High-density, high-speed packages • Low-capacitive bus loading • High 30-pF output drive capability at rated access time The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The CY7C1340A/GVT71128C32 SRAM integrates 131,072 × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (BW1, BW2, BW3, BW4, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV). Address, data inputs, and Write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the Write control inputs. Individual byte Write allows individual byte to be written. BW1 controls DQ1–DQ8. BW2 controls DQ9–DQ16. BW3 controls DQ17–DQ24. BW4 controls DQ25–DQ32. BW1, BW2, BW3, and BW4 can be active only with BWE being LOW. GW being LOW causes all bytes to be written. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The CY7C1340A/GVT71128C32 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium®, 680 × 0, and PowerPC™ systems and for systems that benefit from a wide synchronous data bus. Selection Guide 7C1340A-100 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Cypress Semiconductor Corporation Document #: 38-05153 Rev. *C • 3901 North First Street 7C1340A-66 Unit 5 7 ns 225 120 mA 2 2 mA • San Jose, CA 95134 • 408-943-2600 Revised March 31, 2004 CY7C1340A Functional Block Diagram[1] BYTE 1 WRITE BW1# BWE# D Q CLK BYTE 2 WRITE BW2# D Q GW# BYTE 3 WRITE BW3# D Q BYTE 4 WRITE ENABLE D CE2 Q D Q byte 2 write byte 1 write CE# Q byte 3 write D byte 4 write BW4# CE2# OE# Power Down Logic Input Register A16-A2 Address Register ADSC# CLR ADV# A1-A0 MODE Binary Counter & Logic OUTPUT REGISTER D Q Output Buffers ADSP# 128K x 8 x 4 SRAM Array ZZ DQ1DQ32 Note: 1. The functional block diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05153 Rev. *C Page 2 of 12 CY7C1340A Pin Configuration 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100-pin TQFP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1340A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC DQ16 DQ15 VCCQ VSSQ DQ14 DQ13 DQ12 DQ11 VSSQ VCCQ DQ10 DQ9 VSS NC VCC ZZ DQ8 DQ7 VCCQ VSSQ DQ6 DQ5 DQ4 DQ3 VSSQ VCCQ DQ2 DQ1 NC MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A10 A11 A12 A13 A14 A15 A16 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQ17 DQ18 VCCQ VSSQ DQ19 DQ20 DQ21 DQ22 VSSQ VCCQ DQ23 DQ24 NC VCC NC VSS DQ25 DQ26 VCCQ VSSQ DQ27 DQ28 DQ29 DQ30 VSSQ VCCQ DQ31 DQ32 NC Pin Descriptions Name Type Description A0–A16 InputSynchronous Addresses: These inputs are registered and must meet the set-up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. BW1, BW2, BW3, BW4 InputSynchronous Byte Write: A byte Write is LOW for a Write cycle and HIGH for a Read cycle. BW1 controls DQ1–DQ8. BW2 controls DQ9–DQ16. BW3 controls DQ17–DQ24. BW4 controls DQ25–DQ32. Data I/O are high-impedance if either of these inputs are LOW, conditioned by BWE being LOW. BWE InputSynchronous Write Enable: This active LOW input gates byte Write operations and must meet the set-up and hold times around the rising edge of CLK. GW InputSynchronous Global Write: This active LOW input allows a full 32-bit Write to occur independent of the BWE and BWn lines and must meet the set-up and hold times around the rising edge of CLK. Document #: 38-05153 Rev. *C Page 3 of 12 CY7C1340A Pin Descriptions Name Type Description CLK InputSynchronous Clock: This signal registers the addresses, data, chip enables, Write control and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock’s rising edge. CE InputSynchronous Chip Enable: This active LOW input is used to enable the device and to gate ADSP. CE2 InputSynchronous Chip Enable: This active LOW input is used to enable the device. CE2 InputSynchronous Chip Enable: This active HIGH input is used to enable the device. OE Input Output Enable: This active LOW asynchronous input enables the data output drivers. ADV InputSynchronous Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). ADSP InputSynchronous Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. ADSC InputSynchronous Address Status Controller: This active LOW input causes device to be de-selected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon Write control inputs. MODE InputStatic Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst. ZZ InputAsynchronous Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). DQ1– DQ32 Input/ Output Data Inputs/Outputs: First Byte is DQ1–DQ8. Second Byte is DQ9–DQ16. Third Byte is DQ17–DQ24. Fourth Byte is DQ25–DQ32. Input data must meet set-up and hold times around the rising edge of CLK. VCC Supply Power Supply: +3.3V –5% to +10%. Pin 14 does not have to be connected directly to VCC as long as it is greater than VIH. VSS Ground Ground: GND VCCQ I/O Supply Output Buffer Supply: +3.3V –5% to +10%. For 2.5V I/O: 2.375V to VCC. VSSQ I/O Ground Output Buffer Ground: GND NC - No Connect: These signals are not internally connected. Burst Address Table (MODE = NC/VCC) First Address (external) Second Address (internal) Third Address (internal) A...A00 A...A01 A...A01 A...A00 A...A10 A...A11 A...A11 A...A10 Document #: 38-05153 Rev. *C Burst Address Table (MODE = GND) Fourth Address (internal) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A11 A...A10 A...A01 A...A10 A...A11 A...A00 A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A01 A...A00 A...A11 A...A00 A...A01 A...A10 Page 4 of 12 CY7C1340A Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Address Used CE Deselected Cycle, Power-down None H Deselected Cycle, Power-down None L X L L X X X X L–H High-Z Deselected Cycle, Power-down None L H X L X X X X L–H High-Z Deselected Cycle, Power-down None L X L H L X X X L–H High-Z Deselected Cycle, Power-down None L H X H L X X X L–H High-Z CE2 CE2 ADSP X X X ADSC ADV WRITE OE CLK DQ L X X X L–H High-Z Read Cycle, Begin Burst External L L H L X X X L L–H Q Read Cycle, Begin Burst External L L H L X X X H L–H High-Z Write Cycle, Begin Burst External L L H H L X L X L–H D Read Cycle, Begin Burst External L L H H L X H L L–H Q Read Cycle, Begin Burst External L L H H L X H H L–H High-Z Read Cycle, Continue Burst Next X X X H H L H L L–H Q Read Cycle, Continue Burst Next X X X H H L H H L–H High-Z Read Cycle, Continue Burst Next H X X X H L H L L–H Q Read Cycle, Continue Burst Next H X X X H L H H L–H High-Z Write Cycle, Continue Burst Next X X X H H L L X L–H D Write Cycle, Continue Burst Next H X X X H L L X L–H D Read Cycle, Suspend Burst Current X X X H H H H L L–H Q Read Cycle, Suspend Burst Current X X X H H H H H L–H High-Z Read Cycle, Suspend Burst Current H X X X H H H L L–H Q Read Cycle, Suspend Burst Current H X X X H H H H L–H High-Z Write Cycle, Suspend Burst Current X X X H H H L X L–H D Write Cycle, Suspend Burst Current H X X X H H L X L–H D Partial Truth Table for Read/Write FUNCTION Read GW H BWE H BW1 X BW2 X BW3 X BW4 X Read H L H H H H Write one byte H L L H H H Write all bytes H L L L L L Write all bytes L X X X X X Notes: 2. X means “Don’t Care.” H means logic HIGH. L means logic LOW. Write = L means [BWE + BW1*BW2*BW3*BW4]*GW equals LOW. Write = H means [BWE + BW1*BW2*BW3*BW4]*GW equals HIGH. 3. BW1 enables Write to DQ1–DQ8. BW2 enables Write to DQ9–DQ16. BW3 enables Write to DQ17–DQ24. BW4 enables Write to DQ25–DQ32. 4. All inputs except OE must meet set-up and hold times around the rising edge (LOW–HIGH) of CLK. 5. Suspending burst generates Wait cycle. 6. For a Write operation following a Read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW along with chip being selected always initiates a Read cycle at the L–H edge of CLK. A Write cycle can be performed by setting Write LOW for the CLK L–H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification. Document #: 38-05153 Rev. *C Page 5 of 12 CY7C1340A Maximum Ratings Power Dissipation.......................................................... 1.0W Short Circuit Output Current ........................................ 50 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V VIN ...........................................................–0.5V to VCC+0.5V Range Storage Temperature (plastic) .................... –55°C to +150°C Commercial Junction Temperature ............................................... +150°C Industrial Ambient Temperature[9] VDD[10,11] 0°C to +70°C 3.3V −5%/+10% –40°C to +85°C Electrical Characteristics Over the Operating Range Parameter Description Test Conditions [12, 13] VIHD Input HIGH (Logic 1) Voltage VIH Min. Max. Data Inputs (DQxx) 2.0 VCCQ + 0.3 V All Other Inputs 2.0 4.6 V –0.3 0.8 V –2 2 µA 2 µA VIl Input LOW (Logic 0) Voltage[12, 13] ILI Input Leakage Current[14] ILO Output Leakage Current Output(s) disabled, 0V < VOUT < VCC –2 VOH Output HIGH Voltage[12, 15] IOH = –4.0 mA 2.4 Voltage[12, 15] 0V < VIN < VCC VOL Output LOW VCC Supply Voltage[12] VCCQ I/O Supply Voltage (3.3V I/O)[12] VCCQ I/O Supply Voltage (2.5V I/O)[12] Parameter V IOL = 8.0 mA 0.4 V 3.6 V 3.1 3.6 V 2.375 VCC 3.1 Description Unit Conditions Typ. -5 -7 Unit ICC Power Supply Current: Operating[16, 17, 18] Device selected; all inputs < VILor > VIH; cycle time > tKC min.; VCC = Max.; outputs open 80 225 120 mA ISB2 CMOS Standby[17, 18] Device deselected; VCC = Max.; all inputs < VSS + 0.2 or >VCC – 0.2; all inputs static; CLK frequency = 0 0.2 2 2 mA ISB3 TTL Standby[17, 18] Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max.; CLK frequency = 0 8 18 18 mA ISB4 Clock Running[17, 18] Device deselected; all inputs < VIL or > VIH; VCC = Max.; CLK cycle time > tKC min. 12 30 20 mA Capacitance[19] Parameter Description CI Input Capacitance CO Input/Output Capacitance (DQ) Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Typ. Max. Unit 3 4 pF 6 7 pF Capacitance Derating[20] Parameter ∆ tKQ Description Clock to Output Valid Typ. Max. 0.016 Unit ns/pF Notes: 9. TA is the case temperature. 10. Please refer to waveform (d). 11. Power supply ramp-up should be monotonic. 12. All voltages referenced to VSS (GND). 13. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2. Undershoot: VIL ≤ –2.0V for t ≤ tKC /2. 14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA. 15. AC I/O curves are available upon request. 16. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 17. “Device Deselected” means the device is in power-down mode as defined in the truth table. “Device Selected” means the device is active. 18. Typical values are measured at 3.3V, 25°C, and 8.5-ns cycle time. 19. This parameter is sampled. 20. Capacitance derating applies to capacitance different from the load capacitance shown in AC Test Loads for 3.3V or 2.5V I/O. Document #: 38-05153 Rev. *C Page 6 of 12 CY7C1340A Thermal Resistance Parameter ΘJA Description Test Conditions TQFP Typ. Unit 20 °C/W 1 °C/W Thermal Resistance (Junction to Ambient) Still air, soldered on a 4.25 × 1.125 inch, four-layer PCB Thermal Resistance (Junction to Case) ΘJC AC Test Loads and Waveforms—3.3V I/O[21] 317Ω DQ DQ Z0 = 50Ω 50Ω 351Ω ALL INPUT PULSES 3.0V 0V 5 pF 30 pF 3.3V 10% tP U = 200us 90% 10% 90% Vddtyp Vddm in For proper RESE T bring Vdd down to 0V ≤ 1.5 ns ≤ 1.5 ns = 1.5V Vt (a) (b) (c) (d) AC Test Loads and Waveforms—2.5V I/O DQ ALL INPUT PULSES 2.5V Z0 = 50Ω 50Ω 0V 10% 90% 10% 90% ≤ 1.8 ns ≤ 18 ns Vt = 1.25V (c) (a) Switching Characteristics Over the Operating Range[22] -5 100 MHz Parameter Description Min. -7 66 MHz Max. Min. Max. Unit Clock tKC Clock Cycle Time 10 15 ns tKH Clock HIGH Time 4 5 ns tKL Clock LOW Time 4 5 ns Output Times tKQ Clock to Output Valid tKQX Clock to Output Invalid 2 2 ns tKQLZ Clock to Output in Low-Z[23, 24] 3 3 ns tKQHZ Clock to Output in High-Z[23, 24] 5 6 ns tOEQ OE to Output Valid[25] 5 7 ns 6 ns Low-Z[23, 24] tOELZ OE to Output in tOEHZ OE to Output in High-Z[23, 24] 5 0 7 0 4 ns ns Set-up Times tS Address, Controls, and Data In[26] 2.5 2.5 ns Address, Controls, and Data In[26] 0.5 0.5 ns Hold Times tH Notes: 21. Overshoot: VIH(AC)