CY7C1399-15ZC

CY7C1399 32K x 8 3.3V Static RAM Features • Single 3.3V power supply • Ideal for low-voltage cache memory applications • High speed — 12/15 ns • Low active power — 255 mW (max.) • Low CMOS standby power (L) — 180 µW (max.), f=fMAX • 2.0V data retention (L) — 40 µW • Low-power alpha immune 6T cell • Plastic SOJ and TSOP packaging is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. An active LOW Write Enable signal (WE) controls the writing/ reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399 is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I packages. Functional Description The CY7C1399 is a high-performance 3.3V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory expansion Logic Block Diagram Pin Configurations SOJ Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 INPUT BUFFER I/O0 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE WE OE ROW DECODER I/O2 SENSE AMPS 32K x 8 ARRAY I/O3 I/O4 C1399–2 I/O5 COLUMN DECODER POWER DOWN I/O6 I/O7 A 10 A 11 A 12 A 13 A 14 C1399–1 Selection Guide 7C1399–12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (µA) Maximum CMOS Standby Current (µA) L 12 60 500 50 7C1399–15 15 55 500 50 7C1399–20 20 50 500 50 7C1399–25 25 45 500 50 7C1399–35 35 40 500 50 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 25, 1999 CY7C1399 Pin Configuration TSOP Top View OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 C1399–3 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65 °C to +150°C Ambient Temperature with Power Applied ............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V DC Input Voltage[1].................................–0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ±300 mV 3.3V ±300 mV Electrical Characteristics Over the Operating Range[1] 7C1399–12 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[2] VCC Operating Supply Current GND ≤ VI ≤ VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC L Test Conditions VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 4.0 mA 2.2 –0.3 –1 –5 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +5 –300 60 5 3 500 50 2.2 –0.3 –1 –5 Max. 7C1399–15 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +5 –300 55 5 3 500 50 2.2 –0.3 –1 –5 Max. 7C1399–20 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +5 –300 50 5 3 500 50 µA Max. Unit V V V V µA µA mA mA mA Automatic CE Power-Down Max. VCC, CE ≥ VIH, Current — TTL Inputs VIN ≥ VIH, or VIN ≤ VIL,f = fMAX Automatic CE Power-Down Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ Current — CMOS Inputs[3] VCC – 0.3V, or VIN ≤ 0.3V, L WE ≥VCC – 0.3V or WE ≤0.3V, f=fMAX Notes: 1. Minimum voltage is equal to – 2.0V for pulse durations of less than 20 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3. Device draws low standby current regardless of switching on the addresses. 2 CY7C1399 Electrical Characteristics Over the Operating Range(continued) 7C1399–25 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[2] VCC Operating Supply Current Automatic CE Power-Down Current — TTL Inputs Automatic CE Power-Down Current — CMOS Inputs[3] GND ≤ VI ≤ VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. V CC, CE ≥ VIH, VIN ≥ VIH, or VIN ≤ VIL, f = fMAX Max. VCC, CE ≥ VCC–0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, WE≥VCC–0.3V or WE≤ 0.3V, f=fMAX L Test Conditions VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 4.0 mA 2.2 –0.3 –1 –5 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +5 –300 45 5 3 500 L 50 2.2 –0.3 –1 –5 Max. 7C1399–35 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +5 –300 40 5 3 500 50 Max. Unit V V V V µA µA mA mA mA mA µA µA ISB2 Capacitance[4] Parameter CIN: Addresses CIN: Controls COUT Output Capacitance Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 5 6 6 Unit pF pF pF AC Test Loads and Waveforms R1 317 Ω 3.3V OUTPUT CL INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V R2 351Ω 3.0V 10% GND ≤ 3 ns ALL INPUT PULSES 90% 90% 10% ≤ 3 ns C1399–4 Note: 4. Tested initially and after any design or process changes that may affect these parameters. 3 CY7C1399 Switching Characteristics Over the Operating Range[5] 7C1399–12 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z [6] [6, 7] 7C1399–15 Min. 15 Max. 7C1399–20 Min. 20 Max. 7C1399–25 Min. 25 Max. 7C1399–35 Min. 35 Max. Unit ns 35 3 35 10 0 7 3 8 0 35 35 20 20 0 0 20 12 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 3 ns ns Description Min. 12 Max. 12 3 12 5 0 5 3 6 0 12 12 8 8 0 0 8 7 0 7 3 3 15 10 10 0 0 10 8 0 0 3 0 3 15 3 15 6 0 6 3 7 0 15 20 12 12 0 0 12 10 0 7 3 20 3 20 7 0 6 3 7 0 20 25 15 15 0 0 15 11 0 7 3 25 25 8 7 8 25 OE HIGH to High Z CE HIGH to High Z CE LOW to Low Z[6] [6, 7] CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z [8] [6] WRITE CYCLE[8, 9] 7 WE HIGH to Low Z Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR[4] tR[4] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC – 0.3V, L VIN > VCC – 0.3V or VIN < 0.3V Conditions Min. 2.0 200 20 0 tRC Max. Unit V µA µA ns ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and capacitance CL = 30 pF. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD . 4 CY7C1399 Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE C1399–5 VDR ≥ 2V 3.0V tR Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID C1399–6 Read Cycle No. 2 [11, 12] CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB C1399–7 tRC tHZOE tHZCE DATA VALID HIGH IMPEDANCE DATA OUT Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 5 CY7C1399 Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[8, 13, 14] tWC ADDRESS CE tAW WE tSA tPWE tHA OE tSD DATA I/O NOTE 15 tHZOE DATAIN VALID C1399–8 tHD Write Cycle No. 2 (CE Controlled)[8, 13, 14] tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAIN VALID C1399–9 tSCE tHA tHD Write Cycle No. 3 (WE Controlled, OE LOW)[9, 14] tWC ADDRESS CE tAW WE tSA tHA tSD DATA I/O NOTE 15 tHZWE Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in the output state and input signals shold not be applied. tHD DATA IN VALID tLZWE C1399–10 6 CY7C1399 Truth Table CE H L L L WE X H L H OE X L X H Input/Output High Z Data Out Data In High Z Read Write Deselect, Output Disabled Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 12 Ordering Code CY7C1399–12VC CY7C1399L–12VC CY7C1399–12ZC CY7C1399L–12ZC CY7C1399–12VI CY7C1399–12ZI 15 CY7C1399–15VC CY7C1399L–15VC CY7C1399–15ZC CY7C1399L–15ZC CY7C1399–15VI CY7C1399–15ZI CY7C1399L–15ZI 20 CY7C1399–20VC CY7C1399L–20VC CY7C1399–20ZC CY7C1399L–20ZC CY7C1399–20VI 25 CY7C1399–25VC CY7C1399L–25VC CY7C1399–25ZC CY7C1399L–25ZC 35 CY7C1399–35VC CY7C1399L–35VC CY7C1399–35ZC CY7C1399L–35ZC Package Name V21 V21 Z28 Z28 V21 Z28 V21 V21 Z28 Z28 V21 Z28 Z28 V21 V21 Z28 Z28 V21 V21 V21 Z28 Z28 V21 V21 Z28 Z28 Package Type 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package Commercial Industrial Commercial Commercial Industrial Commercial Industrial Operating Range Commercial Document #: 38–00222–G 7 CY7C1399 Package Diagrams 28-Lead (300-Mil) Molded SOJ V21 51-85031-B 28-Lead Thin Small Outline Package Z28 51-85071-E © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.