CY7C164-15PC

CY7C164 CY7C166 16K x 4 Static RAM Features Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and tri-state drivers. The CY7C166 has an active LOW Output Enable (OE) feature. Both devices have an automatic powerdown feature, reducing the power consumption by 65% when deselected. • High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW (and the Output Enable (OE) is LOW for the CY7C166). Data on the four input/output pins (I/O0 through I/O3) is written into the memory location specified on the address pins (A0 through A13). — 633 mW • Low standby power — 110 mW • TTL-compatible inputs and outputs • Automatic power-down when deselected • CY7C164 is available in non Pb-free 22-pin (300-Mil) Molded DIP, CY7C166 in non Pb-free 24-pin Molded SOJ Reading the device is accomplished by taking Chip Enable (CE) LOW (and OE LOW for CY7C166), while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data I/O pins. The I/O pins stay in a high-impedance state when Chip Enable (CE) is HIGH (or Output Enable (OE) is HIGH for CY7C166). A die coat is used to insure alpha immunity. Logic Block Diagram Pin Configurations DIP Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 CE GND 16K x 4 ARRAY I/O2 I/O1 VCC A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE A5 A6 A7 A8 A9 A10 A11 A12 A13 CE OE GND 1 24 2 23 3 22 4 21 5 20 6 7C166 19 18 7 17 8 9 16 10 15 11 14 12 13 VCC A4 A3 A2 A1 A0 NC I/O3 I/O2 I/O1 I/O0 WE CE WE (OE) (7C166 ONLY) A13 Cypress Semiconductor Corporation Document #: 38-05025 Rev. *A 22 21 20 19 18 17 16 15 14 13 12 I/O0 POWER DOWN COLUMN DECODER A0 A9 A10 A11 A12 I/O3 SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER 1 2 3 4 5 6 7C164 7 8 9 10 11 SOJ Top View • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 CY7C164 CY7C166 Selection Guide CY7C164-15 CY7C166-15 CY7C164-25 CY7C166-25 Maximum Access Time (ns) 15 25 Maximum Operating Current (mA) 115 105 Maximum CMOS Standby Current (mA) 20 20 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied............................................. –55°C to +125°C Latch-Up Current .................................................... >200 mA Supply Voltage to Ground Potential ............... –0.5V to +7.0V Operating Range DC Voltage Applied to Outputs in High Z State[1] ............................................ –0.5V to +7.0V Range Ambient Temperature VCC DC Input Voltage[1] ......................................... –0.5V to +7.0V Commercial 0°C to +70°C 5V ± 10% Electrical Characteristics Over the Operating Range –15 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Voltage[1] Min. –25 Max. Min. 2.4 Max. Unit 2.4 0.4 V 0.4 V 2.2 VCC 2.2 VCC V –0.5 0.8 –0.5 0.8 V VIL Input LOW IIX Input Leakage Current GND < VI < VCC –5 +5 –5 +5 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –5 +5 –5 +5 µA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA 115 105 mA ISB1 Automatic CE Power-Down Current[2] Max. VCC, CE > VIH, Min. Duty Cycle = 100% 40 20 mA ISB2 Automatic CE Power-Down Current[2] Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V 20 20 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF 10 pF Notes: 1. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns. 2. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05025 Rev. *A Page 2 of 9 CY7C164 CY7C166 AC Test Loads and Waveforms R1 481Ω 5V OUTPUT R1 481Ω 5V ALL INPUT PULSES OUTPUT 30 pF R2 255Ω 3.0V 5 pF INCLUDING JIG AND SCOPE (b) INCLUDING JIG AND SCOPE (a) R2 255Ω GND 90% 10% 90% 10% < 5 ns < 5 ns C164–6 C164–5 Equivalent to: THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Switching Characteristics Over the Operating Range[4] CY7C164-15 CY7C166-15 Parameter Description Min. Max. CY7C164-25 CY7C166-25 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Output Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid 7C166 tLZOE OE LOW to Low Z 7C166 tHZOE OE HIGH to High Z 7C166 tLZCE CE LOW to Low 15 Z[5] CE HIGH to High tPU CE LOW to Power-Up tPD WRITE 3 5 10 3 3 25 ns 12 ns ns 10 5 8 0 ns ns 10 0 15 ns ns 3 8 CE HIGH to Power-Down ns 25 15 Z[5, 6] tHZCE 25 15 ns ns 20 ns CYCLE[7] tWC Write Cycle Time 15 20 ns tSCE CE LOW to Write End 12 20 ns tAW Address Set-Up to Write End 12 20 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 12 15 ns tSD Data Set-Up to Write End 10 10 ns tHD Data Hold from Write End 0 0 ns [5] tLZWE WE HIGH to Low Z tHZWE WE LOW to High Z[5, 6] 5 5 7 ns 7 ns Notes: 4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. These parameters are guaranteed by design and not 100% tested. 6. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05025 Rev. *A Page 3 of 9 CY7C164 CY7C166 Switching Waveforms Read Cycle No. 1[8,9] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID C164–7 Read Cycle No. 2[8,10] tRC CE tACE OE 7C166 tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE V CC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB C164–8 Notes: 8. WE is HIGH for read cycle. 9. Device is continuously selected, CE = VIL. (CY7C166: OE = VIL also). 10. Address valid prior to or coincident with CE transition LOW. Document #: 38-05025 Rev. *A Page 4 of 9 CY7C164 CY7C166 Switching Waveforms (continued) Write Cycle No. 1(WE Controlled)[7,11] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD tHD DATAINVALID DATA IN tHZWE tLZWE HIGH IMPEDANCE DATA I/O DATA UNDEFINED C164–9 Write Cycle No. 2(CE Controlled)[7,11,12] tWC ADDRESS tSA tSCE CE tHA tAW tPWE WE tSD DATA IN tHD DATAIN VALID DATA I/O HIGH IMPEDANCE C164–10 Notes: 11. CY7C166 only: Data I/O will be high-impedance if OE = VIH. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05025 Rev. *A Page 5 of 9 CY7C164 CY7C166 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 SB 1.2 I CC 0.8 0.6 0.4 4.5 5.0 0.8 0.6 0.4 V CC = 5.0V V IN = 5.0V 5.5 6.0 I SB 0.0 –55 25 1.6 1.3 NORMALIZED tAA NORMALIZED t AA 1.4 1.2 1.1 TA = 25°C 1.0 1.4 1.2 1.0 VCC =5.0V 0.8 0.9 5.0 5.5 0.6 –55 6.0 TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 2.5 25.0 DELTA tAA (ns) 30.0 2.0 1.5 1.0 25 2.0 3.0 4.0 SUPPLY VOLTAGE (V) Document #: 38-05025 Rev. *A 40 20 0 0.0 1.0 5.0 3.0 4.0 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 VCC = 5.0V TA =25°C 80 60 40 20 0 0.0 125 20.0 15.0 10.0 0.0 2.0 OUTPUT VOLTAGE (V) 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) NORMALIZED I CC vs. CYCLE TIME 1.25 VCC = 4.5V TA = 25°C 5.0 0.5 1.0 V CC = 5.0V TA = 25°C 60 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 3.0 0.0 0.0 80 AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) NORMALIZED I PO 125 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 4.5 100 AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) 0.8 4.0 120 OUTPUT SINK CURRENT (mA) 0.0 4.0 I CC 0.2 I SB 0.2 1.0 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 0 200 400 600 800 1000 CAPACITANCE (pF) NORMALIZED I CC 1.0 NORMALIZED I,CC I NORMALIZED I,CC I SB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics VCC = 5.0V TA = 25°C VIN = 0.5V 1.00 0.75 0.50 10 20 30 40 CYCLE FREQUENCY (MHz) Page 6 of 9 CY7C164 CY7C166 CY7C164 Truth Table CE WE H X High Z Input/Output Deselect/Power-Down Mode Standby (ISB) Power L H Data Out Read Active (ICC) L L Data In Write Active (ICC) CY7C166 Truth Table CE WE OE Input/Output Mode Power H X X High Z Deselect/Power-Down Standby (ISB) L H L Data Out Read Active (ICC) L L H Data In Write Active (ICC) L H H High Z Select/Output Disabled Active (ICC) Address Designators Address Name Address Function CY 7C164 Pin CY7C166 Pin Number Number A5 X3 1 1 A6 X4 2 2 A7 X5 3 3 A8 X6 4 4 A9 X7 5 5 A10 Y5 6 6 A11 Y4 7 7 A12 Y0 8 8 A13 Y1 9 9 A0 Y2 17 19 A1 Y3 18 20 A2 X0 19 21 A3 X1 20 22 A4 X2 21 23 Ordering Information Speed (ns) 15 25 Ordering Code Package Diagram Package Type CY7C164-15PC 51-85012 22-pin (300-Mil) Molded DIP CY7C166-15VC 51-85030 24-pin (300-Mil) Molded SOJ CY7C164-25PC 51-85012 22-pin (300-Mil) Molded DIP CY7C166-25VC 51-85030 24-pin (300-Mil) Molded SOJ Document #: 38-05025 Rev. *A Operating Range Commercial Commercial Page 7 of 9 CY7C164 CY7C166 Package Diagrams 22-pin (300-Mil) PDIP (51-85012) 11 1 DIMENSIONS IN INCHES MIN. MAX. 0.250 0.270 12 22 0.030 0.065 1.070 1.120 SEATING PLANE 0.280 0.325 0.120 0.140 0.140 0.190 0.115 0.160 0.015 0.060 0.055 0.065 0.090 0.110 0.009 0.012 3° MIN. 0.310 0.385 0.015 0.020 51-85012-*A 24-pin (300-mil) SOJ (51-85030) PIN 1 ID 12 1 MIN. DIMENSIONS IN INCHES[MM] MAX. REFERENCE JEDEC MO-088 0.291[7.39] 0.300[7.62] 0.330[8.38] 0.350[8.89] PACKAGE WEIGHT 0.75gms PART # 13 24 0.597[15.16] 0.613[15.57] V24.3 STANDARD PKG. VZ24.3 LEAD FREE PKG. SEATING PLANE 0.120[3.05] 0.140[3.55] 0.007[0.17] 0.013[0.33] 0.004[0.10] 0.050[1.27] TYP. 0.025[0.63] MIN. 0.262[6.65] 0.272[6.91] 0.013[0.33] 0.019[0.48] 51-85030-*B Document #: 38-05025 Rev. *A Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress CY7C164 CY7C166 Document History Page Document Title: CY7C164/CY7C166 16K x 4 Static RAM Document Number: 38-05025 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106811 09/10/01 SZV Change from Spec number: 38-00032 to 38-05025 *A 486744 See ECN NXR Removed 20 ns and 35 ns speed bin from Product offering Removed 24-pin (300-Mil) Molded DIP package Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the ordering information table Document #: 38-05025 Rev. *A Page 9 of 9