CY7C185-25ZC

185 CY7C185 8K x 8 Static RAM Features • High speed — 15 ns • Fast tDOE • Low active power — 715 mW • Low standby power — 220 mW • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature (CE1 or CE2), reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP, SOJ, or SOIC package. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity. Functional Description[1] The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is Logic Block Diagram Pin Configurations DIP/SOJ/SOIC Top View NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A3 A2 A1 OE A0 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O0 INPUT BUFFER I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 CE1 CE2 WE OE A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER 256 x 32 x 8 ARRAY COLUMN DECODER POWER DOWN SENSE AMPS I/O7 A10 A11 Selection Guide[2] Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 7C185-15 15 130 40/15 7C185-20 20 110 20/15 7C185-25 25 100 20/15 7C185-35 35 100 20/15 Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. 2. For military specifications, see the CY7C185A data sheet. Cypress Semiconductor Corporation Document #: 38-05043 Rev. *A • A12 A0 A9 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 13, 2002 CY7C185 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[3] ............................................ –0.5V to +7.0V DC Input Voltage[3]......................................... –0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range 7C185-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] Input Load Current Output Leakage Current Output Short Circuit Current[4] VCC Operating Supply Current Automatic Power-Down Current Automatic Power-Down Current GND ≤ VI ≤ VCC GND ≤ VI ≤ VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL Min. Duty Cycle = 100% Max. VCC, CE1 ≥ VCC – 0.3V, or CE2 ≤ 0.3V VIN ≥ VCC – 0.3V or VIN ≤ 0.3V 40 15 Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.5 –5 –5 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 –300 130 20 15 2.2 –0.5 –5 –5 Max. 7C185-20 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 –300 110 Max. Unit V V V V µA µA mA mA mA mA Notes: 3. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns. 4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Document #: 38-05043 Rev. *A Page 2 of 11 CY7C185 Electrical Characteristics Over the Operating Range (continued) 7C185-25 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] Input Load Current Output Leakage Current Output Short Circuit Current[4] VCC Operating Supply Current Automatic Power-Down Current Automatic Power-Down Current GND ≤ VI ≤ VCC GND ≤ VI ≤ VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL Min. Duty Cycle = 100% Max. VCC, CE1 ≥ VCC – 0.3V or CE2 ≤ 0.3V VIN ≥ VCC – 0.3V or VIN ≤ 0.3V Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.5 –5 –5 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 –300 100 20 15 2.2 –0.5 –5 –5 Max. 7C185-35 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 –300 100 20 15 Max. Unit V V V V µA µA mA mA mA mA Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 7 7 Unit pF pF Note: 5. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R1 481 Ω 5V OUTPUT 5 pF INCLUDING JIGAND SCOPE R1 481 Ω ALL INPUT PULSES 3.0V R2 255Ω GND 10% 90% 90% 10% ≤ 5 ns R2 255Ω ≤ 5 ns (a) (b) Equivalent to: THÉVENIN EQUIVALENT OUTPUT 167Ω 1.73V Document #: 38-05043 Rev. *A Page 3 of 11 CY7C185 Switching Characteristics Over the Operating Range[6] 7C185-15 Parameter Read Cycle tRC tAA tOHA tACE1 tACE2 tDOE tLZOE tHZOE tLZCE1 tLZCE2 tHZCE tPU tPD Write Cycle[9] tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW to Write End CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High Z[7] 3 WE HIGH to Low Z 15 12 12 12 0 0 12 8 0 7 5 20 15 15 15 0 0 15 10 0 7 5 25 20 20 20 0 0 15 10 0 7 5 35 20 20 25 0 0 20 12 0 8 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE1 LOW to Low Z[7] Z[8] Z[7, 8] 0 15 3 3 7 0 20 3 7 5 3 8 0 20 3 15 15 8 3 8 5 3 10 0 20 15 15 5 20 20 9 3 10 5 3 10 20 20 5 25 25 12 3 10 25 25 5 35 35 15 35 35 ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C185-20 Min. Max. 7C185-25 Min. Max. 7C185-35 Min. Max. Unit CE2 HIGH to Low Z CE1 HIGH to High CE2 LOW to High Z CE1 LOW to Power-Up CE2 to HIGH to Power-Up CE1 HIGH to Power-Down CE2 LOW to Power-Down Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device. 9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05043 Rev. *A Page 4 of 11 CY7C185 Switching Waveforms Read Cycle No.1[10,11] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No.2[12,13] CE1 tRC CE2 OE OE tACE DATA OUT tDOE tLZOE HIGH IMPEDANCE tLZCE tHZOE tHZCE DATA VALID tPD ICC HIGH IMPEDANCE VCC SUPPLY CURRENT tPU 50% 50% ISB Write Cycle No. 1 (WE Controlled)[11,13] tWC ADDRESS CE1 tAW CE2 CE WE tSA tSCE2 tPWE tSCEI tHA OE tSD DATA I/O NOTE 14 tHZOE 10. 11. 12. 13. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH. WE is HIGH for read cycle. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 14. During this period, the I/Os are in the output state and input signals should not be applied. tHD DATA IN VALID Document #: 38-05043 Rev. *A Page 5 of 11 CY7C185 Switching Waveforms (continued) rite Cycle No. 2 (CE Controlled)[13,14,15] tWC ADDRESS CE1 tSA CE2 tAW WE tSD DATA I/O DATA IN VALID tHD tSCE2 tHA tSCE1 Write Cycle No. 3 (WE Controlled, OE LOW)[13,14,15,16] tWC ADDRESS CE1 CE2 tSCE1 tSCE2 tAW tSA WE tSD DATA I/O NOTE 14 tHZWE DATA IN VALID tLZWE tHD tHA Notes: 15. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05043 Rev. *A Page 6 of 11 CY7C185 Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 SB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 SB OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 I SB 5.5 6.0 I CC 1.0 0.8 0.6 0.4 0.2 0.0 –55 ISB 25 V CC=5.0V V IN=5.0V NORMALIZED I,CC I NORMALIZED I, I CC I CC 125 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA NORMALIZED t AA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 6.0 TA =25°C 1.6 1.4 1.2 1.0 AMBIENT TEMPERATURE (°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) 4.0 VCC =5.0V TA =25°C VCC =5.0V 0.8 0.6 –55 25 125 AMBIENT TEMPERATURE (°C) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED I PO DELTA tAA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED I CC OUTPUT SINK CURRENT (mA) NORMALIZED I CC vs. CYCLE TIME VCC =5.0V TA =25°C VCC =0.5V 1.00 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC =4.5V TA =25°C 0.75 600 800 1000 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 38-05043 Rev. *A Page 7 of 11 CY7C185 Truth Table CE1 H X L L L CE2 X L H H H WE X X H L H OE X X L X H High Z High Z Data Out Data In High Z Input/Output Mode Deselect/Power-Down Deselect/Power-Down Read Write Deselect Address Designators Address Name A4 A5 A6 A7 A8 A9 A10 A11 A12 A0 A1 A2 A3 Address Function X3 X4 X5 X6 X7 Y1 Y4 Y3 Y0 Y2 X0 X1 X2 Pin Number 2 3 4 5 6 7 8 9 10 21 23 24 25 Ordering Information Speed (ns) 15 Ordering Code CY7C185-15PC CY7C185-15SC CY7C185-15VC CY7C185-15VI 20 CY7C185-20PC CY7C185-20SC CY7C185-20VC CY7C185-20VI 25 CY7C185-25PC CY7C185-25SC CY7C185-25VC CY7C185-25VI 35 CY7C185-35PC CY7C185-35SC CY7C185-35VC CY7C185-35VI Package Name P21 S21 V21 V21 P21 S21 V21 V21 P21 S21 V21 V21 P21 S21 V21 V21 Package Type 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ Industrial Industrial Commercial Industrial Commercial Industrial Commercial Operating Range Commercial Document #: 38-05043 Rev. *A Page 8 of 11 CY7C185 Package Diagrams 28-Lead (300-Mil) Molded DIP P21 51-85014-*B 28-Lead (300-Mil) Molded SOIC S21 51-85026-*A Document #: 38-05043 Rev. *A Page 9 of 11 CY7C185 Package Diagrams (continued) 28-Lead (300-Mil) Molded SOJ V21 51-85031-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05043 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C185 Document History Page Document Title: CY7C185 8K x 8 Static RAM Document Number: 38-05043 REV. ** *A ECN NO. 107145 116470 Issue Date 09/10/01 09/16/02 Orig. of Change SZV CEA Description of Change Change from Spec number: 38-00037 to 38-05043 Add applications foot note to data sheet. Document #: 38-05043 Rev. *A Page 11 of 11