CY7C199B-12ZC

PRELIMINARY CY7C199B 32K x 8 Static RAM Features • High speed — 10 ns • Fast tDOE • CMOS for optimum speed/power • Low active power — 495 mW (max, 10 ns “L” version) • Low standby power — 0.275 mW (max, “L” version) • 2V data retention (“L” version only) • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 81% when deselected. The CY7C199B is in the standard 300-mil-wide DIP, SOJ, and LCC packages. An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. A die coat is used to improve alpha immunity. Functional Description The CY7C199B is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion Logic Block Diagram Pin Configurations DIP / SOJ / SOIC Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 22 23 24 25 26 27 28 1 2 3 4 5 6 7 LCC Top View A7 A6 A5 VCC WE A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 C199B–2 I/O2 GND I/O3 I/O4 I/O5 3 2 1 28 27 4 26 A4 5 25 A3 6 24 A2 7 23 A1 8 22 OE 9 21 A0 10 20 CE 11 19 I/O7 12 18 I/O6 1314151617 C199–3 I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE WE OE I/O1 ROW DECODER I/O2 SENSE AMPS 1024 x 32 x 8 ARRAY 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O3 I/O4 I/O5 OE A1 A2 A3 A4 WE V CC A5 A6 A7 A8 A9 A 10 A 11 21 20 19 18 17 16 15 14 13 12 11 10 9 8 COLUMN DECODER POWER DOWN I/O6 I/O7 TSOP I Top View (not to scale) A 10 A 11 A 12 A 13 A 14 C199B–1 A0 CE I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A 14 A 13 A 12 C199–4 Selection Guide 199B-8 Maximum Access Time (ns) Maximum Operating Current (mA) L Maximum CMOS Standby Current (mA) L 8 120 0.5 199B-10 10 110 90 0.5 0.05 199B-12 12 160 90 10 0.05 199B-15 15 155 90 10 0.05 199B-20 20 150 90 10 0.05 199B-25 25 150 80 10 0.05 199B-35 35 140 70 10 0.05 199B-45 45 140 10 Shaded area contains advance information. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 June 13, 2000 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... –0.5V to +7.0V CY7C199B DC Voltage Applied to Outputs in High Z State[1] ................................... –0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Range Commercial Industrial Military Ambient Temperature[2] 0°C to +70°C –40°C to +85°C – 55°C to +125°C VCC 5V ± 10% 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range[3] 7C199B-8 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC O perating Supply Current GND < VI < VCC GND < VO < V CC, Output Disabled VCC = M ax., IOUT = 0 m A, f = fMAX = 1/tRC Com’l L Mil 5 5 5 0.5 0.05 0.5 0.05 30 5 10 0.05 Test Conditions VCC = Min., IOH=–4.0 mA VCC = Min., IOL=8.0 mA 2.2 –0.5 –5 –5 Min. 2.4 0.4 VCC +0.3V 0.8 +5 +5 120 2.2 –0.5 –5 –5 Max. 7C199B-10 Min. 2.4 0.4 VCC +0.3V 0.8 +5 +5 110 85 2.2 –0.5 –5 –5 Max. 7C199B-12 Min. 2.4 0.4 VCC +0.3V 0.8 +5 +5 160 85 2.2 –0.5 –5 –5 Max. 7C199B-15 Min. 2.4 0.4 VCC +0.3V 0.8 +5 +5 155 100 180 30 5 10 0.05 15 Max. Unit V V V V µA µA mA mA mA mA mA mA mA mA ISB1 Automatic CE Power-Down Current— TTL Inputs Automatic CE Power-Down Current— CMOS Inputs Max. V CC, Com’l CE > VIH, L V IN > VIH or V IN < VIL, f = fMAX Max. V CC, Com’l CE > VCC – 0 .3V L V IN > VCC – 0.3V or V IN < 0.3V, f = 0 Mil ISB2 Shaded area contains advance information. Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. See the last page of this specification for Group A subgroup testing information. 2 PRELIMINARY Electrical Characteristics Over the Operating Range[3] (continued) 7C199B-20 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com ’l L Mil Test Conditions VCC = M in., IOH=– 4.0 mA VCC = M in., IOL=8.0 mA 2.2 –0.5 –5 –5 Min. 2.4 0.4 VCC +0.3V 0.8 +5 +5 150 90 170 30 5 10 0.05 15 2.2 -0.5 –5 –5 Max. 7C199B-25 Min. 2.4 0.4 VCC +0.3V 0.8 +5 +5 150 80 150 30 5 10 0.05 15 2.2 -0.5 –5 –5 Max. 7C199B-35 Min. 2.4 0.4 VCC +0.3V 0.8 +5 +5 140 70 150 25 5 10 0.05 15 Max. CY7C199B 7C199B-45 Min. 2.4 0.4 2.2 -0.5 –5 –5 VCC +0.3V 0.8 +5 +5 140 70 150 25 5 10 0.05 15 Max. Unit V V V V µA µA mA mA mA mA mA mA µA mA ISB1 Automatic CE Power-Down Current— TTL Inputs Automatic CE Power-Down Current— CMOS Inputs Max. VCC, CE > VIH, Com ’l VIN > VIH L or VIN < VIL, f = fMAX Max. V CC, Com ’l CE > VCC – 0.3V L VIN > VCC – 0.3V or VIN < 0.3V, f=0 Mil ISB2 ] Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF Note: 4. Tested initially and after any design or process changes that may affect these parameters. 3 PRELIMINARY AC Test Loads and Waveforms R1 481 Ω 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255 Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255Ω 3.0V 10% GND ≤tr R1 481 Ω CY7C199B ALL INPUT PULSES 90% 90% 10% ≤tr C199B–6 C199B–5 (a) (b) Equivalent to: THÉVENIN EQUIVALENT 167 Ω 1.73V OUTPUT Data Retention Characteristics Over the Operating Range (L version only) Parameter VDR ICCDR tCDR[4] tR Description VCC for Data Retention Data Retention Current VCC = VDR = 2.0V, CE > VCC – 0.3V, Com ’l L VIN > VCC – 0.3V or Chip Deselect to Data Retention Time VIN < 0.3V O peration Recovery Time Com ’l Conditions[5] Min. 2.0 Max. Unit V µA 10 0 200 µA ns µs Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE C199B–7 VDR > 2V 3.0V tR Note: 5. No input may exceed VCC + 0.5V. 4 PRELIMINARY Switching Characteristics Over the Operating Range[3, 6] 7C199B-8 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z [7] [7, 8] CY7C199B 7C199B-10 Min. 10 Max. 7C199B-12 Min. 12 Max. 7C199B-15 Min. 15 Max. Unit ns 15 3 15 7 0 7 3 7 0 15 15 10 10 0 0 9 9 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 3 ns ns Description Min. 8 Max. 8 3 8 4.5 0 5 3 4 0 8 8 7 7 0 0 7 5 0 5 3 3 10 7 7 0 0 7 5 0 0 3 0 3 10 3 10 5 0 5 3 5 0 10 12 9 9 0 0 8 8 0 6 3 12 12 5 5 5 12 OE HIGH to High Z CE LOW to Low Z[7] CE HIGH to High Z[7,8] CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z [8] [7] WRITE CYCLE[9, 10] 7 WE HIGH to Low Z Shaded area contains advance information. Notes: 6. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 5 PRELIMINARY Switching Characteristics Over the Operating Range[3,6] (continued) 7C199B-20 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[7] OE HIGH to High Z[7, 8] CE LOW to Low Z [7] [7, 8] CY7C199B 7C199B-25 Min. 25 Max. 7C199B-35 Min. 35 Max. 7C199B-45 Min. 45 Max. Unit ns 45 3 ns ns 45 16 0 15 3 15 0 25 45 22 40 0 0 22 15 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 3 ns ns Description Min. 20 Max. 20 3 20 9 0 9 3 9 0 20 20 15 15 0 0 15 10 0 10 3 3 25 18 20 0 0 18 10 0 0 3 0 3 25 3 25 10 0 11 3 11 0 20 35 22 30 0 0 22 15 0 11 3 35 35 16 15 15 20 CE HIGH to High Z CE LOW to Power-Up CE HIGH to Power-Down [9,10] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z [8] 15 WE HIGH to Low Z[7] Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID C199B–8 Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 6 PRELIMINARY Switching Waveforms (continued) Read Cycle No. 2 [12, 13] CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD tHZOE tHZCE DATA VALID tRC CY7C199B HIGH IMPEDANCE DATA OUT ICC 50% ISB C199B–9 Write Cycle No. 1 (WE Controlled)[9, 14, 15] tWC ADDRESS CE tAW WE tSA tPWE tHA OE tSD DATA I/O tHZOE DATA IN VALID C199B–10 tHD Write Cycle No. 2 (CE Controlled)[9, 14, 15] tWC ADDRESS CE tSA tAW tHA tSCE WE tSD DATA I/O DATA IN VALID C199B–11 tHD Notes: 13. Address valid prior to or coincident with CE transition LOW. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 7 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled OE LOW)[10, 15] tWC ADDRESS CY7C199B CE tAW WE tSA tHA tSD DATA I/O tHZWE DATA IN VALID tHD tLZWE C199B–12 Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC,I SB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN =5.0V TA =25°C ICC NORMALIZED ICC,I SB 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 –55 ISB 25 125 AMBIENT TEMPERATURE ( °C) VCC =5.0V VIN =5.0V NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C SUPPLY VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT (mA) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA NORMALIZED t AA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA =25°C 1.6 1.4 1.2 1.0 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C VCC =5.0V 0.8 0.6 –55 25 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE ( °C) OUTPUT VOLTAGE (V) 8 PRELIMINARY Typical DC and AC Characteristics (continued) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED I PO DELTA t AA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 NORMALIZED I CC 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 0.50 10 20 VCC =4.5V TA =25°C TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 VCC =5.0V TA =25°C VIN =0.5V CY7C199B NORMALIZED I CC vs. CYCLE TIME 1.00 0.75 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Truth Table CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect, Output Disabled Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 8 Ordering Code CY7C199B-8VC CY7C199B-8ZC CY7C199BL-8VC CY7C199BL-8ZC CY7C199B-10VC CY7C199B-10ZC CY7C199BL-10VC CY7C199BL-10ZC CY7C199B-10VI CY7C199B-10ZI CY7C199BL-10VI CY7C199BL-10ZI CY7C199B-12PC CY7C199B-12VC CY7C199B-12ZC CY7C199BL-12PC CY7C199BL-12VC CY7C199BL-12ZC CY7C199B-12VI CY7C199B-12ZI CY7C199BL-12VI CY7C199BL-12ZI Package Name V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 P21 V21 Z28 P21 V21 Z28 V21 Z28 V21 Z28 Package Type 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package Operating Range Commercial 10 Commercial Industrial 12 Commercial Industrial Shaded area contains advance information. Contact your Cypress sales representative for availability 9 PRELIMINARY Ordering Information (continued) Speed (ns) 15 Ordering Code CY7C199B-15PC CY7C199B-15VC CY7C199B-15ZC CY7C199BL-15PC CY7C199BL-15VC CY7C199BL-15ZC CY7C199B-15VI CY7C199B-15ZI CY7C199B-15DMB CY7C199B-15LMB CY7C199BL-15DMB CY7C199BL-15LMB CY7C199B-20PC CY7C199B-20VC CY7C199B-20ZC CY7C199BL-20PC CY7C199BL-20VC CY7C199BL-20ZC CY7C199B-20VI CY7C199B-20ZI CY7C199B-20DMB CY7C199B-20LMB CY7C199BL-20DMB CY7C199BL-20LMB CY7C199B-25PC CY7C199B-25SC CY7C199B-25VC CY7C199B-25ZC CY7C199BL-25ZI CY7C199B-25DMB CY7C199B-25LMB CY7C199B-35PC CY7C199B-35SC CY7C199B-35VC CY7C199B-35ZC CY7C199B-35DMB CY7C199B-35LMB CY7C199B-45DMB CY7C199B-45LMB Package Name P21 V21 Z28 P21 V21 Z28 V21 Z28 D22 L54 D22 L54 P21 V21 Z28 P21 V21 Z28 V21 Z28 D22 L54 D22 L54 P21 S21 V21 Z28 Z28 D22 L54 P21 S21 V21 Z28 D22 L54 D22 L54 Package Type 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier CY7C199B Operating Range Commercial Industrial Military 20 Commercial Industrial Military 25 Commercial Industrial Military Commercial 35 Military Military 45 Shaded area contains advance information. Contact your Cypress sales representative for availability 10 PRELIMINARY MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL Max. IIX IOZ ICC ISB1 ISB2 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 CY7C199B Switching Characteristics Parameter READ CYCLE tRC tAA tOHA tACE tDOE WRITE CYCLE tWC tAA tAW tHA tSA tPWE tSD tHD Document #: 38-00941-** Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 11 PRELIMINARY Package Diagrams 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D-15 Config. A CY7C199B 51-80032 12 PRELIMINARY Package Diagrams (continued) 28-Pin Rectangular Leadless Chip Carrier L54 MIL-STD-1835 C-11A CY7C199B 51-80067 28-Lead (300-Mil) Molded DIP P21 51-85014-B 13 PRELIMINARY Package Diagrams (continued) 28-Lead (300-Mil) Molded SOIC S21 CY7C199B 51-85026-A 28-Lead (300-Mil) Molded SOJ V21 51-85031-B 14 PRELIMINARY Package Diagrams (continued) 28-Lead Thin Small Outline Package Z28 CY7C199B 51-85071-F © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.