DS26521DK

DS26521DK Single T1/E1/J1 Transceiver Design Kit www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26521DK is an easy-to-use evaluation kit for the DS26521 T1/E1/J1 single-chip transceiver (SCT). The DS26521DK is intended to be used as a standalone system. The board comes complete with a transceiver, transformer, termination resistors, configuration switches, network connectors, microprocessor, and RS-232 connector. The onboard processor and Dallas’ ChipView software give point-and-click access to configuration and status registers from a Windows-based PC. On-board LEDs indicate receive loss-of-signal and interrupt status, as well as multiple clock and signal routing configurations. Demonstrates Key Functions of DS26521 T1/E1/J1 SCT Includes Transceiver, Transformers, and Termination Passives BNC Connections for 75Ω E1 RJ48 Connector for 120Ω E1 and 100Ω T1 On-Board Processor and ChipView Software Provide Point-and-Click Access to the DS26521 Register Set Accessible Address/Data Bus with Tri-State Control to Allow Interface for External Processor Windows is a registered trademark of Microsoft Corp. All Equipment-Side Framer Pins are Easily Accessible for External Data Source/Sink DESIGN KIT CONTENTS LEDs for Loss-of-Signal and Interrupt Status DS26521DK PC Board CD_ROM Including: ChipView Software DS26521 Definition Files DS26521 Initialization Files DS26521DK Data Sheet DS26521 Data Sheet DS26521 Errata Sheet (if applicable) Easy-to-Read Silkscreen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs ORDERING INFORMATION PART DS26521DK 1 of 18 DESCRIPTION Design Kit for DS26521 REV: 021406 DS26521DK COMPONENT LIST DESIGNATION C01, CB07, CB08, CB10, CB12, CB16, CB18, CB19, CB21, CB23, CB26, CB32, CB39–CB41 QTY DESCRIPTION 15 0.1µF ±10%, 16V ceramic capacitors (0603) Phycomp 06032R104K7B20D C02 1 1µF ±10%, 16V ceramic capacitor (1206) Panasonic ECJ-3YB1C105K 12 10µF ±20%, 10V ceramic capacitors (1206) Panasonic ECJ-3YB1A106M 8 4.7µF, 6.3V multilayer ceramic capacitors (0603) Digi-Key ECJ-1VB0J475M CB09 1 560pF ±5%, 50V ceramic capacitor (1206) CB15, CB22, CB27, CB33, CB35 5 CB30 1 DB01 1 1A 40V Schottky diode DS01, DS02, DS05 3 Red LEDs, SMD DS04 1 Green LED, SMD GND_TP01– GND_TP06 6 Standard ground clips H1–H5, H10 6 Kit, 4-40 hardware, 0.50 nylon standoff and nylon hex-nut J01–J03, J06 4 10-pin, dual-row, vertical terminal strips J04, J08 2 5-pin right-angle BNC connectors J05 1 DB9 right-angle connector (long case) J07, J10 2 J09 J11 1 1 Nonpopulated 14-pin, dual-row, vertical headers 100-mil, 2 x 7-position jumper 100-mil, 2-position jumper JB01 1 Red banana plug socket, horizontal JB02 1 8-pin single-port RJ48 connector JB03 1 Black banana plug socket, horizontal JP01–JP09, JP10 10 100-mil, 3-position jumpers R01–R04, RB47 5 0Ω ±5%, 1/8W resistors (1206) R05, RB35–RB40, RB45, RB46 9 1.0kΩ ±5%, 1/16W resistors (0603) CB01, CB02, CB05, CB06, CB11, CB14, CB20, CB28, CB31, CB34, CB36, CB37 CB03, CB04, CB13, CB17, CB24, CB25, CB29, CB38 0.1µF ±20%, 16V X7R ceramic capacitors (0603) 470µF ±20%, 6.3V tantalum capacitor (D case) 2 of 18 SUPPLIER/PART Digi-Key 478-1489-2-ND Arrow 0603YC104MAT2 Digi-Key 399-3002-1-ND International Rectifier 10BQ040 Panasonic LN1251C Panasonic LN1351C Keystone 4954 Lab Stock 4-40KIT4 Samtec TSW-105-07-T-D Trompetor UCBJR220 AMP 747459-1 Samtec NOPOP-HDR-TSW-107-14-T-D Lab Stock Lab Stock Mouser Electronics 164-6219 Molex 15-43-8588 Mouser Electronics 164-6218 Lab Stock Panasonic ERJ-8GEYJ0R00V Panasonic ERJ-3GEYJ102V DS26521DK DESIGNATION R06, R07, RB06, RB07, RB44, RB54, RB55 RB01–RB05, RB11, RB23–RB26, RB28, RB29 RB08, RB09, RB10, RB14–RB22, RB27, RB32, RB33, RB43, RB48 QTY DESCRIPTION SUPPLIER/PART 7 10kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V 12 30Ω ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ300V 17 10kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V RB12, RB13, RB50 3 330Ω ±5%, 1/16W resistors (0603) RB30, RB31 2 61.9Ω ±1%, 1/10W resistors (0805) RB34 1 1.0MΩ ±5%, 1/16W resistor (0603) RB41 1 51.1Ω ±1%, 1/10W resistor (0805) RB42 1 10kΩ ±1%, 1/10W resistor (0805) RB51 1 0Ω ±5%, 1/16W resistor (0603) RB52 1 330Ω ±5%, 1/16W resistor (0603) RB53 1 1.0kΩ ±5%, 1/16W resistor (0603) SW01 1 4-pin single-pole switch TB01 1 16-pin SMT transformer TP01, TP02 2 Testpoints, one plated hole DO NOT STUFF Lab Stock U01, U02 2 Cypress SRAM Lab Stock U03 1 Single T1/E1/J1 transceiver, 64-pin, 10mm x 10mm LQFP U04 1 MMC2107 processor U05 1 1.2V FPGA 144-pin, 20mm x 20mm TQFP U06 1 3V to 5V regulating charge pump UB01 1 UB02 1 UB04 1 UB05 1 YB01 1 Dallas Semiconductor DS26521 Motorola MMC2107 Lattice LFEC3E-3T144C Maxim MAX1686HEUA MAXIM NA Maxim MAX811SEUS-T Atmel AT25F2048N-10SU-2.7 Maxim MAX1963EZT120-T SaRonix NTH039A3-1.5440 Dual RS-232 transceivers with 3.3V/5V internal capacitors Microprocessor voltage monitor, 2.93V reset, 4-pin SOT143 SPI serial EEPROM, 2M, 2.7V to 3.6V, 8-pin SO LDO regulator with reset, 1.20V output, 300mA, 6-pin SOT23 Oscillator, crystal clock 3.3V, 1.544MHz 3 of 18 Panasonic ERJ-3GEYJ331V Panasonic ERJ-6ENF61R9V Panasonic ERJ-3GEYJ105V Panasonic ERJ-6ENF51R1V Panasonic ERJ-6ENF1002V Panasonic ERJ-3GEY0R00V Panasonic ERJ-3GEYJ331V Panasonic ERJ-3GEYJ102V Panasonic EVQPAE04M Pulse Engineering TX1099 DS26521DK DESIGNATION QTY YB02 1 XB01 1 DESCRIPTION Oscillator, crystal clock 3.3V, 2.048MHz SUPPLIER/PART SaRonix NTH039A3-2.0480 PEI Sales Inc. EC1-8.000M 8.0MHz low-profile crystal BOARD FLOORPLAN RS-232 DB9 CONNECTOR FPGA CONFIG PROM TESTPOINTS: DS26521 ADDRESS[12..0] DATA[7..0] INT, CS, RW, RD INT LED DS26521 JTAG LATTICE EC3 FPGA TESTPOINTS: RCHBLK_CLK, RLF_LTC, AL_RSIGF, RM_RFSYNC, TCHBLK_CLK MMC2107 PROCESSOR FPGA JTAG PROCESSOR SRAM TESTPOINTS: SPI_CPOL, SPI_CPHA, SPI_SWAP, SPI_SEL, BTS, TXENABLE TESTPOINTS: BPCLK, MCLK, RSYSCLK, TSYSCLK, TCLK, RCLK OSCILLATOR SELECTION 1.544MHz, 2.048MHz PC BOARD ERRATA DS26521DK01A0 10/10/2005: There is no errata for the DS26521DK01A0 design. DS26521DK02A0 11/22/2005: There is no errata for the DS26521DK02A0 design. 4 of 18 DS26521 BNC Rx RJ48 5V PROCESSOR FLASH SUPPLY 1.2V FPGA SUPPLY TRANSFORMER BOARD POWER 3.3V BANANA PLUGS BNC Tx TESTPOINTS: TSER, RSER, TSSYNCIO, TSYNC, RSYNC, REFCLKIO, MCLK, RSIG, TSIG, RLOS LED RLF LED DS26521DK BASIC OPERATION This design kit relies upon several supporting files, which are available for downloading on our website at www.maxim-ic.com/DS26521DK QuickView page. Hardware Configuration • • • Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. Install the following jumpers (detailed in Table 2): • JP01—Connect MCLK to 2.048MHz (for both T1 and E1). • Connect JP02 MCLK to RSYSCLK, JP03 MCLK to TSYSCLK, JP04 TCLK to RCLK. • JP08 SPI_SEL to GND, JP09 BTS to VCC, TXENABLE to VCC. From the Programs menu, launch the host application named ChipView.exe. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs → ChipView → ChipView. General: • Upon power-up, the RLF and AL_LOS LEDs (red) will be lit, and the INT LED (red) will not be lit. The board will draw approximately 200mA at power-up. Quick Setup (Register View) • • • • The PC will load ChipView, offering a choice among DEMO MODE, REGISTER VIEW, and TERMINAL MODE. Select REGISTER VIEW. The program will request a definition file. Navigate to the .def files in the T1 or E1 folder, then select the file named DS26521_GLOBAL_T1.def (T1 mode) or DS26521_GLOBAL_E1.def (E1 mode). Note: Through the “links” section this will also load the LIU def file and framer def file. The Register View Screen will appear, showing the register names, acronyms, and values for the DS26521. Predefined register settings for several functions are available as initialization files. • .ini files are loaded by selecting the menu File→Reg Ini File→Load Ini File. • Load the .ini file Load_T1_LBO0_0_133_impMatchOn.ini (T1 mode) or Load_E1_75_impMatchOn.ini (E1 mode). • After loading the .ini file, the following may be observed: • The DS26521 begins transmitting AIS with impedance match. • The AL_LOS LEDs extinguishes upon external loopback. Miscellaneous: • The DS26521 uses three register definition files. All three files are loaded when the DS26521_GLOBAL*.def file is loaded. Individual files are selected from the Def File Selection menu in ChipView. ADDRESS MAP The on-board microcontroller is configured to start the user address space at 0x81000000. All offsets given below are relative to the beginning of the user address space. Table 1. Address Map OFFSET 0X0000 to 0X0087 0X1000 to 0X2FFF DEVICE DESCRIPTION FPGA Board Identification and FPGA Test Registers DS26521 DS26521 Framer, LIU, and BERT Registers 5 of 18 DS26521DK TESTPOINTS AND CONNECTORS The DS26521DK has several connectors, testpoints, oscillators, and jumpers. Table 2 provides a description of these signals, given in order of appearance on the PC board, from left to right then top to bottom (with the board held so that the RS-232 connector is on the top edge). Table 2. Main Board PC Board Configuration SILKSCREEN REFERENCE VCC 3.3V (banana plug) GND (banana plug) FUNCTION DEFAULT SETTING SCHEMATIC PAGE 3.3V 2 GND 2 DESCRIPTION J05 RS232 Connector Connected to Host PC 8 J09 OnCE BDM Connector — 8 SW01 System Reset — 6 Not Installed 8 — 11 System VDD. Always connected to power supply. System Ground. Always connected to power supply. Used for Communication with Host PC. Basic setting is 57.6k baud, 8 bits, no stop bit, 1 parity bit (57.6, 8, N, 1). OnCE Debug Connector for MMC2107 Processor System Reset. Connects to all device reset pins. Provides Flash Programming Voltage (5V) to Processor JTAG Connector for Lattice EC3 FPGA — 11 FPGA Init and Done Pins DS26521 Testpoints — 5 J06 YB01, YB02 (Bottom side of PC Board) DS26521 JTAG —- 3 Testpoints for DS26521 Pins: RCHBLK_CLK, RLF_LTC, AL_RSIGF, RM_RFSYNC, TCHBLK_CLK JTAG Connector for DS26521 Oscillators — 5 Oscillators for 2.048MHz and 1.544MHz J07, J10 Testpoints — 10 J10.12 + J10.14 Bus Tri-State 10 JP01 MCLK Selection Not Jumpered Jumpered pins 2+3 Jumpered Pins 1+2 Jumpered Pins 1+2 Jumpered Pins 1.2 Testpoints for DS26521 Address/Data Bus and Control Lines — 5 MCLK Selection: 1.544MHz, 2.048MHz (default) 5 RSYSCLK Selection: MCLK (default), BPCLK 5 TSYSCLK Selection: MCLK (default), BPCLK 5 TCLK Selection: RCLK (default), MCLK J11 J01 TP01, TP02 J03 JP02 JP03 Power supply VDD Power supply Ground Flash VPP Jumper FPGA, JTAG FPGA, Testpoint RSYSCLK Selection TSYSCLK Selection JP04 TCLK Selection J02 DS26521 Testpoints — 5 JP05 SPI_CPOL bias Not Jumpered 3 Testpoints for DS26521 Pins: TSER, RSER, TSSYNCIO, TSYNC, RSYNC, REFCLKIO, MCLK, RSIG, TSIG SPI_CPOL Selection: Pulldown, Pullup JP06 SPI_CPHA bias Not Jumpered 3 SPI_CPHA Selection: Pulldown, Pullup JP07 SPI_SWAP bias Not Jumpered 3 SPI_SWAP Selection: Pulldown, Pullup JP08 SPI_SEL bias 3 SPI_SEL Selection: Pulldown (default), Pullup JP09 BTS bias 3 BTS Selection: Pulldown, Pullup (default) JP10 TXENABLE bias J04, J08 JB02 Network BNC Network RJ48 Jumpered Pins 1+2 Jumpered Pins 2+3 Jumpered Pins 2+3 — — 3 4 4 6 of 18 TXENABLE Selection: Pulldown, Pullup (default) BNC for 75Ω Network Connection RJ48 Network Connection DS26521DK DS26521 INFORMATION For more information about the DS26521, consult the DS26521 data sheet available on our website at www.maxim-ic.com/DS26521. Software downloads are also available for this design kit. DS26521DK INFORMATION For more information about the DS26521DK, including software downloads, consult the DS26521DK data sheet available on our website at www.maxim-ic.com/DS26521DK. TECHNICAL SUPPORT For additional technical support, please e-mail your questions to telecom.support@dalsemi.com. SCHEMATICS The DS26521DK schematics are featured in the following pages. 7 of 18 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products • Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. CR-1 : @\_ZTOP_LIB\.\_DS26521TOPDN_\(SCH_1):PAGE1 7 8 6 5 3 4 1 2 D D DS26521DK HIERARCHY BLOCK MICROPROCESSOR HIERARCHY BLOCK PAGES 06-11 C PAGES 03-05 INT521 INT521 CS_X1 CS_X1 CS_X5 RD_DUT RD_DUT RD_DUT WR_DUT WR_DUT WR_DUT SPI_MOSI INT2 SPI_CS INT3 SPI_SCK INT4 SPI_MISO INT5 CS_X1 C CS_X2 CS_X3 CS_X4 D_DUT A_DUT_ RESET B D_DUT D_DUT A_DUT A_DUT RESET521 RESET521 _motprocrescard_dn _ds26521dk01a0dutdn_ B CONTENTS PAGE 01: PAGE 02: A DS26521 DESIGN KIT AND ENGINEERING EVALUATION TOP LEVEL HIERARCHY BLOCKS DECOUPLING / MOUNTING HOLES A DS26521 DESIGN KIT PAGES 03-05: PAGES 06-11: DS26521 DEVICE, LINE BUILDOUT AND TESTPOINTS MICROPROCESSORAND INTERFACE TITLE: DS26521DK02A0 NOTES: EACH HIERARCHY BLOCK IS INDEPENDENT OF THE NEXT. ONLY SIGNALS WITH IMPORT/OUTPORT CONNECTORS HAVE CONNECTION OUTSIDE THE HIERARCHY BLOCK. THESE SIGNALS APPEAR AS PINS ON THE HIERARCHY BLOCK CONNECTOR DATE: DS26521DK TOP LEVEL ENGINEER: STEVE SCULLY 8 7 6 BLOCK NAME: _ds26521topdn_. 5 PARENT BLOCK: 4 3 2 10/26/2005 PAGE: 1/2(BLOCK) 1/11(TOTAL) 1 CR-2 : @\_ZTOP_LIB\.\_DS26521TOPDN_\(SCH_1):PAGE2 7 8 6 5 3 4 1 2 D D JB01 V3_3 RED C CONN_BANANA_2P JB03 CB02 10UF CB11 10UF CB14 10UF CB05 10UF B CB06 10UF CB20 10UF 1 2 CB30 2 DB01 1 C 470UF A CB31 10UF CB01 10UF V3_3 A B BLACK H1 CONN_BANANA_2P H3 41 H5 41 41 .50STANDOFF_NUT H2 CB38 4.7UF CB24 4.7UF CB25 4.7UF CB29 4.7UF CB13 4.7UF CB03 4.7UF CB04 4.7UF CB17 4.7UF V3_3 H4 41 H10 41 41 B B GND_TP04 GND_TP06 GND_TP03 GND_TP02 1 1 1 0.1UF CB40 2 0.1UF C01 2 0.1UF CB32 2 0.1UF 1 CB41 2 0.1UF 0.1UF 1 CB07 2 1 CB08 2 1 1 1 1 0.1UF CB10 2 0.1UF CB26 2 0.1UF CB21 2 0.1UF CB19 2 0.1UF CB23 2 0.1UF 1 1 1 CB12 2 GND_TP01 GND_TP05 0.1UF CB16 2 0.1UF 1 CB18 2 V3_3 A A TITLE: DS26521DK02A0 DATE: ENGINEER: PAGE: 2/2(BLOCK) 2/11(TOTAL) 1 10/26/2005 STEVE SCULLY 8 7 6 BLOCK NAME: _ds26521topdn_. 5 PARENT BLOCK: 4 3 2 CR-3 : @\_ZTOP_LIB\.\_DS26521TOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_DS26521DK01A0DUTDN_\(SCH_1):PAGE1 5B5 DVDD 11 4B7< V3_3 TXENABLE RSER 57 RSER521 5B7< 64 TSER RCLK 56 RCLK521 5B3< RSYSCLK 55 RSYSCLK521 RSYNC 54 RSYNC521 RM/RFSYNC 53 RM_RFSYNC521 5B4 RSIG 52 RSIG521 AL/RSIGF/FLOS 51 AL_RSIGF_FLOS521 3A5 RLF/LTC 50 RLF_LTC521 RCHBLK/CLK 49 RCHBLK_CLK521 BPCLK 48 BPCLK521 D/SPI_MISO 33 0 1 60 TSSYNCIO 59 TSIG U03 DS26521_U TCHBLK/CLK 1 24 A 2 23 A 3 20 A D/SPI_MOSI 32 4 19 A D/SPI_CLK 31 2 5 18 A D 30 3 6 17 A D 29 4 7 16 A D/SPI_SWAP 28 5 8 15 A D/SPI_CPHA 27 6 12 14 A D/SPI_CPOL 26 7 4 5 5 TDI 6 7 7 TDO 8 GND VCC 10 3D6< 3A6< 1B4^ 3C3 ACVSS ARVSS ATVSS DVSS 3C4> 2 RB36 SPISEL521 (LOW FOR PARALLEL PORT) 1.0K 3A6< 5C4 RB39 1.0K 3D6< IO 8 12 41 22 SCAN_ENABLE SCAN_MODE JTDO JTDI V3_3 D7_SPI_CPOL 7 2 B DS02 AL_RSIGF_FLOS521 BTS521 (HIGH FOR MOTO MODE) RB37 1.0K 2 SCANMO521 RB46 1.0K SCANEN521 RB45 1.0K A RB13 330 3 TCK 2 5C4 5A3< 3A2< 3 SCANMO521 3 SCANEN521 4 2 3A2< TMS JTDI JTDO 1 3 RB40 1.0K 5C4 3B4> 3C8< DS01 RLF_LTC521 TXENABLE521 (HIGH FOR NORMAL OPERATION) RB12 330 RB38 1.0K 2 JP10 1 9 JTCLK 47 46 45 44 43 J06 D6_SPI_CPHA JP09 JTRST I30 5C4 6 2 JP08 JTRST A 3A5 5C4 RB35 1.0K 3 25 5B5< D5_SPI_SWAP JP05 0 1B4^ 3A4 5 1 TSYNC 5B7 1 61 I22 NA 3 TSYSCLK C 1 62 5A2 1 TCLK JP06 63 3 13 58 A 4B7< 3 RRING RTIP RRING 1 10 3 RTIP 1 ARVDD ATVDD REFCLKIO RESET* 5 9 40 21 1B4^ 5D5< RESET521 IN MCLK521 D 39 38 42 MCLK BTS INT* WR/RW* V3_3 JP07 1B4^ IN TRING 1 2 D_DUT A_DUT B 7 JTMS C TTIP 3 4 D_DUT TXENABLE521 5B5 TSER521 5B2 TCLK521 5A2 TSYSCLK521 5B5< TSYNC521 5B5< TSSYNCIO521 5B7 TSIG521 5B4 TCHBLK_CLK521 3A2< 6 JTMS JTCLK 4B7< TTIP TRING SPI_SEL CS* 4C7< RD/DS* CS_X1 IN 34 RD_DUT IN 35 WR_DUT IN 36 SPISEL521 1 3B2< INT521 37 BTS521 3B2< 2 IN D REFCLKIO521 5 1C4^ 1B4^ 1B4^ 1C4^ 6 ACVDD 7 8 BEGINNING OF DS26521DK HIERARCHY BLOCK CONN_10P TITLE: DS26521DK02A0 DATE: ENGINEER: PAGE: 1/3(BLOCK) 3/11(TOTAL) 1 10/26/2005 INT_LED AND TESTPOINTS FOR ADDR/DATA/CTRL ARE IN THE MICRO PROCESSOR BLOCK 8 7 6 BLOCK NAME: _ds26521dk01a0dutdn_. 5 4 PARENT BLOCK: \_ds26521topdn_\ STEVE SCULLY 3 2 CR-4 : @\_ZTOP_LIB\.\_DS26521TOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_DS26521DK01A0DUTDN_\(SCH_1):PAGE2 7 8 6 5 3 4 1 2 D D CONN_BNC_5PIN J04 2 1 C C R01 0.0 CB09 560PF TTIP 3C7> TB01 3C7> 9 8 7 6 5 1:0.8 10 R02 0.0 TRING 11 JB02 8 1:1 H 6 3C4< RTIP R03 0.0 15 RRING 1:0.8 A 1 B CONN_RJ48 1 2 2 14 3 RB31 61.9 61.9 RB30 1 R04 0.0 C TB01 3C4< 5 B 1:1 1 2 3 4 E D 2 16 7 F 4 B G CONN_BNC_5PIN J08 A 1 RB41 51.1 2 2 A 2 CB15 .1UF 1 1 TITLE: DS26521DK02A0 DATE: ENGINEER: PAGE: 2/3(BLOCK) 4/11(TOTAL) 1 10/26/2005 STEVE SCULLY 8 7 6 BLOCK NAME: _ds26521dk01a0dutdn_. 5 4 PARENT BLOCK: \_ds26521topdn_\ 3 2 CR-5 : @\_ZTOP_LIB\.\_DS26521TOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_DS26521DK01A0DUTDN_\(SCH_1):PAGE3 7 8 6 5 3 4 1 2 2.048MHZ_3.3V YB02 V3_3 D 4 1 VCC GND OUT 8 I58 JMP_3 5 3 OSC 1 MCLK521PREBUF RB04 2 JP01 MCLK521 D 3D6< 1 30 1.544MHZ_3.3V V3_3 OSC 8 VCC YB01 1 4 1 GND OUT 5 C C J03 3B4> RCHBLK_CLK521 2 2 1 1 4 4 3 3 3B4> 3A5 RLF_LTC521 3C4> 3A5 AL_RSIGF_FLOS521 6 6 5 5 RM_RFSYNC521 8 8 7 7 10 9 9 3C4> 3B8> TCHBLK_CLK521 10 J02 CONN_10P 5A3< 5D6 MCLK521PREBUFRB05 TSIG521 3C8< 30 2 1 1 4 4 3 3 6 6 5 5 8 8 7 7 10 9 9 10 RB26 30 RB24 30 TSER521 3C8< TSSYNCIO521 3C8 TSYNC521 REFCLKIO521 RB25 30 B 3C8 3D5 5B7< 5A3< 5D6 MCLK521PREBUF RB03JMP_3 I56 3 5B3< 2 30 RSIG521 3C4> RCLK521 3C4> CONN_10P 5A3< 3B4> RB11 30 BPCLK521 RB28JMP_3 30 2 5B3< 5A3< MCLK521PREBUFRB01 5D6 3C8< TSYSCLK521 3C8< 1 JP03 5B7< TCLK521 2 JP04 1 B RSYNC521 RB23 30 3 3C4> 3C4 RSER521 30 A 5A3< 3B4> BPCLK521 RB29JMP_3 3 A 30 2 5B7< 5B3< 5A3< 5D6 MCLK521PREBUFRB02 RSYSCLK521 3C4< 1 JP02 30 END OF DS26521DK HIERARCHY BLOCK TITLE: DS26521DK02A0 DATE: ENGINEER: PAGE: 3/3(BLOCK) 5/11(TOTAL) 1 10/26/2005 STEVE SCULLY 8 7 6 BLOCK NAME: _ds26521dk01a0dutdn_. 5 4 PARENT BLOCK: \_ds26521topdn_\ 3 2 CR-6 : @\_ZTOP_LIB\.\_DS26521TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE1 6 5 4 3 2 1 54 ICOC21 55 ICOC20 TDI PQA0 PQA1 PQA3 PQA4 PQB0 PQB1 PQB2 PQB3 EB0* EB1* EB2* 0.0 CB22 .1UF RB47 8B1 FLASH_VPP VRH TA TEA RW 9D5 OE 7B4 RCON 7D6< 59 OE* 95 SHS* 97 TA* 99 TEA* 102 VSTBY 92 VRH 113 VRL 112 VPP 87 VDDA 115 VDDF 74 VDDH 103 VDDSYN 123 VDD8 141 VDD7 129 VDD6 77 VDD5 65 VDD4 45 VDD3 33 VDD2 19 VDD1 9 RW TDO TC1 78 CS3* 81 CS2* 83 CS1* 85 CS0* 86 116 22 D31 A21 117 21 D30 A20 119 20 A19 121 19 A18 122 18 A17 131 17 A16 132 16 A15 134 15 14 30 1 CSE1 CSE0 29 2 28 3 D28 TC2 TC1 CS3 27 4 D27 26 5 D26 D29 MMC2107 PORT 25 24 10 D24 A14 136 23 12 D23 A13 137 13 22 15 D22 A12 139 12 21 16 D21 A11 6 11 20 17 D20 A10 11 10 19 20 D19 A9 13 9 SCK CS0 7B3 7B7 9D5 118 PROC_RESET 8C3 6A4< 128 CPUCLK_OUT 9C8 120 PROC_RESET_OUT SPI_SCK 93 18 21 D18 A8 14 8 DE* 143 17 22 D17 A7 23 7 SS* 94 16 25 D16 A6 24 6 15 27 D15 A5 26 5 14 30 D14 A4 28 4 13 31 D13 A3 29 3 12 34 D12 A2 47 2 11 35 A1 49 1 A0 50 0 B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSSSYN VSSF VSSA D0 D1 D2 D3 D10 2.93V A 8C1 8C2 D11 D4 TMS TRST* EXTAL TCLK 8C3 8D5 MISO XTAL XTAL OSC_MCU ONCE_TCLK ONCE_TRST_B ONCE_TMS 8C5 MOSI OUT IN INT0* YC0 YCO SPI_MOSI SPI_MISO INT2* INT1* 8A3< INT3* ONCE_DE_B 8C2 SPI_CS OUT UB02 MAX811_U SW01 PD 7A2> 7A6> 7C7< 7D7< 9D6 V3_3 1 4 3 MR* VCC 4 2 3 1 GND RESET* 2 10C5< 10C3< 10B6 INT4 RXD1 OUT D5 TXD1 D6 RSTOUT* RXD2 D7 CLKOUT TXD2 D8 RESET* TEST D9 ICOC10 36 37 38 39 40 41 42 43 46 48 51 114 73 126 140 127 76 64 44 32 18 8 ICOC11 10 9 8 7 6 5 4 3 2 1 0 58 D25 C PA A 67 A22 CS2 9D5 CS1 9D5 ICOC13 ICOC12 GND TEST63 SCI2_OUT 66 68 SCI2_IN SCI1_OUT 69 70 SCI1_IN TC2 144 7 57 61 MMC2107 CONTROL 10C5< 10C3< 56 CSE0 62 ICOC22 INT7* 8B8> 53 CSE1 60 ICOC23 INT5* 8B8< 52 V3_3 89 84 82 79 75 72 71 80 90 91 124 125 130 142 138 B ICOC23 ICOC22 ICOC21 ICOC20 ICOC13 ICOC12 ICOC11 ICOC10 D USER_LED1 USER_LED2 INT3 INT4 RUN_KIT_USR KIT_STATUS INT2 C VDDSYN U04 31 EB3* INT6* U04 88 TIM_16H_8L 96 EB3 EB2 98 100 EB1 7B4 9D4 101 EB0 7B7 9D5 104 PQB3 105 PQB2 PQB1 106 107 PQB0 PQA4 108 109 PQA3 110 PQA1 111 PQA0 133 ONCE_TDI 8D3 135 2107_TDO 8D3 D C02 1UF 7 7B7 9D5 8 RESET R05 9C8 10C2> 11B4< 1B5^ PROC_RESET 6B5 BEGINNING OF PROCESSOR HIERARCHY BLOCK 8C3 1.0K TITLE: DS26521DK02A0 DATE: ENGINEER: PAGE: 1/6(BLOCK) 10/26/2005 8 7 6 BLOCK NAME: _motprocrescard_dn. 5 4 PARENT BLOCK: \_ds26521topdn_\ 3 STEVE SCULLY 6/11(TOTAL) 2 PRINTED 1 Wed Oct 26 16:50:57 2005 CR-7 : @\_ZTOP_LIB\.\_DS26521TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE2 7 8 6 5 3 4 1 2 RESET CONFIGURATION 1 RB14 D V3_3 9D6 7A6> 6A2> PD 1 1 2 9D6 7A2> 6A2> PD 2 1 9D6 7A2> 6A2> PD 1 MASTER MODE D RB18 10K RB20 10K 2 1 1 10K RB16 RB15 FULL DRIVE 9D6 7A2> 6A2> PD 1 6D3 2 RCON 2 10K 1 10K RB08 XTAL W/ PLL 7A2> 6A2> 9D6 9D6 7A2> 6A2> PD 1 PD 1 1 2 RB21 10K 2 1 10K INTERNAL FLASH ENABLE RB09 9D6 6A2> 7A6> PD 1 2 10K C C RB19 2 28 A13 13 4 IO5 IO4 A12 23 A10 10 26 A9 9 27 A8 5 6 7 8 9 10 11 12 PA 28 A13 28 17 27 13 4 12 25 A11 IO2 15 26 IO1 14 25 11 23 A10 10 26 A9 IO0 13 9 27 A8 24 PD 6A2> 7C7< 7D7< 6B5 7B7 9D5 32 1 29 24 30 22 16 GND 14 WE* A14 N_C 3 VCC 15 29 18 8 7 6 5 4 3 2 1 6A1> 9B8 7A5 A15 30 21 23 20 22 19 21 18 20 17 19 IO2 15 18 IO1 14 17 IO0 13 16 IO7 IO6 CY62128V IO5 IO4 A12 A0 11 IO3 A1 A11 A2 25 A3 12 19 31 IO3 A A0 14 IO6 CY62128V A16 16 A6 A14 2 A7 3 20 17 31 5 6 7 8 9 10 11 12 15 21 B 9D6 9B8 7A8 6A1> PA PD 6A2> 7C7< 7D7< 9D6 8 7 6 5 4 3 2 1 GND CE2 OE* WE* N_C CE1* IO7 A5 CS0 U02 A15 A7 A 31 A16 A4 16 2 A6 17 VCC U01 CY62128V 32 1 29 24 30 22 16 CY62128V A5 B V3_3 EB0 OE V3_3 CE1* 10K CS0 WHEN SET FOR BOOT INTERNAL D18 HAS A 10K LOAD TO GND BOOT EXT D18 HAS A 10.5K LOAD TO V3V 2 A1 1 CE2 PD A2 BOOT INTERN/EXTERN A3 10K 1 RB17 6D7 9D4 6D3 7B7 9D5 1 EB1 OE PD OE* 6A2> A4 9D6 7A2> TITLE: DS26521DK02A0 DATE: ENGINEER: PAGE: 2/6(BLOCK) 10/26/2005 8 7 6 BLOCK NAME: _motprocrescard_dn. 5 4 PARENT BLOCK: \_ds26521topdn_\ 3 STEVE SCULLY 7/11(TOTAL) 2 1 CR-8 : @\_ZTOP_LIB\.\_DS26521TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE3 7 8 6 5 3 4 1 2 1 1 RB34 1.0M CON14P 1 D PLACE PADS FOR CAP BUT DO NOT POPULATE 2 1 1 J09 8.0MHZ D RB33 10K OSC_MCU 6A6 1 2 XB01 2 RB3210K V3_3 2 CON14P 6D6 6D6 XTAL 6A7 6A6 6B5 V3_3 PROC_RESET 1 2 3 4 5 6 7 8 9 10 11 6B5 12 13 6A6 14 ALIGN KEY ONCE_TMS 6A6 ONCE_DE_B ONCE_TRST_B C 1 C 1 10K RB43 2 6A4< ONCE_TDI 2107_TDO ONCE_TCLK V3_3 V- 17 3 IN CXN V3_3 FORCEON C2- 16 6 R1OUT C2+ 15 2 SHDN 7 T1OUT C1- 14 1 V3/5* 8 R1IN C1+ 13 9 VCC V+2 12 FORCEOFF* V+1 11 10 2 MAX1686_U 5 1.0K T1IN RB53 18 1 GND 7 T2IN 6 3 4 0.1UF 1 J11 U06 OUT PGND 8A8 INVALID* 2 8 2 B FLASH_VPP 1 6D3< 8A8 SCI1_IN PRT1_OUT PRT1_IN 19 2 CB39 CB36 10UF 6B8 T2OUT 1 GND B SCI1_OUT 20 4 6B8 V3_3 R2IN R2OUT CXP 1 5 UB01 MAX3233E V3_3 DS04 PRT1_OUT 8B8> 8B8< PRT1_IN 1 A 2 B 3 C F 4 D 5 E 10K 6A7 RB52 GREEN 1 1 2 A 330 6 G 7 H 8 J 9 TITLE: DS26521DK02A0 DATE: ENGINEER: PAGE: 3/6(BLOCK) 10/26/2005 CONN_DB9P 8 KIT_STATUS 2 1 10K 2 RB27 1 RB22 RB10 10K J05 2 A 1 2 1 1 1 7 6 BLOCK NAME: _motprocrescard_dn. 5 4 PARENT BLOCK: \_ds26521topdn_\ 3 STEVE SCULLY 8/11(TOTAL) 2 1 CR-9 : @\_ZTOP_LIB\.\_DS26521TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE4 5 PL7B 1 6 PL8A 2 7 PL8B 8 PL9A/PCLKT7_0 20 4 21 PLL INPUT PLL PL9B/PCLKC7_0 INPUT PT25B DS05 6A7 INT2 107 PR2B/VREF1_2 106 PR7A 105 PR7B PR8A 104 ALE_DUT 103 WR_DUT 10A6 10B2> 1B5^ PR8B 102 RD_DUT 10A6 10B2> 1B5^ PR9A/PCLKT2_0 101 PR9B/PCLKC2_0 100 C PR11A/D7/SPID0 11C8> 88 MEM_SO PR11B/BUSY/SISPI 87 MEM_SI PR12B/DI/CSSPI* 85 MEM_CS PR13A/RLM0_PLLT_IN_A 83 TRISTATE_AD_BUS 6 23 PL12B/LLM0_PLLC_FB_A 7 25 PL13A PR13B/RLM0_PLLC_IN_A 82 8 26 PL13B PLL INPUT PR14A/RLM0_PLLT_FB_A 81 9 27 PL14A PR14B/RLM0_PLLC_FB_A 79 10 29 PL14B PR15A/RDQS15 78 11 30 PL15A/LDQS15 PR15B 77 12 31 PL15B PR16A 76 13 32 PL16A PR16B 75 USERFPGA2 14 33 PL16B 15 34 PL18A/VREF1_6 16 35 PL18B/VREF2_6 B 0.0 RB51 74 INT5 10C3< MEM_SCK MEM_SCK MUST BE AT PIN77 FOR TQFP144 10C5< PB25B/D6/SPID1 PB24B/D5/SPID2 PB23B/D4/SPID3 PB23A PB22B/D3/SPID4 PB22A/BDQS22 PB21B/D1/SPID6 PB21A/D2/SPID5 PB20B/D0/SPID7 PB20A/VREF2_4 PB19B/CS* PB19A/VREF1_4 PB18B/CS1* PB18A/WRITE* 11B8< 56 57 58 59 60 61 62 64 65 66 67 68 69 70 PB16B/VREF1_5 PB16A/VREF2_5 PB15B PB15A PB14B PB14A/BDQS14 PB17A/PCLKT5_0 PLL PB17B/PCLKC5_0 INPUT BANK 3 BANK 6 PB13B PB11B PB11A 39 40 41 42 43 45 46 47 48 49 50 51 53 PR18A/VREF1_3 10B6 11C8< 22 BANK 4 1C5^ 330 5 BANK 5 10C5< RB50 PL11B/LLM0_PLLC_IN_A PLL PL12A/LLM0_PLLT_FB_A INPUT I/O PORT 10C3< V3_3 86 U05 LFEC_T144_U 10B6 INT_LED PR12A/DOUT/CSO* 97_IO PL11A/LLM0_PLLT_IN_A PT25A PT23A PT22B PT21B PT22A/TDQS22 PT21A PT20B PT17B/PCLKC0_0 PT16B/VREF1_0 PT16A/VREF2_0 PT15B PT15A PT14B PT13B PT14A/TDQS14 PT13A PT12B PT17A/PCLKT0_0 BANK 1 1 2 D PR2A/VREF2_2 BANK 2 5 PB10A B PL7A 0 3 BANK 0 BANK 7 PL2B/VREF1_7 9 PA PT12A PL2A/VREF2_7 PB10B C 2 RESET 3 CPUCLK_OUT4 PLL INPUT 10C2> 6A4 1B5^ 6B5 PT10B 31 30 29 28 27 26 25 24 23 22 21 20 11B4< PT20A PD 6A2> PT19B/VREF2_1 7A2> PT19A/VREF1_1 124 19 123 18 122 17 121 16 120 119 118 OE 116 RW 6D4 115 CS0 114 CS1 6B5 113 CS2 6C5 112 EB0 6D7 111 EB1 PT18A 7A6> PT18B 142 141 140 139 138 137 135 134 133 132 131 130 129 127 7C7< PT10A 7D7< D 3 4 7B7 6 6D7 7B4 7 8 10A6 10A6 10B2> 10B2> 7 6 5 4 3 2 1 0 D_DUT 10A6 10B2 10B2> 10B2> A_DUT_ TITLE: DS26521DK02A0 DATE: ENGINEER: PAGE: 4/6(BLOCK) 10/26/2005 1B5^ 1C5^ 10B2> 10B2> 1B5^ 10B7 CS_X3 CS_X4 CS_X5 0 1 2 3 4 5 6 7 8 9 12 A CS_X1 10A6 CS_X2 10A6 A 8 7 6 BLOCK NAME: _motprocrescard_dn. 5 4 PARENT BLOCK: \_ds26521topdn_\ 3 STEVE SCULLY 9/11(TOTAL) 2 1 CR-10 : @\_ZTOP_LIB\.\_DS26521TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE5 7 8 6 5 3 4 1 2 D D 2 10K 1 1 1 1 10K R06 10K RB55 2 2 RB44 10K RB54 2 V3_3 C 1C5^ 10C5< 10C3< 1C5^ 10C3< 10B6 9B4 6A7 6A7 6A7 INT5 9B4 10C3< 6A7 10C3< 10C5< 10C5< 10C5< 10B6 10B6 9C4 10B6 6A7 9C4 6A7 INT4 RESET 12 1 OUT 6A4 9C8 11B4< 1B5^ CS_X4 CS_X5 J10 2 2 OUT OUT OUT OUT OUT CS_X1 CS_X2 CS_X3 A_DUT_ 1 C INT3 INT2 NOPOP B INT5 INT4 INT3 INT2 IN IN IN IN 9A5 9A5 9A7 9A7 9A4 10A6 10A6 10A6 10A6 1C5^ B 2 8 3 3 4 4 1 7 5 5 6 6 0 6 7 7 8 8 5 9 9 10 4 11 11 12 3 13 13 14 WR_DUT RD_DUT INT3 6A7 10C3< 10C5< 10 INT2 6A7 9C4 10C3< 10C5< 1C5^ 12 TRISTATE_AD_BUS V3_3 9C3> 14 1 2 10K R07 CONN_14P A_DUT_ OUT 9C4 10A6 1B5^ OUT 9C4 10A6 1B5^ OUT 9A6 10B7 1B5^ D_DUT IO 9A6 10A6 1B5^ JUMPER PINS 12+14 TO TRISTATE THE ADDRESS DATABUSS OF THE FPGA. THIS ALLOWS THE USER TO CONNECT A DIFFERENT PROCESSOR NOPOP J07 D_DUT A 1 1 2 2 2 3 3 4 4 3 5 6 6 4 7 7 8 8 5 9 9 10 10 6 11 11 12 12 7 13 13 14 14 1 5 A 0 CS_X4 CS_X3 CS_X2 CS_X1 RD_DUT WR_DUT 9A5 10B2> 9A4 10B2> 9A7 10B2> 9A7 10B2> 1C5^ 9C4 10B2> 1B5^ 9C4 10B2> 1B5^ TITLE: DS26521DK02A0 DATE: ENGINEER: PAGE: 5/6(BLOCK) 10/26/2005 CONN_14P 8 7 6 BLOCK NAME: _motprocrescard_dn. 5 4 PARENT BLOCK: \_ds26521topdn_\ 3 STEVE SCULLY 10/11(TOTAL) 2 1 CR-11 : @\_ZTOP_LIB\.\_DS26521TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE6 7 8 6 5 3 4 1 2 I24 J01 L_TMS TCK 4 L_TCK L_TDI TDI 6 L_TDO 11C4> V3_3 11D6 11D6 I26 2.7V C 11D6 11D6 L_TCK 14 TCK L_TDI 16 TDI L_TDO 18 TDO L_TMS 17 9C4 9C4 9B3< 11B1 5 MEM_SO SI 2 SO MEM_SCK 6 MEM_CS SCK 1 VCC 8 90 CFG1 WP* 3 91 CFG0 CS* VCCIO7 VCCIO6B VCCIO6A VCCIO5B U05 LFEC_T144_U CONTROL ALL LOW FOR SPI3 MODE GND 4 1B5^ 10C2> 9C8 6A4 RESET 93 VCC3 99 VCCJ 19 VCCAUX1 54 VCCAUX2 126 NEEDS 10K,1% RESISTOR PLACE CLOSE TO PIN 7 HOLD* VCC2 V1_2 11A6< XRES 10 11B8< 9B3< CCLK 94 INIT* 95 DONE 97 PROGRAM* RB42 C 10K MEM_SCK I5 TP02 I6 TP01 10K RB48 NC2 NC1 B 11 12 GND10 GND9 GND8 GND7/GND0 GND6B/GND5 GND6A GND5 GND4 GND3B GND3A/GND4 128 117 109 72 80 63 52 28 37 144 15 96 98 GND0 B GND1 AT25160A_U GND2/GND1 1 1 9B4 MEM_SI CFG2 13 92 V3_3 TMS 89 VCC1 I10 97_IO UB04 V3_3 VCCIO5A CONN_10P VCCIO4B 10 VCCIO4A VCC VCCIO3B GND VCCIO3A TDO 9 11C4< RB07 10K RB06 10K 7 8 VCCIO2 5 7 11C4< VCCIO1B 3 D V3_3 11C4< VCCIO1A 3 5 2 TMS VCCIO0B 1 VCCIO0A 1 136 143 110 125 108 73 84 55 71 38 44 24 36 1 D I28 UB05 MAX1963 SHDN* 2 GND OUT 6 IC 5 RST* 4 11C1< V1_2 CB37 10UF CB34 10UF CB28 10UF IN 3 CB33 .1UF CB35 .1UF 1 CB27 .1UF V3_3 A A END OF PROCESSOR HIERARCHY BLOCK TITLE: DS26521DK02A0 DATE: ENGINEER: PAGE: 6/6(BLOCK) 10/26/2005 8 7 6 BLOCK NAME: _motprocrescard_dn. 5 4 PARENT BLOCK: \_ds26521topdn_\ 3 STEVE SCULLY 11/11(TOTAL) 2 1