±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
SPI is a trademark of Motorola, Inc.
UCSP is a trademark of Maxim Integrated Products, Inc.
PIN-PACKAGE
8 TDFN-EP**
MAX3394EEBL+T
9 UCSP
MAX3395EETC+
12 TQFN-EP**
MAX3395EEBC+T
12 UCSP
MAX3396EEBP+T*
20 UCSP
MAX3396EETP+*
20 TQFN-EP**
PKG CODE
T833-1
B9-5
T1244-4
B12-1
B20-1
T2055-4
Note: All devices specified over the -40°C to +85°C operating
range.
+Denotes lead(Pb)-free/RoHS-compliant package.
*Future product—contact factory for availability.
**EP = Exposed paddle.
Selector Guide appears at end of data sheet.
TOP VIEW
(LEADS ON BOTTOM)
8
GND
Pin Configurations
7
6
5
*EP
MAX3394E
+
1
2
3
4
I/O VCC2
MICROWIRE is a trademark of National Semiconductor Corp.
PART
MAX3394EETA+T
I/O VL1
Multivoltage Bidirectional Level Translation
SPI™, MICROWIRE™, and I2C Level Translation
Open-Drain Rise-Time Speed-Up
High-Speed Bus Fan-Out Expansion
Cell Phones
Telecom, Networking, Servers, RAID/SAN
Ordering Information
I/O VL2
●●
●●
●●
●●
●●
●●
●● ±15kV ESD Protection on I/O VCC_ Lines
●● Bidirectional Level Translation Without Direction Pin
●● I/O VL_ and I/O VCC_ 10mA Sink-/15mA SourceCurrent Capability
●● Slew-Rate Enhancement Circuitry Supports
●● Larger Capacitive Loads or Larger External Pullup
Resistors
●● 6Mbps Push-Pull/1Mbps Open-Drain Guaranteed
Data Rate
●● Wide Supply-Voltage Range: Operation Down to
+1.2V on VL and +1.65V on VCC
●● Low Supply Current in Tri-State Output Mode
(3μA typ)
●● Low Quiescent Current
●● Thermal-Shutdown Protection
●● UCSP, TDFN, and TQFN Packages
I/O VCC1
Applications
Features
VL
The MAX3394E/MAX3395E/MAX3396E bidirectional level
translators provide level shifting required for data transfer
in a multivoltage system. Internal slew-rate enhancement
circuitry features 10mA current-sink and 15mA currentsource drivers to isolate capacitive loads from lower current
drivers. In open-drain systems, slew-rate enhancement
enables fast data rates with larger pullup resistors and
increased bus load capacitance. Externally applied voltages, VCC and VL, set the logic-high levels for the device.
A logic-low signal on one I/O side of the device appears as
a logic-low signal on the opposite I/O side, and vice-versa.
Each I/O line is pulled up to VCC or VL by an internal pullup
resistor, allowing the devices to be driven by either pushpull or open-drain drivers.
The MAX3394E/MAX3395E/MAX3396E feature a tristate output mode, thermal-shutdown protection, and
±15kV Human Body Model (HBM) ESD protection on the
VCC side for greater protection in applications that route
signals externally.
The MAX3394E/MAX3395E/MAX3396E accept VCC voltages from +1.65V to +5.5V, and VL voltages from +1.2V
to VCC, making them ideal for data transfer between low
voltage ASIC/PLDs and higher voltage systems. The
MAX3394E/MAX3395E/MAX3396E operate at a guaranteed data rate of 6Mbps with push-pull drivers and 1Mbps
with open-drain drivers.
The MAX3394E is a dual-level translator available in
9-bump UCSP™ and 8-pin 3mm x 3mm TDFN packages.
The MAX3395E is a quad-level translator available in
12-bump UCSP, and 12-pin 4mm x 4mm TQFN packages. The MAX3396E is an octal-level translator available in
20-bump UCSP and 20-pin 5mm x 5mm TQFN packages.
The MAX3394E/MAX3395E/MAX3396E operate over the
extended -40°C to +85°C temperature range.
EN
General Description
VCC
MAX3394E/MAX3395E/
MAX3396E
TDFN
*CONNECT EXPOSED PAD TO GROUND
Pin Configurations continued at end of data sheet.
19-3884; Rev 3; 7/17
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Absolute Maximum Ratings
(All voltages referenced to GND.)
VCC...........................................................................-0.3V to +6V
VL.............................................................................-0.3V to +6V
I/O VCC_.......................................................-0.3V to VCC + 0.3V
I/O VL_............................................................ -0.3V to VL + 0.3V
EN............................................................................-0.3V to +6V
Short-Circuit Duration I/O VL_, I/O VCC_ to GND......Continuous
Maximum Continuous Current..........................................±50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin TDFN (derate 18.2mW/°C above +70°C).........1455mW
9-Bump UCSP (derate 4.7mW/°C above +70°C).........379mW
12-Pin TQFN (derate 16.9mW/°C above +70°C).......1349mW
12-Bump UCSP (derate 6.5mW/°C above +70°C).......519mW
20-Pin TQFN (derate 20.8mW/°C above +70°C).......1667mW
20-Bump UCSP (derate 10.0mW/°C above +70°C).....800mW
Operating Temperature Range............................ -40°C to +85°C
Storage Temperature Range............................. -65°C to +150°C
Junction Temperature.......................................................+150°C
Bump Temperature (soldering).........................................+235°C
Lead Temperature (soldering, 10s).................................. +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VCC = +1.65V to +5.5V, VL = +1.2V to VCC; CIOVL ≤ 15pF, CIOVCC ≤ 15pF; TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
VL Supply Range
VCC Supply Range
Supply Current from VCC
Supply Current from VL
VCC Tri-State Supply Current
VL Tri-State Supply Current
VL
1.2
VCC
V
VCC
1.65
5.50
V
ICC
IL
I/O lines internally pulled up
I/O lines internally pulled up
MAX3394E
150
MAX3395E
300
MAX3396E
600
MAX3394E
30
MAX3395E
30
MAX3396E
30
µA
µA
ICC-3
EN = GND, TA = +25°C
3
6
µA
IL-3
EN = GND, TA = +25°C
0.7
2
µA
LOGIC I/O
I/O VL_ Input-Voltage High
Threshold
VIHL
I/O VL_ Input-Voltage Low
Threshold
VILL
I/O VL_ Internal Pullup DC
Resistance
RL
EN = VCC or VL
I/O VL_ Source Current During
Low-to-High Transition
IIHL
VL = +1.2V
15
mA
I/O VL_ Sink Current During
High-to-Low Transition
IILL
VCC = +1.65V
10
mA
www.maximintegrated.com
0.7 x
VL
5
V
10
0.3 x
VL
V
20
kΩ
Maxim Integrated │ 2
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Electrical Characteristics (continued)
(VCC = +1.65V to +5.5V, VL = +1.2V to VCC; CIOVL ≤ 15pF, CIOVCC ≤ 15pF; TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
I/O VL_ Low-to-High Transition
Threshold
VL-TH
I/O VL_ Output-Voltage Low
VOLL
I/O VL_ Tri-State Output Leakage
Current
CONDITIONS
VCC = +3.3V, VL = +1.8V
MIN
TYP
0.3 x
VL
0.5 x
VL
I/O VL_ sink current = 5mA, VILC = 0V
UNITS
V
0.25
I/O VL_ sink current = 10mA, VILC ≤ 0.4V or
0.2 x VL
EN = GND, TA = +25°C
MAX
-1
VILC +
0.4V
V
+1
µA
I/O VCC_ Input-Voltage High
Threshold
VIHC
(Note 2)
I/O VCC_ Input-Voltage Low
Threshold
VILC
(Note 2)
I/O VCC_ Internal Pullup DC
Resistance
RCC
EN = VCC or VL
I/O VCC_ Source Current During
Low-to-High Transition
IIHCC
VCC = +1.65V
15
mA
I/O VCC_ Sink Current During
High-to-Low Transition
IILCC
VCC = +1.65V
10
mA
0.5 x
VCC
V
I/O VCC_ Low-to-High Transition
Threshold
I/O VCC_ Output-Voltage Low
VCC-TH
VOLC
I/O VCC_ Tri-State Output
Leakage Current
VIHE
EN Input-Voltage Low Threshold
VILE
5
0.3 x
VCC
V
10
I/O VCC_ sink current = 5mA, VILL = 0V
0.3 x
VCC
V
20
kΩ
0.25
I/O VCC_ sink current = 10mA, VILL ≤ 0.4V
or 0.2 x VL
EN = GND, TA = +25°C
EN Input-Voltage High Threshold
EN Pin Input Leakage Current
VCC = +3.3V, VL = +1.8V
0.7 x
VCC
-1
VILL +
0.4V
V
+1
µA
0.7 x
VL
TA = +25°C
V
-1
0.3 x
VL
V
+1
µA
ESD PROTECTION
I/O VCC_ ESD Protection
www.maximintegrated.com
CVCC = 1µF, Human Body Model
±15
kV
Maxim Integrated │ 3
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Timing Characteristics
(VCC = +1.65V to +5.5V, VL = +1.2V to VCC; CIOVL ≤ 15pF, CIOVCC ≤ 15pF; TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
I/O VCC_ Rise Time
tRVCC
I/O VCC_ Fall Time
tFVCC
I/O VL_ Rise Time
tRVL
I/O VL_ Fall Time
tFVL
tI/OVL-VCC
Propagation Delay
tI/OVCC-VL
Propagation Delay After EN
tEN
Channel-to-Channel Skew
tSKEW
Maximum Data Rate
CONDITIONS
MIN
TYP
MAX
Push-pull driver, Figure 1
50
Open-drain driver, internal pullup, Figure 2
500
Push-pull driver, Figure 1
50
Open-drain driver, internal pullup, Figure 2
50
Push-pull driver, Figure 3
50
Open-drain driver, internal pullup, Figure 4
500
Push-pull driver, Figure 3
50
Open-drain driver, internal pullup, Figure 4
50
Push-pull driver, Figure 1
50
Open-drain driver, internal pullup, Figure 2
600
Push-pull driver, Figure 3
50
Open-drain driver, internal pullup, Figure 4
600
Push-pull or open-drain driver, Figure 5
5
Push-pull driver
5
Open-drain driver, internal pullup
100
Push-pull driver, Figures 1, 3
6
Open-drain driver, internal pullup,
Figures 2, 4
1
UNITS
ns
ns
ns
ns
ns
µs
ns
Mbps
Note 1: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2: During a low-to-high transition, the threshold at which the I/O changes state is the lower of VILL and VILC since the two
sides are internally connected by an internal switch while the device is in the logic-low state.
www.maximintegrated.com
Maxim Integrated │ 4
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Typical Operating Characteristics
(VCC = +2.5V, VL = +1.8V, CL = 15pF, TA = +25°C, unless otherwise noted.)
1.5
1.0
0.5
3.0
3.5
4.0
4.5
1.0
0
5.5
4.0
4.5
0
5.0
-40
-15
10
35
60
2.0
1.5
0
0
10
35
60
85
6Mbps PUSH-PULL
1.0
0.8
0.7
0.6
0.5
0.4
0.3
1Mbps OPEN-DRAIN
0.2
0.1
1Mbps OPEN-DRAIN
0
DRIVING I/O VL_
0.9
0
10 20 30 40 50 60 70 80 90 100
6Mbps PUSH-PULL
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
OPEN-DRAIN RISE TIME
vs. LOAD CAPACITANCE
OPEN-DRAIN FALL TIME
vs. LOAD CAPACITANCE
PUSH-PULL RISE TIME
vs. LOAD CAPACITANCE
MAX3394E-96E toc07
30
350
DRIVING I/O VL_
DRIVING I/O VCC_
100
DRIVING I/O VCC_
25
FALL TIME (ns)
400
20
15
10
5
50
30
25
MAX3394E–96E toc09
TEMPERATURE (°C)
450
85
MAX3394E-96E toc06
2.5
0.5
-15
DRIVING I/O VL_
1.0
MAX3394E–96E toc03
0.2
0.1
VL SUPPLY CURRENT (mA)
3.0
0.05
0
3.5
0.3
VL SUPPLY CURRENT
vs. LOAD CAPACITANCE
0.10
150
3.0
1Mbps OPEN-DRAIN
0.4
VCC SUPPLY CURRENT
vs. LOAD CAPACITANCE
1Mbps OPEN-DRAIN
200
2.5
0.5
VL SUPPLY CURRENT
vs. TEMPERATURE
0.15
250
2.0
0.6
TEMPERATURE (°C)
0.20
300
1.5
0.7
VL SUPPLY VOLTAGE (V)
6Mbps PUSH-PULL
-40
1Mbps OPEN-DRAIN
6Mbps PUSH-PULL
0.8
VCC SUPPLY VOLTAGE (V)
0.25
500
RISE TIME (ns)
5.0
DRIVING I/O VL_
0.30
VL SUPPLY CURRENT (mA)
2.5
6Mbps PUSH-PULL
DRIVING I/O VL_
0.9
RISE TIME (ns)
0.35
2.0
1.5
MAX3394E-96E toc05
1.5
2.0
0.5
1Mbps OPEN-DRAIN
VCC SUPPLY CURRENT (mA)
0
2.5
VCC SUPPLY CURRENT
vs. TEMPERATURE
1.0
VCC SUPPLY CURRENT (mA)
6Mbps PUSH-PULL
MAX3394E–96E toc02
2.0
VCC = +5.0V
DRIVING I/O VL_
MAX3394E–96E toc08
2.5
VL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
3.0
VL SUPPLY CURRENT (mA)
VL = +1.2V
DRIVING I/O VL_
MAX3394E–96E toc04
VCC SUPPLY CURRENT (mA)
3.0
MAX3394E–96E toc01
VCC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DRIVING I/O VL_
20
15
DRIVING I/O VCC_
10
5
DRIVING I/O VL_
0
10 20 30 40 50 60 70 80 90 100
CAPACITIVE LOAD (pF)
www.maximintegrated.com
0
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
0
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
Maxim Integrated │ 5
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Typical Operating Characteristics (continued)
(VCC = +2.5V, VL = +1.8V, CL = 15pF, TA = +25°C, unless otherwise noted.)
6
4
DRIVING I/O VL_
15
10
5
0
0
10 20 30 40 50 60 70 80 90 100
12
10
8
6
tPDHL
4
tPDLH
2
10 20 30 40 50 60 70 80 90 100
0
0
10 20 30 40 50 60 70 80 90 100
PROPAGATION DELAY
vs. LOAD CAPACITANCE
PROPAGATION DELAY
vs. LOAD CAPACITANCE
(DRIVING I/O VL_, VCC = +2.5V, VL = +1.8V,
CL = 15pF, DATA RATE = 6Mbps)
35
tPDHL
30
25
20
15
10
20
DRIVING I/O VCC_ PUSH-PULL
SEE FIGURE 3
18
tPDLH
5
0
14
LOAD CAPACITANCE (pF)
40
0
0
16
LOAD CAPACITANCE (pF)
DRIVING I/O VL_ PUSH-PULL
45
tPDLH
DRIVING I/O VCC_ OPEN-DRAIN
18
LOAD CAPACITANCE (pF)
PROPAGATION DELAY (ns)
0
tPDHL
20
2
50
PROPAGATION DELAY (ns)
25
20
PROPAGATION DELAY (ns)
8
MAX3394E-96E toc11
DRIVING I/O VCC_
DRIVING I/O VL_ OPEN-DRAIN
PROPAGATION DELAY
vs. LOAD CAPACITANCE
16
14
12
10
8
tPDHL
I/O VCC_
1V/div
6
4
0
0
40ns/div
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
(DRIVING I/O VL_, VCC = +5.0V, VL = +3.3V,
CL = 400pF, EXTERNAL 4.7kΩ
PULLUPS, DATA RATE = 1Mbps)
(DRIVING I/O VL_, VCC = +5.0V, VL = +3.3V,
CL = 100pF, DATA RATE = 1Mbps)
MAX3394E-96E toc17
MAX3394E-96E toc16
www.maximintegrated.com
I/O VL_
1V/div
2
10 20 30 40 50 60 70 80 90 100
200ns/div
MAX3394E-96E toc15
MAX3394E-96E toc14
10
MAX3394E–96E toc13
FALL TIME (ns)
12
30
PROPAGATIN DELAY (ns)
MAX3394E-96E toc10
14
PROPAGATION DELAY
vs. LOAD CAPACITANCE
MAX3394E-96E toc12
PUSH-PULL FALL TIME
vs. LOAD CAPACITANCE
I/O VL_
2V/div
I/O VL_
2V/div
I/O VCC_
2V/div
I/O VCC_
2V/div
200ns/div
Maxim Integrated │ 6
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Pin Description
PIN
MAX3394E
TDFN
1
UCSP
MAX3395E
TQFN
A1
11
UCSP
B1
MAX3396E
TQFN
14
NAME
FUNCTION
VCC
VCC Supply Voltage +1.65V ≤ VCC ≤ +5.5V. Bypass
VCC to GND with a 0.1µF ceramic capacitor and
a 1µF or greater ceramic capacitor as close to the
device as possible.
Enable Input. Drive EN logic high for normal
operation. Drive EN logic low to force all I/O lines
to a high-impedance state and disconnect internal
pullup resistors.
UCSP
D3
2
B1
6
B3
4
A4
EN
3
A2
10
C1
18
C1
I/O VCC1
I/O 1 Referred to VCC
4
A3
9
C2
16
D1
I/O VCC2
I/O 2 Referred to VCC
5
B3
5
B4
13
D4
GND
6
C3
2
A2
20
A1
I/O VL2
I/O 2 Referred to VL
7
C2
1
A1
19
B1
I/O VL1
I/O 1 Referred to VL
8
C1
12
B2
3
A3
VL
—
—
3
A3
1
B2
I/O VL3
I/O 3 Referred to VL
—
—
4
A4
2
A2
I/O VL4
I/O 4 Referred to VL
—
—
7
C4
15
D2
I/O VCC4
I/O 4 Referred to VCC
—
—
8
C3
17
C2
I/O VCC3
I/O 3 Referred to VCC
—
—
—
—
12
C3
I/O VCC5
I/O 5 Referred to VCC
—
—
—
—
11
D5
I/O VCC6
I/O 6 Referred to VCC
—
—
—
—
10
C4
I/O VCC7
I/O 7 Referred to VCC
—
—
—
—
9
C5
I/O VCC8
I/O 8 Referred to VCC
—
—
—
—
5
B3
I/O VL5
I/O 5 Referred to VL
—
—
—
—
6
A5
I/O VL6
I/O 6 Referred to VL
—
—
—
—
7
B4
I/O VL7
I/O 7 Referred to VL
—
—
—
—
8
B5
I/O VL8
I/O 8 Referred to VL
EP
—
EP
—
EP
—
EP
Detailed Description
The MAX3394E/MAX3395E/MAX3396E bidirectional level
translators provide level shifting required for data transfer
in a multivoltage system. Internal slew-rate enhancement
circuitry features 10mA current-sink and 15mA currentsource drivers to isolate capacitive loads from lower current drivers. In open-drain systems, slew-rate enhancement enables fast data rates with larger pullup resistors
www.maximintegrated.com
Ground
Logic Supply Voltage +1.2V ≤ VL ≤ VCC. Bypass VL
to GND with a 0.1µF or greater ceramic capacitor
as close to the device as possible.
Exposed Pad. Connect exposed pad to GND.
and increased bus load capacitance. Externally applied
voltages, VCC and VL, set the logic-high levels for the
device. A logic-low signal on one I/O side of the device
appears as a logic-low signal on the opposite I/O side and
vice-versa. Each I/O line is pulled up to VCC or VL by an
internal pullup resistor, allowing the devices to be driven
by either push-pull or open-drain drivers.
Maxim Integrated │ 7
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
VL
tRVCC
VCC
VL
VL
EN
VCC
MAX3394E
MAX3395E
MAX3396E
VCC
tFVCC
90%
90%
I/O VL
50%
50%
50%
50%
I/O VL_
I/O VCC_
50Ω
I/O VCC
10%
10%
CIOVCC
tI/OVL-VCC
tI/OVL-VCC
Figure 1. Push-Pull Driving I/O VL_Test Circuit and Timing
VL
tRVCC
VCC
VL
VL
EN
MAX3394E
MAX3395E
MAX3396E
90%
VCC
VGATE
90%
50%
VCC
50%
50%
50%
I/O VL_
tFVCC
I/O VCC
I/O VCC_
10%
10%
VGATE
CIOVCC
tI/OVL-VCC
tI/OVL-VCC
Figure 2. Open-Drain Driving I/O VL_ Test Circuit and Timing
The MAX3394E/MAX3395E/MAX3396E feature a tristate output mode, thermal-shutdown protection, and
±15kV Human Body Model (HBM) ESD protection on the
VCC side for greater protection in applications that route
signals externally.
The MAX3394E/MAX3395E/MAX3396E accept VCC voltages from +1.65V to +5.5V, and VL voltages from +1.2V
to VCC, making them ideal for data transfer between
low-voltage ASIC/PLDs and higher voltage systems. The
MAX3394E/MAX3395E/MAX3396E operate at a guaran-
www.maximintegrated.com
teed data rate of 6Mbps with push-pull drivers and 1Mbps
with open-drain drivers.
Level Translation
The MAX3394E/MAX3395E/MAX3396E utilize a transmission gate architecture to provide bidirectional level
translation between I/O VL_ and I/O VCC_. The transmission gate architecture is comprised of a pass-FET,
gate-control logic, and slew-rate enhancement circuitry.
When both I/O VL_ and I/O VCC_ are logic high,
the gate-control logic disables the pass-FET, providing
Maxim Integrated │ 8
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
VL
VL
VL
EN
tFVL
tRVL
VCC
I/O VCC
VCC
MAX3394E
MAX3395E
MAX3396E
VCC
90%
50%
50%
I/O VCC_
I/O VL_
50Ω
CIOVL
90%
50%
50%
10%
10%
I/O VL
tI/OVCC-VL
tI/OVCC-VL
Figure 3. Push-Pull Driving I/O VCC_ Test Circuit and Timing
VL
tRVL
VCC
VL
VL
EN
MAX3394E
MAX3395E
MAX3396E
tFVL
VCC
I/O VL
50%
VCC
90%
50%
I/O VL_
I/O VCC_
CIOVL
90%
50%
50%
10%
VGATE
tI/OVCC-VL
10%
tI/OVCC-VL
Figure 4. Open-Drain Driving I/O VCC_ Test Circuit and Timing
capacitive isolation between I/O lines. When one or both
I/O lines are at a logic-low level, the gate-control logic
turns the pass-FET on. When the pass-FET is active, I/O
VL_ and I/O VCC_ are connected, allowing the logic-low
signal to be expressed simultaneously on both I/O lines.
The MAX3394E/MAX3395E/MAX3396E have internal
10kΩ (typ) pullup resistors from I/O VL_ and I/O VCC_
to the respective supply voltages, allowing operation
with open-drain drivers. Internal slew-rate enhancement
circuitry accelerates logic-state transitions, maintaining a fast data rate with a higher bus load capacitance.
Additionally, the 10mA current sink drivers permit the use
of smaller external pullup resistors.
www.maximintegrated.com
Internal Slew-Rate Enhancement
Internal slew-rate enhancement circuitry accelerates logic-state changes by turning on MOSFETs MP1 and MP2
during low-to-high logic transitions, and MOSFETs MN3
and MN4 during high-to-low logic transitions (see the
Functional Diagram). During logic-state changes, speedup MOSFETS are triggered by I/O line voltage thresholds.
MOSFETS MN3 and MN4 sink 10mA during high-to-low
logic transitions. MP1 and MP2 source 15mA during lowto-high logic transitions. Slew-rate enhancement allows
a fast data rate despite large capacitive bus loads, and
permits larger external pullup resistors.
Maxim Integrated │ 9
MAX3394E/MAX3395E/
MAX3396E
VL
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
VCC
VL
EN
VL
VL
VCC
MAX3394E
MAX3395E
MAX3396E
RLOAD
CIOVCC
50Ω
MAX3394E
MAX3395E
MAX3396E
I/O VL_
I/O VCC_
I/O VL_
VL
RLOAD
VCC
VL
EN
VCC
VCC
VCC
I/O VCC_
CIOVL
50Ω
tEN
V
I/O VCC_
EN
0.5V
TIME
V
tEN
I/O VL_
EN
0.2V (VL < 2V)
0.5V (VL 2V)
TIME
Figure 5. Enable Test Circuit and Timing
Power-Supply Sequencing
The MAX3394E/MAX3395E/MAX3396E require two supply voltages. For proper operation, ensure that +1.65V ≤
VCC ≤ +5.5V, and +1.2V ≤ VL ≤ VCC. There are no restrictions on power-supply sequencing. During power-up or
power-down, the MAX3394E/MAX3395E/MAX3396E can
withstand either the VL or the VCC supply floating while
the other supply is applied. The device will not latch up in
this state.
www.maximintegrated.com
Tri-State Output Mode
Connect EN to VL or VCC for normal operation. Drive EN
low to force the MAX3394E/MAX3395E/MAX3396E to a
tri-state output mode. In tri-state output mode, all I/O lines
are driven to a high-impedance state, and the pass-FET
is disabled to prevent current flow between I/O lines. Tristate output mode disables the internal pullup resistors on
I/O VL_ and I/O VCC_, and reduces supply current to 3μA
typ (VCC) and 0.7μA typ (VL).
Maxim Integrated │ 10
MAX3394E/MAX3395E/
MAX3396E
RC
1MΩ
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
Cs
100pF
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
RD
1500Ω
IP 100%
90%
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
DEVICEUNDERTEST
36.8%
10%
0
0
tRL
TIME
tDL
CURRENT WAVEFORM
Figure 6a. Human Body ESD Test Model
Figure 6b. HBM Discharge Current Waveform
The high-impedance state of the I/O lines during tri-state
output mode facilitates use in multidrop networks. In tristate output mode, do not exceed (VL + 0.3V) on I/O VL_
or (VCC + 0.3V) on I/O VCC_.
To ensure full ±15kV ESD protection, bypass VCC to
ground with a 0.1μF ceramic capacitor and an additional
1μF ceramic capacitor as close to the device as possible.
Thermal-Shutdown Protection
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report documenting test
setup, methodology, and results.
The MAX3394E/MAX3395E/MAX3396E are protected
from thermal damage resulting from short-circuit faults. In
the event of a short-circuit fault, when the junction temperature (TJ) reaches +125°C, a thermal sensor forces
the device into the tri-state output mode. When TJ drops
below +115°C, normal operation resumes.
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against ESD encountered during handling and assembly. The I/O VCC_ lines
are further protected by advanced ESD structures to
guard these pins from damage caused by ESD of up to
±15kV. Protection structures prevent damage caused by
ESD events in normal operation, tri-state output mode,
and when the device is unpowered. After arresting an
ESD event, MAX3394E/MAX3395E/MAX3396E continue
to function without latching up, whereas competing devices can enter a latched-up state and must be power cycled
to restore functionality.
Several ESD testing standards exist for gauging the
robustness of ESD structures. The ESD protection of
the MAX3394E/MAX3395E/MAX3396E is characterized
for the human body model (HBM). Figure 6a shows the
model used to simulate an ESD event resulting from contact with the human body. The model consists of a 100pF
storage capacitor that is charged to a high voltage then
discharged through a 1.5kΩ resistor. Figure 6b shows
the current waveform when the storage capacitor is discharged into a low impedance.
www.maximintegrated.com
ESD Test Conditions
Applications Information
Power-Supply Decoupling
Bypass VL and VCC to ground with 0.1μF ceramic capacitors. To ensure full ±15kV ESD protection, bypass VCC to
ground with an additional 1μF or greater ceramic capacitor. Place all capacitors as close to the device as possible.
Open-Drain Mode vs. Push-Pull Mode
The MAX3394E/MAX3395E/MAX3396E are compatible
with push-pull (active) and open-drain drivers. For pushpull operation, maximum data rate is guaranteed to
6Mbps. For open-drain applications, the MAX3394E/
MAX3395E/MAX3396E include internal pullup resistors
and slew-rate enhancement circuitry, providing a maximum data rate of 1Mbps. External pullup resistors can
be added to increase data rate when the bus is loaded
by high capacitance. (See the Use of External Pullup
Resistors section.)
Serial-Interface Level Translation
The MAX3395E provides level translation on four I/O
lines, making it an ideal device for multivoltage I2C,
MICROWIRE, and SPI serial interfaces.
Use of External Pullup Resistors
The MAX3394E/MAX3395E/MAX3396E include internal
10kΩ pullup resistors. During a low-to-high logic transition, the internal pullup resistors charge the bus capaci-
Maxim Integrated │ 11
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Functional Diagram
VCC
VL
VL
VCC
MP1
MP2
GATE CONTROL
I/O VL_
I/O VCC_
N-CHANNEL
PASS-FET
SLEW-RATE
ENHANCEMENT
MN3
MN4
Typical Operating Circuit
+1.8V
+3.3V
0.1µF
+1.8V
SYSTEM
CONTROLLER
EN
CLK
DATA
GND
VL
EN
I/O VL1
I/O VL2
+3.3V
SYSTEM
I/O VCC1
CLK
I/O VCC2
DATA
GND
The MAX3395E provides level translation for Class A, B,
and C smart cards. When supply voltage VCC is interrupted due to the disconnection of a smart card, the
www.maximintegrated.com
1µF
MAX3394E
tance with a characteristic RC charging waveform. When
the low-to-high transition threshold (VCC-TH or VLTH) is
reached, the rise time accelerators switch on, sourcing
15mA to fully charge the bus capacitance. External pullup
resistors reduce the time needed to reach the low-to-high
transition threshold, thereby increasing the data rate.
In the logic-low state however, external pullup resistors
increase the DC current through the internal pass-FET,
increasing the output voltage of the device.
Smart-Card Interface
0.1µF
VCC
GND
device does not latch up. Normal operation resumes upon
restoration of the VCC supply voltage. The MAX3395E
provides bidirectional level translation on four I/O lines,
making it well suited for buffering and translating 4-wire
serial interfaces.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profiles, as well as the latest information on reliability
testing results, go to Maxim’s web site at www.maximintegrated.com/ucsp to find the Application Note 1891:
Wafer-Level Packaging (WLP) and Its Applications.
Maxim Integrated │ 12
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Pin Configurations (continued)
TOP VIEW
(BUMPS ON BOTTOM)
1
2
3
VCC
I/O VCC1
I/O VCC2
A
B
MAX3394E
EN
GND
C
VL
I/O VL1
I/O VL2
I/O VCC1
11
VL
12
I/O VCC4
9
8
7
TOP VIEW
(BUMPS ON BOTTOM)
1
2
3
4
MAX3395E
A
*EP
10
VCC
I/O VCC3
TOP VIEW
(LEADS ON BOTTOM)
I/O VCC2
UCSP
MAX3395E
6
EN
5
GND
4
I/O VL4
I/O VL3
I/O VL2
I/O VL1
I/O VL3
I/O VL4
VCC
VL
EN
GND
I/O VCC1
I/O VCC2
I/O VCC3
I/O VCC4
C
3
2
I/O VL2
B
+
1
I/O VL1
TQFN
UCSP
VCC
GND
I/O VCC5
I/O VCC6
TOP VIEW
(LEADS ON BOTTOM)
I/O VCC4
*CONNECT EXPOSED PAD TO GROUND
15
14
13
12
11
I/O VCC2 16
*EP
I/O VCC3 17
MAX3396E
TOP VIEW
(BUMPS ON BOTTOM)
1
10
I/O VCC7
9
I/O VCC8
8
I/O VL8
7
I/O VL7
I/O VL2 20
6
I/O VL6
4
5
I/O VL5
I/O VL4
3
EN
2
VL
1
I/O VL3
+
TQFN
*CONNECT EXPOSED PAD TO GROUND
3
4
5
MAX3396E
I/O VL1 19
I/O VCC1 18
2
A
I/O VL2
I/O VL4
VL
EN
I/O VL6
I/O VL1
I/O VL3
I/O VL5
I/O VL7
I/O VL8
I/O VCC1
I/O VCC3
I/O VCC5
I/O VCC7
I/O VCC8
I/O VCC2
I/O VCC4
VCC
GND
I/O VCC6
B
C
D
UCSP
www.maximintegrated.com
Maxim Integrated │ 13
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Selector Guide
Chip Information
NUMBER OF
TRANSLATORS
TOP
MARK
MAX3394EETA+T
2
APE
MAX3394EEBL+T
2
AEZ
MAX3395EETC+
4
AAFZ
MAX3395EEBC+T
4
ACO
MAX3396EEBP+T
8
—
MAX3396EETP+
8
—
PART
PROCESS: BiCMOS
CONNECT EXPOSED PAD TO GND.
Note: All devices specified over the -40°C to +85°C operating
range.
+Denotes lead(Pb)-free/RoHS-compliant package.
www.maximintegrated.com
Maxim Integrated │ 14
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
maxim
integrated
COMMON DIMENSIONS
PACKAGE VARIATIONS
MIN
NOM
MAX
PKG. CODE
N
D2
E2
e
JEDEC SPEC
b
[(N/2)-1] x e
A
0.70
0.75
0.80
T633-2
6
1.50±0.10
2.30±0.10
0.95 BSC
MO229 / WEEA
0.40±0.05
1.90 REF
D
2.90
3.00
3.10
T633-2C
6
1.50±0.10
2.30±0.10
0.95 BSC
MO229 / WEEA
0.40±0.05
1.90 REF
E
2.90
3.00
3.10
T633MK-1
6
1.50±0.10
2.30±0.10
0.95 BSC
MO229 / WEEA
0.40±0.05
1.90 REF
A1
0.00
0.025
0.05
T833-1F
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
L
0.20
0.30
0.40
T833-2
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
SYMBOL
k
0.25 MIN.
T833-2C
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
A2
0.20 REF.
T833-3
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
T833-3C
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
T1033-1
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
T1033-1C
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
T1033MK-1
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
T1033-2
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
T1033-4
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
T1433-1
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
T1433-2
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
T1433-2C
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
T1433-3F
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
maxim
integrated
www.maximintegrated.com
TM
TM
Maxim Integrated │ 15
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
www.maximintegrated.com
Maxim Integrated │ 16
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Pin 1
Indicator
A
E
1
see Note 7
Marking
AAAA
D
COMMON DIMENSIONS
TOP VIEW
SIDE VIEW
PKG.
CODE
A3
A
A1
A2
S
0.05 S
FRONT VIEW
E1
B12-1
B12-2
B12-3
B12-4
B12-6
B12-7
B12-8
B12-9
B12-10
B12-11
e
SD
C
D1
B
A
1
2
3
4
A
BOTTOM VIEW
- DRAWING NOT TO SCALE -
www.maximintegrated.com
b
0.05 M
D
1.54 0.05
1.54 0.05
1.54 0.05
1.54 0.05
1.64 0.05
1.54 0.05
1.54 0.05
1.54 0.05
1.54 0.05
1.54 0.05
2.02
2.02
2.12
2.02
2.12
2.02
2.02
2.12
2.02
2.02
E
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
DEPOPULATED
SOLDER BALLS
NONE
B3
NONE
B2, B3
B3
B1, B3
B2
B2, B3
B1, B2, B3, B4
A2, C3
0.64
A1
0.24 0.03
0.40 REF
A2
0.040 BASIC
0.31 0.03
1.00 BASIC
1.50 BASIC
0.50 BASIC
A3
b
D1
E1
e
0.00 BASIC
0.25 BASIC
DEPOPULATED BUMPS:
see table on left
SD
SE
NOTES:
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
SE
B
VARIABLE DIMENSIONS
0.05
A
maxim
integrated
S AB
TITLE
TM
PACKAGE OUTLINE 12 BUMPS
WLP PKG. 0.5 mm PITCH,
APPROVAL
DOCUMENT CONTROL NO.
21-0104
REV.
I
1
1
Maxim Integrated │ 17
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
maxim
integrated
maxim
integrated
www.maximintegrated.com
TM
TM
Maxim Integrated │ 18
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
maxim
integrated
TM
maxim
integrated
www.maximintegrated.com
TM
Maxim Integrated │ 19
MAX3394E/MAX3395E/
MAX3396E
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
www.maximintegrated.com
Maxim Integrated │ 20
MAX3394E/MAX3395E/
MAX3396E
REVISION
NUMBER
REVISION
DATE
3
7/17
±15kV ESD-Protected, High-Drive Current,
Dual-/Quad-/Octal-Level Translators with
Speed-Up Circuitry
DESCRIPTION
Updated Electrical Characteristics table
PAGES
CHANGED
2–3
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2017 Maxim Integrated Products, Inc. │ 21
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