AS3845NT

SEMICONDUCTOR AS384x Current Mode Controller Description The AS3842 family of control ICs provide pin-for-pin replacement of the industry standard UC3842 series of devices. The devices are redesigned to provide significantly improved tolerances in power supply manufacturing. The 2.5 V reference has been trimmed to 1.0% tolerance. The oscillator discharge current is trimmed to provide guaranteed duty cycle clamping rather than specified discharge current. The circuit is more completely specified to guarantee all parameters impacting power supply manufacturing tolerances. In addition, the oscillator and flip-flop sections have been enhanced to provide additional performance. The RT/CT pin now doubles as a synchronization input that can be easily driven from open collector/open drain logic outputs. This sync input is a high impedance input and can easily be used for externally clocked systems. The new flip-flop topology allows the duty cycle on the AS3844/5 to be guaranteed between 49 and 50%. The AS3843/5 requires less than 0.5 mA of start-up current over the full temperature range. Features ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ 2.5 V bandgap reference trimmed to 1.0% and temperature-compensated Standard temperature range extended to 105¡C AS3842/3 oscillations trimmed for precision duty cycle clamp AS3844/5 have exact 50% max duty cycle clamp Advanced oscillator design simplifies synchronization Improved specs on UVLO and hysteresis provide more predictable start-up and shutdown Improved 5 V regulator provides better AC noise immunity Guaranteed performance with current sense pulled below ground Top view Pin Configuration Ñ PDIP (N) COMP VFB ISENSE RT/CT 1 2 3 4 8 7 6 5 8L SOIC (D8) VREG VCC OUT GND COMP VFB ISENSE RT/CT 1 2 3 4 8 7 6 5 14L SOIC (D14) VREG VCC OUT GND COMP NC VFB NC ISENSE NC RT/CT 1 2 3 4 5 6 7 14 VREG 13 NC 12 VCC 11 VC 10 OUT 9 8 PWR G GND Ordering Information AS384X Circuit Type: Current Mode Controller (See Table A) Package Style D8 = 8 Pin Plastic SOIC D14 = 14 Pin Plastic SOIC N = 8 Pin Plastic DIP D8 13 Packaging Option: T = Tube 13 = Tape and Reel (13" Reel Dia) Table A Model AS3842 AS3843 AS3844 AS3845 VCC(min) 10 7.6 10 7.6 VCC(on) 16 8.4 16 8.4 Duty Cycle Typ. 97% 97% 49.5% 49.5% ICC 0.5 mA 0.3 mA 0.5 mA 0.3 mA ASTEC Semiconductor 1 AS384x Functional Block Diagram (5.0 V) 1 COMP + 2 VFB Ð ERROR AMP (1.0 V) R 2R Current Mode Controller 5V REGULATOR (2.5 V) REF OK (5.0 V) 8 VREG 7 VCC (4 V) UVLO (6 V) PWM COMPARATOR 3 CURRENT SENSE (3.0 V) (5 V) Ð + FF S R PWM LOGIC 6 OUTPUT Pin Function Description Pin Number Function 1 2 3 4 COMP VFB Current Sense RT/CT Description This pin is the error amplifier output. Typically used to provide loop compensation to maintain VFB at 2.5 V. Inverting input of the error amplifier. The non-inverting input is a trimmed 2.5 V bandgap reference. A voltage proportional to inductor current is connected to the input. The PWM uses this information to terminate the gate drive of the output. Oscillator frequency and maximum output duty cycle are set by connecting a resistor (RT) to VREG and a capacitor (CT) to ground. Pulling this pin to ground or to VREG will accomplish a synchronization function. Circuit common ground, power ground, and IC substrate. This output is designed to directly drive a power MOSFET switch. This output can sink or source peak currents up to 1A. The output for the AS3844/5 switches at one-half the oscillator frequency. Positive supply voltage for the IC. This 5 V regulated output provides charging current for the capacitor CT through the resistor RT. 2 5 6 GND Output 7 8 VCC VREG ASTEC Semiconductor + (0.6 V) + 4 RT/CT (1.3 V) + Ð FF S R OSCILLATOR OVER TEMPERATURE T CLK [3842/43] FF 5 GND Ð Ð CLK ÷ 2 [3844/45] Figure 1. Block Diagram of the AS3842/3/4/5 Current Mode Controller Absolute Maximum Ratings Parameter Symbol Rating AS384x Unit Supply Voltage (ICC < 30 mA) Supply Voltage (Low Impedance Source) Output Current Output Energy (Capacitive Load) Analog Inputs (Pin 2, Pin 3) Error Amp Sink Current Maximum Power Dissipation VCC VCC IOUT Self-Limiting 30 ±1 5 Ð0.3 to 30 10 V V A µJ V mA 750 mW 1000 mW 950 mW ¡C ¡C ¡C ¡C Maximum Junction Temperature Operating Temperature Storage Temperature Range Lead Temperature, Soldering 10 Seconds PD 8L SOIC 8L PDIP 14L SOIC TJ TSTG TL 150 0 to 150 Ð65 to 150 300 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Conditions Parameter Supply Voltage AS3842,4 AS3843,5 Oscillator fOSC Symbol VCC 15 10 50 to 500 V V kHz Rating Unit Typical Thermal Resistances Package 8L PDIP 8L SOIC 14L SOIC θJA 95¡C/W 175¡C/W 130¡C/W θJC 50¡C/W 45¡C/W 35¡C/W Typical Derating 10.5 mW/¡C 5.7 mW/¡C 7.7 mW/¡C ASTEC Semiconductor 3 AS384x Electrical Characteristics Current Mode Controller Electrical characteristics are guaranteed over full junction temperature range (0 to 105¡C). Ambient temperature must be derated based on power dissipation and package thermal characteristics. The conditions are: VCC = 15 V, RT = 10 k½, and CT = 3.3 nF, unless otherwise stated. To override UVLO, VCC should be raised above 17 V prior to test. Parameter 5 V Regulator Output Voltage Line Regulation Load Regulation Temperature Stability 1 1 Symbol Test Condition Min. Typ. Max. Unit VREG PSRR TJ = 25¡C, IREG = 1 mA 12 ² VCC ² 25 V 1 ² IREG ² 20 mA 4.95 5.00 2 2 0.2 5.05 10 10 0.4 5.15 V mV mV mV/¡C V mV µV TCREG Line, load, temperature Over 1,000 hrs at 25¡C VNOISE ISC VFB PSRR T = 25¡C; IREG = 1 mA 12 V ² VCC ² 25 V 1 ² IREG ² 20 mA TCVFB Line, load, temperature Over 1,000 hrs at 125¡C 2.450 10 Hz ² f ² 100 kHz, TJ = 25¡C 30 4.85 Total Output Variation1 Long-term Stability 5 50 100 25 Output Noise Voltage Short Circuit Current 2.5 V Internal Reference Nominal Voltage Line Regulation Load Regulation Temperature Stability1 Total Output Variation1 Long-term Stability1 Oscillator Initial Accuracy Voltage Stability Temperature Stability1 Amplitude Upper Trip Point Lower Trip Point Sync Threshold Discharge Current Duty Cycle Limit 180 mA 2.475 2.500 2 2 0.1 2.500 2 2.525 5 5 0.2 2.550 12 V mV mV mV/¡C V mV fOSC TCf fOSC VH VL VSYNC ID TJ = 25¡C 12 V ² VCC ² 25 V TMIN ² TJ ² TMAX VRT/CT peak-to-peak 47 52 0.2 5 1.6 2.9 1.3 57 1 kHz % % V V V 400 7.5 RT = 680 ½, CT = 5.3 nF, TJ = 25¡C 46 600 8.7 50 800 9.5 52 mV mA % ASTEC Semiconductor 4 Current Mode Controller Electrical Characteristics (contÕd) AS384x Electrical characteristics are guaranteed over full junction temperature range (0 to 105¡C). Ambient temperature must be derated based on power dissipation and package thermal characteristics. The conditions are: VCC = 15 V, RT = 10 k½, and CT = 3.3 nF, unless otherwise stated. To override UVLO, VCC should be raised above 17 V prior to test. Parameter Error Amplifier Input Voltage Input Bias Current Voltage Gain Transconductance Unity Gain Bandwidth1 Power Supply Rejection Ratio Output Sink Current Output Source Current Output Swing High Output Swing Low Current Sense Comparator Transfer Gain2,3 ISENSE Level Shift2 Maximum Input Signal 2 Symbol Test Condition Min. Typ. Max. Unit VFB IBIAS AVOL Gm GBW PSRR ICOMPL ICOMPH VCOMPH VCOMPL AVCS VLS PSRR IBIAS tPD VOL VOL VOH VOH tR tF VCC(on) VCC(min) VOUV TOT TJ = 25¡C 2 ² VCOMP ² 4 V 2.475 2.500 Ð0.1 2.525 Ð1 1 V µA dB mA/mV MHz dB mA mA V 65 90 1 0.8 12 ² VCC ² 25 V VFB = 2.7 V, VCOMP = 1.1 V VFB = 2.3 V, VCOMP = 5 V VFB = 2.3 V, RL = 15 k½ to Ground VFB = 2.7 V, RL = 15 k½ to Pin 8 Ð0.2 ² VSENSE ² 0.8 V VSENSE = 0 V VCOMP = 5 V 12 ² VCC ² 25 V 0.9 2.85 60 2 0.5 5 1.2 70 6 0.8 5.5 0.7 1.1 V 3.0 1.5 1 70 Ð1 85 3.15 V/V V 1.1 V dB Power Supply Rejection Ratio Input Bias Current Propagation Delay to Output1 Output Output Low Level Ð10 150 µA ns ISINK = 20 mA ISINK = 200 mA ISOURCE = 20 mA ISOURCE = 200 mA CL = 1 nF CL = 1 nF 3842/4 3843/5 15 7.8 9 7.0 13 12 0.1 1.5 13.5 13.5 50 50 0.4 2.2 V V V V Output High Level Rise Time1 Fall Time1 Housekeeping Start-up Threshold 150 150 ns ns 16 8.4 10 7.6 1.5 125 17 9.0 11 8.2 2.0 V V V V V ¡C Minimum Operating Voltage After Turn On Output Low Level in UV State Over-Temperature Shutdown4 3842/4 3843/5 ISINK = 20 mA, VCC = 6 V ASTEC Semiconductor 5 AS384x Electrical Characteristics (contÕd) Current Mode Controller Electrical characteristics are guaranteed over full junction temperature range (0 to 105¡C). Ambient temperature must be derated based on power dissipation and package thermal characteristics. The conditions are: VCC = 15 V, RT = 10 k½, and CT = 3.3 nF, unless otherwise stated. To override UVLO, VCC should be raised above 17 V prior to test. Parameter PWM Maximum Duty Cycle Minimum Duty Cycle Maximum Duty Cycle Minimum Duty Cycle Supply Current Start-up Current ICC ICC VZ ICC = 25 mA 3842/4, VFB = VSENSE = 0 V, VCC = 14 V 3843/5, VFB = VSENSE = 0 V, VCC = 7 V Operating Supply Current VCC Zener Voltage 0.5 0.3 9 30 1.0 0.5 17 mA mA mA V Dmax Dmin Dmax Dmin 3842/3 3842/3 3844/5 3844/5 49 49.5 94 97 100 0 50 0 % % % % Symbol Test Condition Min. Typ. Max. Unit Notes: 1. This parameter is not 100% tested in production. 2. Parameter measured at trip point of PWM latch. 3. Transfer gain is the relationship between current sense input and corresponding error amplifier output at the PWM latch trip point and is mathematically expressed as follows: A= ∆ I COMP ∆VSENSE ; Ð 0.2 ≤ V SENSE ≤ 0.8 V 4. At the over-temperature threshold, TOT, the oscillator is disabled. The 5 V reference and the PWM stages, including the PWM latch, remain powered. ASTEC Semiconductor 6 Current Mode Controller Typical Performance Curves AS384x Supply Current vs Supply Voltage 25 25 Output Voltage vs Supply Voltage 20 ICC – Supply Current (mA) VOUT – Output Voltage (V) AS3843/5 AS3842/4 20 15 15 10 10 AS3843/5 0 0 5 20 25 10 15 VCC – Supply Voltage (V) 30 35 0 0 5 AS3842/4 5 5 10 15 20 25 30 VCC – Supply Voltage (V) Figure 2 Figure 3 Regulator Output Voltage vs Ambient Temperature 5.04 5.02 5.00 VREG – Regulator Output (V) 4.98 4.96 4.94 4.92 4.90 –60 IREG – Regulator Short Circuit (mA) –30 30 60 90 TA – Ambient Temperature (°C) 0 120 150 Regulator Short Circuit Current vs Ambient Temperature 160 140 120 100 80 60 40 –60 –30 0 30 60 90 TA – Ambient Temperature (°C) 120 150 Figure 4 Figure 5 ASTEC Semiconductor 7 AS384x Typical Performance Curves Current Mode Controller Regulator Load Regulation 0 100 Maximum Duty Cycle vs Timing Resistor ∆VREG – Regulator Voltage Change (mV) –4 Maximum Duty Cycle (%) 140 80 –8 –12 150°C –16 25°C –55°C 60 40 –20 –24 0 20 40 60 80 100 120 ISC – Regulator Source Current (mA) 20 0.3 1 3 RT – Timing Register (kΩ) 10 Figure 6 Figure 7 Timing Capacitor vs Oscillator Frequency 100 100 Maximum Duty Cycle Temperature Stability RT = 10 kΩ RT = 680 Ω CT – Timing Capacitor (nF) Maximum Duty Cycle (%) 10 90 80 RT = 2.2 kΩ RT = 2.2 kΩ RT = 4.7 kΩ RT = 1 kΩ 70 RT = 1 kΩ 1 60 50 RT = 10 kΩ 0.1 10 100 FOSC – Oscillator Frequency (kHz) 1M 40 –55 –35 –15 5 25 45 65 RT = 680 Ω 85 105 125 TA – Ambient Temperature (°C) Figure 8 Figure 9 ASTEC Semiconductor 8 Current Mode Controller Typical Performance Curves AS384x Current Sense Input Threshold vs Error Amp Output Voltage 1.2 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 0 1 2 3 4 5 6 VCOMP – Error Amp Output Voltage (V) TA = –55°C VFB – Error Amp Input Voltage (V) TA = 25°C TA = 125°C 2.50 2.51 Error Amp Input Voltage vs Ambient Temperature VSENSE – Current Sense Input Threshold (V) 2.49 2.48 2.47 VFB = VCOMP VCC = 15 V 2.46 –60 –30 0 30 60 90 120 15 TA – Ambient Temperature (°C) Figure 10 Figure 11 Output Sink Capability in Under-Voltage Mode 1A VCC = 6 V TA = 25°C VSAT – Output Saturation Voltage (V) IOUT _ Output Sink Current (mA) 0 TJ = 125°C Output Saturation Voltage Source Saturation VOUT – VCC –1 100 –2 TJ = –55°C 3 TJ = 25°C 10 2 Sink Saturation TJ = 125°C 1 1 0 0.5 1.0 1.5 2.0 2.5 VOUT – Output Voltage (V) 0 10 100 IOUT – Output Saturation Current (mA) 500 Figure 12 Figure 13 ASTEC Semiconductor 9 AS384x Application Information The AS3842/3/4/5 family of current-mode control ICs are low cost, high performance controllers which are pin compatible with the industry standard UC3842 series of devices. Suitable for many switch mode power supply applications, these ICs have been optimized for use in high frequency off-line and DC-DC converters. The AS3842 has been enhanced to provide significantly improved performance, resulting in exceptionally better tolerances in power supply manufacturing. In addition, all electrical characteristics are guaranteed over the full 0 to 105¡C temperature range. Among the many enhancements are: a precision trimmed 2.5 volt reference (+/Ð 1% of nominal at the error amplifier input), a significantly reduced propagation delay from current sense input to the IC output, a trimmed oscillator for precise duty-cycle clamping, a modified flip-flop scheme that gives a true 50% duty ratio clamp on 3844/45 types, and an improved 5 V regulator for better AC noise immunity. Furthermore, the AS3842 provides guaranteed performance with current sense input below ground. The advanced oscillator design greatly simplifies synchronization. The device is more completely specified to guarantee all parameters that impact power supply manufacturing tolerances. VDC >1 mA R R< AC LINE 5 GND 16 V/10 V (3842/4) 8.4 V/7.8 V (3843/5) VDC MIN 1 mA 7 AS384x VCC Current Mode Controller Section 1 Ð Theory of Operation The functional block diagram of the AS3842 is shown in Figure 1. The IC is comprised of the six basic functions necessary to implement current mode control; the under-voltage lockout; the reference; the oscillator; the error amplifier; the current sense comparator/PWM latch; and the output. The following paragraphs will describe the theory of operation of each of the functional blocks. 1.1 Under-voltage lockout (UVLO) The under-voltage lockout function of the AS3842 holds the IC in a low quiescent current (² 1 mA) ÒstandbyÓ mode until the supply voltage (VCC) exceeds the upper UVLO threshold voltage. This guarantees that all of the ICÕs internal circuitry are properly biased and fully functional before the output stage is enabled. Once the IC turns on, the UVLO threshold shifts to a lower level (hysteresis) to prevent VCC oscillations. The low quiescent current standby mode of the AS3842 allows ÒbootstrappingÓÐÑa technique used in off-line converters to start the IC from the rectified AC line voltage initially, after which power to the IC is provided by an auxiliary winding off the power supplyÕs main transformer. Figure 14 shows a typical bootstrap circuit where capacitor (C) is PRI IC ENABLE OUT 6 SEC + C + AUX Figure 14. Bootstrap Circuit ASTEC Semiconductor 10 Current Mode Controller charged via resistor (R) from the rectified AC line. When the voltage on the capacitor (VCC) reaches the upper UVLO threshold, the IC (and hence, the power supply) turns on and the voltage on C begins to quickly discharge due to the increased operating current. During this time, the auxiliary winding begins to supply the current necessary to run the IC. The capacitor must be sufficiently large to maintain a voltage greater than the lower UVLO threshold during start-up. The value of R must be selected to provide greater than 1 mA of current at the minimum DC bus voltage (R < VDCmin/1 mA). The UVLO feature of the AS3842 has significant advantages over standard 3842 devices. First, the UVLO thresholds are based on a temperature compensated bandgap reference rather than conventional zeners. Second, the UVLO disables the output at power down, offering additional protection in cases where VREG is heavily decoupled. The UVLO on some 3842 devices shuts down the 5 volt regulator only, which results in eventual power down of the output only after the 5 volt rail collapses. This can lead to unwanted stresses on the switching devices during power down. The AS3842 has two separate comparators which monitor both VCC and VREF and hold the output low if either are not within specification. The AS3842 family offers two different UVLO options. The AS3842/4 has UVLO thresholds of 16 volts (on) and 10 volts (off). The AS3843/5 has UVLO levels of 8.4 volts (on) and 7.6 volts (off). AS384x the internal reference is ± 1% over the full specified temperature range, and ± 1% for VREG. The reference section of the AS3842 is greatly improved over the standard 3842 in a number of ways. For example, in a closed loop system, the voltage at the error amplifierÕs inverting input (VFB, pin 1) is forced by the loop to match the voltage at the non-inverting input. Thus, VFB is the voltage which sets the accuracy of the entire system. The 2.5 V reference of the AS3842 is tightly trimmed for precision at VFB, including errors caused by the op amp, and is specified over temperature. This method of trim provides a precise reference voltage for the error amplifier while maintaining the original 5 V regulator specifications. In addition, force/sense (Kelvin) bonding to the package pin is utilized to further improve the 5 V load regulation. Standard 3842s, on the other hand, specify tight regulation for the 5 V output only and rate it over line, load and temperature. The voltage at VFB, which is of critical importance, is loosely specified and only at 25¡C. The reference section, in addition to providing a precise DC reference voltage, also powers most of the ICÕs internal circuitry. Switching noise, therefore, can be internally coupled onto the reference. With this in mind, all of the logic within the AS3842 was designed with ECL type circuitry which generates less switching noise because it runs at essentially constant current regardless of logic state. This, together with improved AC noise rejection, results in substantially less switching noise on the 5 V output. The reference output is short circuit protected and can safely deliver more than 20 mA to power external circuitry. 1.2 Reference (VREG and VFB) The AS3842 effectively has two precise bandgap based temperature compensated voltage references. Most obvious is the VREG pin (pin 8) which is the output of a series pass regulator. This 5.0 V output is normally used to provide charging current to the oscillatorÕs timing capacitor (Section 1.3). In addition, there is a trimmed internal 2.5 V reference which is connected to the non-inverting (+) input of the error amplifier. The tolerance of 1.3 Oscillator The newly designed oscillator of the AS3842 is enhanced to give significantly improved performance. These enhancements are discussed in ASTEC Semiconductor 11 AS384x the following paragraphs. The basic operation of the oscillator is as follows: A simple RC network is used to program the frequency and the maximum duty ratio of the AS3842 output. See Figure 15. Timing capacitor (CT) is charged through timing resistor (RT) from the fixed 5.0 V at VREG. During the charging time, the OUT (pin 6) is high. Assuming that the output is not terminated by the PWM latch, when the voltage across CT reaches the upper oscillator trip point (Å3.0 V), an internal current sink from pin 4 to ground is turned on and discharges CT towards the lower trip point. During this discharge time, an internal clock pulse blanks the output to its low state. When the voltage across CT reaches the lower trip point (Å1.3 V), the current sink is turned off, the output goes high, and the cycle repeats. Since the output is blanked during the discharge of CT, it is the discharge time which controls the output deadtime and hence, the maximum duty ratio. Current Mode Controller The nature of the AS3842 oscillator circuit is such that, for a given frequency, many combinations of RT and CT are possible. However, only one value of RT will yield the desired maximum duty ratio at a given frequency. Since a precise maximum duty ratio clamp is critical for many power supply designs, the oscillator discharge current is trimmed in a unique manner which provides significantly improved tolerances as explained later in this section. In addition, the AS3844/5 options have an internal flip-flop which effectively blanks every other output pulse (the oscillator runs at twice the output frequency), providing an absolute maximum 50% duty ratio regardless of discharge time. 1.3.1 Selecting timing components RT and CT The values of RT and CT can be determined mathematically by the following expressions: CT = D R T ƒOSC K  ln  L   KH  = 1.63D R T ƒOSC (1) 7 VCC 8 CT 5 V REG PWM CLOCK 4 OSCILLATOR ID CT AS3842 OUTPUT CT OUTPUT 6 OUTPUT Large RT/Small CT RT Small RT/ Large CT 5 GND Figure 15. Oscillator Set-up and Waveforms ASTEC Semiconductor 12 Current Mode Controller 1 1 AS384x D 1ÐD RT (KL) V = REG ¥ ID (KL) D 1ÐD D Ð (KH) Ð (KH) Table 1. RT vs Maximum Duty Ratio (2) RT (½) 470 560 683 750 Dmax 22% 37% 50% 54% 58% 63% 66% 72% 77% 81% 85% 88% 90% 91% 93% 94% 95% 96% 97% 98% D 1 = 582 ¥ (0.736) (0.736) D 1ÐD D − (0.432) − (0.432) 1 D 1ÐD D KL = VREG − V L VREG 820 ≈ 0.736 (3) 910 1,000 KH = VREG − VH VH 1,200 ≈ 0.432 ( (4) 1,500 1,800 where fosc is the oscillator frequency, D is the maximum duty ratio, VH is the oscillatorÕs upper trip point, VL is the lower trip point, VR is the Reference voltage, ID is the discharge current. Table 1 lists some common values of RT and the corresponding maximum duty ratio. To select the timing components; first, use Table 1 or equation (2) to determine the value of RT that will yield the desired maximum duty ratio. Then, use equation (1) to calculate the value of CT. For example, for a switching frequency of 250 kHz and a maximum duty ratio of 50%, the value of RT, from Table 1, is 683 ½. Applying this value to equation (1) and solving for CT gives a value of 4700 pF. In practice, some fine tuning of the initial values may be necessary during design. However, due to the advanced design of the AS3842 oscillator, once the final values are determined, they will yield repeatable results, thus eliminating the need for additional trimming of the timing components during manufacturing. 2,200 2,700 3,300 3,900 4,700 5,600 6,800 8,200 10,000 18,000 1.3.2 Oscillator enhancements The AS3842 oscillator is trimmed to provide guaranteed duty ratio clamping. This means that the discharge current (ID ) is trimmed to a value that compensates for all of the tolerances within the device (such as the tolerances of VREG, propagation delays, the oscillator trip points, etc.) which have an effect on the frequency and maximum duty ratio. For example, if the combined tolerances of a particular device are 0.5% above nominal, then ID is trimmed to 0.5% above nominal. This method of trimming virtually eliminates the need to trim external oscillator components during power supply manufacturing. Standard 3842 devices specify or trim only for a specific value of discharge current. This makes precise 13 ASTEC Semiconductor AS384x and repeatable duty ratio clamping virtually impossible due to other IC tolerances. The AS3844/5 provides true 50% duty ratio clamping by virtue of excluding from its flip-flop scheme, the normal output blanking associated with the discharge of CT. Standard 3844/5 devices include the output blanking associated with the discharge of CT, resulting in somewhat less than a 50% duty ratio. Current Mode Controller 1.4 Error amplifier (COMP) The AS3842 error amplifier is a wide bandwidth, internally compensated operational amplifier which provides a high DC open loop gain (90 dB). The input to the amplifier is a PNP differential pair. The non-inverting (+) input is internally connected to the 2.5 V reference, and the inverting (Ð) input is available at pin 2 (VFB). The output of the error amplifier consists of an active pull-down and a 0.8 mA current source pull-up as shown in Figure 17. This type of output stage allows easy implementation of soft start, latched shutdown and reduced current sense clamp functions. It also permits wire ÒOR-ingÓ of the error amplifier outputs of several 3842s, or complete bypass of the error amplifier when its output is forced to remain in its Òpull-upÓ condition. 1.3.3 Synchronization The advanced design of the AS3842 oscillator simplifies synchronizing the frequency of two or more devices to each other or to an external clock. The RT/CT doubles as a synchronization input which can easily be driven from any open collector logic output. Figure 16 shows some simple circuits for implementing synchronization. 8 Open Collector Output VREG AS3842 4 RT/CT 5V Open Collector Output 3K CMOS RT/CT 3K RT/CT 2K RT GND 5 2K CT SYNC EXTERNAL CLOCK Figure 16. Synchronization 1 COMPENSATION NETWORK COMP E/A 0.8 mA VOUT 2 VFB – TO PWM + 2.50 V Figure 17. Error Amplifier Compensation ASTEC Semiconductor 14 Current Mode Controller In most typical power supply designs, the converterÕs output voltage is divided down and monitored at the error amplifierÕs inverting input, VFB. A simple resistor divider network is used and is scaled such that the voltage at VFB is 2.5 V when the converterÕs output is at the desired voltage. The voltage at VFB is then compared to the internal 2.5 V reference and any slight difference is amplified by the high gain of the error amplifier. The resulting error amplifier output is level shifted by two diode drops and is then divided by three to provide a 0 to 1 V reference (VE) to one input of the current sense comparator. The level shifting reduces the input voltage range of the current sense input and prevents the output from going high when the error amplifier output is forced to its low state. An internal clamp limits VE to 1.0 V. The purpose of the clamp is discussed in Section 1.5. AS384x and in particular, the characteristics of the major functional blocks within the supply Ñ i.e. the error amplifier, the modulator/switching circuit, and the output filter. In general, the network is designed such that the converterÕs overall gain/phase response approaches that of a single pole with a Ð20 dB/decade rolloff, crossing unity gain at the highest possible frequency (up to fSW/4) for good dynamic response, with adequate phase margin (> 45¡) to ensure stability. Figure 18 shows the Gain/Phase response of the error amplifier. The unity gain crossing is at 1.2 MHz with approximately 57¡C of phase margin. This information is useful in determining the configuration and characteristics required for the compensation network. One of the simplest types of compensation networks is shown in Figure 19. An RC network provides a single pole which is normally set to compensate for the zero introduced by the output capacitorÕs ESR. The frequency of the pole (fP) is determined by the formula; ƒP = 1 2π Rƒ Cƒ 1.4.1 Loop compensation Loop compensation of a power supply is necessary to ensure stability and provide good line/load regulation and dynamic response. It is normally provided by a compensation network connected between the error amplifierÕs output (COMP) and inverting input as shown in Figure 17. The type of network used depends on the converter topology 80 Gain 60 Phase 40 180 150 Phase (Degrees) 120 90 20 60 30 0 0 –30 –20 101 –60 102 103 104 105 106 107 Frequency (Hz) 240 210 (5) CF VOUT RI RF Gain (dB) RBIAS Ð E/A + To PWM 2.50 V Figure 18. Gain/Phase Response of the AS3842 Figure 19. A Typical Compensation Network ASTEC Semiconductor 15 AS384x Resistors R1 and RF set the low frequency gain and should be chosen to provide the highest possible gain, without exceeding the unity gain crossing frequency limit of fSW /4. RBIAS, in conjunction with R1, sets the converterÕs output voltage; but has no effect on the loop gain/phase response. There are a few converter design considerations associated with the error amplifier. First, the values of the divider network (R1 and RBIAS) should be kept low in order to minimize errors caused by the error amplifierÕs input bias current. An output voltage error equal to the product of the input bias current and the equivalent divider resistance, can be quite significant with divider values greater than 5 k½. Low divider resistor values also help to improve the noise immunity of the sensitive VFB input. The second consideration is that the error amplifier will typically source only 0.8 mA; thus, the value of feedback resistance (RF) should be no lower than 5 k½ in order to maintain the error amplifierÕs full output range. In practice, however, the feedback resistance required is usually much greater than 5 k½, hence this limitation is normally not a problem. Some power supply topologies may require a more elaborate compensation network. For example, flyback and boost converters operating with continuous current have transfer functions that include a right half plane (RHP) zero. These types of systems require an additional pole element within the compensation network. A detailed discussion of loop compensation, however, is beyond the scope of this application note. Current Mode Controller sensing/limiting and generates a variable duty ratio pulse train which controls the output voltage of the power supply. Included is a high speed comparator followed by ECL type logic circuitry which has very low propagation delays and switching noise. This is essential for high frequency power supply designs. The comparator has been designed to provide guaranteed performance with the current sense input below ground. The PWM latch ensures that only one pulse is allowed at the output for each oscillator period. The inverting input to the current sense comparator is internally connected to the level shifted output of the error amplifier (VE) as discused in the previous section. The non-inverting input is the ISENSE input (pin 3). It monitors the switched inductor current of the converter. Figure 20 shows the current sense/PWM circuitry of the AS3842, and associated waveforms. The output is set high by an internal clock pulse and remains high until one of two conditions occurs; 1) the oscillator times out (Section 1.3) or 2) the PWM latch is set by the current sense comparator. During the time when the output is high, the converterÕs switching device is turned on and current flows through resistor RS. This produces a stepped ramp waveform at pin 3 as shown in Figure 20. The current will continue to ramp up until it reaches the level of VE at the inverting input. At that point, the comparatorÕs output goes high, setting the PWM latch and the output pulse is then terminated. Thus, VE is a variable reference for the current sense comparator, and it controls the peak current sensed by RS on a cycle-by-cycle basis. VS varies in proportion to changes in the input voltage/current (inner control loop) while VE varies in proportion to changes in the converterÕs output voltage/current (outer control loop). The two control loops merge at the current sense comparator, producing a variable duty ratio pulse train that controls the output of the converter. 16 1.5 ISENSE current comparator/PWM latch The current sense comparator (sometimes called the PWM comparator) and accompanying latch circuitry make up the pulse width modulator (PWM). It provides pulse-by-pulse current ASTEC Semiconductor Current Mode Controller AS3842/3/4/5 1 COMP ERROR AMP + 2 2.5 V VFB 1V 3 CURRENT SENSE RT/CT Ð PWM COMPARATOR VE Ð + CLOCK 2R R 5 V REG VCC 7 VREG VIN 8 PRI SEC AS384x PWM LOGIC FF S R OUTPUT 6 GND 5 IS CLOCK VE VS OUTPUT 4 VS C R Leading Edge Filter RS Figure 20. Current Sense/PWM Latch Circuit and Waveforms The current sense comparatorÕs inverting input is internally clamped to a level of 1.0 V to provide a current limit (or power limit for multiple output supplies) function. The value of RS is selected to produce 1.0 V at the maximum allowed current. For example, if 1.5 A is the maximum allowed peak inductor current, then RS is selected to equal 1 V/1.5 A = 0.66 ½. In high power applications, power dissipation in the current sense resistor may become intolerable. In such a case, a current transformer can be used to step down the current seen by the sense resistor. See Figure 21. 1.6 Output (OUT) The output stage of the AS3842 is a high current totem-pole configuration that is well suited for directly driving power MOSFETs. It is capable of sourcing and sinking up to 1 A of peak current. Cross conduction losses in the output stage have been minimized resulting in lower power dissipation in the device. This is particularly important for high frequency operation. During undervoltage shutdown conditions, the output is active low. This eliminates the need for an external pulldown resistor. 1.7 Over-temperature shutdown N:1 VS VS = IS N RS RS IS Figure 21. Optional Current Transformer The AS3842 has a built-in over-temperature shutdown which will limit the die temperature to 130¡C typically. When the over-temperature condition is reached, the oscillator is disabled. All other circuit blocks remain operational. Therefore, when the oscillator stops running, output pulses terminate without losing control of the supply or losing any peripheral functions that may be running off the 5 V regulator. The output may go high during the final cycle, but the PWM ASTEC Semiconductor 17 AS384x latch is still fully operative, and the normal termination of this cycle by the current sense comparator will latch the output low until the over-temperature condition is rectified. Cycling the power will reset the over-temperature disable mechanism, or the chip will re-start after cooling through a nominal hysteresis band. Current Mode Controller A simple RC filter is used to suppress the spike. The time constant should be chosen such that it approximately equals the duration of the spike. A good choice for R1 is 1 k½, as this value is optimum for the filter and at the same time, it simplifies the determination of RSLOPE (Section 2.2). If the duration of the spike is, for example, 100 ns, then C is determined by: C= = Time Constant 1 kΩ 100 ns 1 kΩ Section 2 Ð Design Considerations 2.1 Leading edge filter The current sensed by RS contains a leading edge spike as shown in Figure 20. This spike is caused by parasitic elements within the circuit including the interwinding capacitance of the power transformer and the recovery characteristics of the rectifier diode(s). The spike, if not properly filtered, can cause stability problems by prematurely terminating the output pulse. Ve IAVG 2 IL 2 IAVG 1 m 2 (6) = 100 pF 2.2 Slope compensation Current-mode controlled converters can experience instabilities or subharmonic oscillations Ve ∆I m 1 IPK ∆I' m 2 m IL1 T0 1 D1 (a) D2 T1 T0 D1 (b) D2 T1 VCOMP m=m VCOMP m 1 2 /2 m=m 2 /2 m 1 IL 2 IL1 IAVG 1 = IAVG 2 m ∆I 2 m ∆I' 2 T0 D1 (c) D2 T1 T0 D1 (d) D2 T1 Figure 22. Slope Compensation ASTEC Semiconductor 18 Current Mode Controller when operated at duty ratios greater than 50%. Two different phenomena can occur as shown graphically in Figure 22. First, current-mode controllers detect and control the peak inductor current, whereas the converterÕs output corresponds to the average inductor current. Figure 22(a) clearly shows that the average inductor current (I1 & I2) changes as the duty ratio (D1 & D2) changes. Note that for a fixed control voltage, the peak current is the same for any duty ratio. The difference between the peak and average currents represents an error which causes the converter to deviate from true current-mode control. Second, Figure 22(b) depicts how a small perturbation of the inductor current (ÆI) can result in an unstable condition. For duty ratios less than 50%, the disturbance will quickly converge to a steady state condition. For duty ratios greater than 50%, ÆI progressively increases on each cycle, causing an unstable condition. Both of these problems are corrected simultaneously by injecting a compensating ramp into either the control voltage (VE) as shown in Figure 22(c) & (d), or to the current sense waveform at pin 3. Since VE is not directly accessible, and, a positive ramp waveform is readily available from 8 RT 4 RT/CT AS3842 IS RSLOPE R1 CT 3 OPTIONAL BUFFER IS ISENSE GND RS 5 RS RSLOPE R1 CT 3 VREG RT 4 RT/CT AS384x the oscillator at pin 4, it is more practical to add the slope compensation to the current waveform. This can be implemented quite simply with the addition of a single resistor, RSLOPE, between pin 4 and pin 3 as shown in Figure 23(a). RSLOPE, in conjunction with the leading edge filter resistor, R1 (Section 2.1), forms a divider network which determines the amount of slope added to the waveform. The amount of slope added to the current waveform is inversely proportional to the value of RSLOPE. It has been determined that the amount of slope (m) required is equal to or greater than 1/2 the downslope (m2) of the inductor current. Mathematically stated: m≥ m2 2 (7) In some cases the required value of RSLOPE may be low enough to affect the oscillator circuit and thus cause the frequency to shift. An emitter follower circuit can be used as a buffer for RSLOPE as depicted in Figure 23(b). Slope compensation can also be used to improve noise immunity in current mode converters operating at less than 50% duty ratio. Power supplies operating under very light load can experience 8 VREG AS3842 ISENSE GND 5 (a) (b) Figure 23. Slope Compensation ASTEC Semiconductor 19 AS384x instabilities caused by the low amplitude of the current sense ramp waveform. In such a case, any noise on the waveform can be sufficient to trip the comparator resulting in random and premature pulse termination. The addition of a small amount of artificial ramp (slope compensation) can eliminate such problems without drastically affecting the overall performance of the system. Current Mode Controller large loops and keep the area enclosed within any loops to a minimum. Use common point grounding techniques and separate the power ground traces from the signal ground traces. Locate the control IC and circuitry away from switching devices and magnetics. Also, the timing capacitorÕs ground connection must be right at pin 5 as shown in Figure 15. These grounding and wiring techniques are very important because the resistance and inductance of the traces are significant enough to generate noise glitches which can disrupt the normal operation of the IC. Also, to provide a low impedance path for high frequency noise, VCC and VREF should be decoupled to IC ground with 0.1 µF capacitors. Additional decoupling in other sensitive areas may also be necessary. It is very important to locate the decoupling capacitors as close as possible to the circuit being decoupled. 2.3 Circuit layout and other considerations The electronic noise generated by any switchmode power supply can cause severe stability problems if the circuit is not layed-out (wired) properly. A few simple layout practices will help to minimize noise problems. When building prototype breadboards, never use plug-in protoboards or wire wrap construction. For best results, do all breadboarding on double sided PCB using ground plane techniques. Keep all traces and lead lengths to a minimum. Avoid ASTEC Semiconductor 20