NT6868A-0011

NT6868A Keyboard Controller Features n n n n n Built-in 6502 8-bit CPU 2 MHz CPU operation frequency 4K bytes of ROM 128 bytes of SRAM One 8-bit programmable base timer with 1 - 256 µsec interval n 29 programmable bi-directional I/O pins n 3 LED direct sink pins with internal serial resistors n Mask optional for built-in RC oscillator with an external resistor or external ceramic resonator applied n Watch-dog timer n Built-in power-on reset n Built-in low voltage reset n CMOS technology for low power consumption n Available in 40 pin DIP package and 40 pad CHIP FORM General Description NT6868A is a single chip micro-controller for keyboard applications. It incorporates a 6502 8-bit CPU core, 4K bytes of ROM, and 128 bytes of RAM used as working RAM and stack area. It also includes 29 programmable bi-directional I/O pins and one 8-bit pre-loadable base timer. Additionally, it includes a built-in low voltage reset, a 4MHz RC oscillator that requires only a resistor externally applied or a 4MHz ceramic resonator, and a watch-dog timer that prevents system standstill. Pin Configuration GND NC DATA CLK P30 P31 P32 P33 P34 RESET P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 1 2 3 4 5 6 7 8 40 39 38 37 36 35 34 33 OSCI R/OSCO VDD LED2 LED1 LED0 P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 Pad Configuration P 1 7 P 1 6 P 1 5 P 1 4 P 1 3 P 1 2 P 1 1 P 1 0 P 0 7 P 0 6 26 25 24 23 22 21 20 19 18 17 16 15 P05 P04 P03 P02 P01 P00 RESET P34 P33 P32 P20 P21 P22 P23 P24 P25 P26 P27 LED0 LED1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 14 13 12 11 10 9 8 7 NT6868A 9 10 11 12 13 14 15 16 17 18 19 20 32 31 30 29 28 27 26 25 24 23 22 21 NT6868AH 6 P31 L E D 2 V D D R / O S C O O S C I G N D N C D A T A C L K P 3 0 1 V2.1 NT6868A Block Diagram CLK TIMING GENERATOR (RC OSC/CERAMIC RESONATOR: 4MHz) 4K BYTES ROM DATA LED0 LED1 6502 CPU 128 BYTES SRAM + STACK LED2 I/O PORTS P00 - P07 INT. CONTROLLER WATCH DOG TIMER P10 - P17 P20 - P27 RESET VDD GND POWER-ON RESET/ LOW VOLTAGE RESET BASE TIMER P30 - P34 Pin and Pad Descriptions Pin No. 1 2 3 4 5 - 9, 11 - 34 10 35 - 37 38 39 40 Pad No. 1 2 3 4 5 - 9, 11 - 34 10 35 - 37 38 39 40 Designation GND NC DATA CLK P30 - P34, P00 - P27 RESET I/O P I/O I/O I/O I O P I Ground pin Description No connection, recommended to connect VDD or floating I/O, 10KΩ pull-up resistor for communication I/O, 10KΩ pull-up resistor for communication Bi-directional I/O pins RESET signal input pin with internal pull up resistor; Active low LED0 LED2 VDD R/OSCO OSCI LED direct sink pins Power supply 47KΩ resistor connected for RC OSC or 4MHz ceramic resonator connected No connection for RC OSC, connected for 4MHz ceramic resonator * Under the constraint of the maximum frequency variation, (∆F/F)max, ≤ ±1%, code 3 (ceramic resonator option) must be selected and pin 39 and pin 40 are connected to a ceramic resonator. If (∆F/F)max, ≤ ±10%, code 1 (RC OSC option) is recommended to be selected and pin39 connects a 47KΩ resistor with, ≤ ±1% accuracy to VDD and pin 40 is floating. 2 NT6868A Functional Description 6502 CPU 6502 is an 8-bit CPU. Refer to 6502 data sheet for details. 7 ACCUMULATOR A 7 INDEX REGISTER X 0 0000 SRAM 0 007F UNUSED 00C0 0 INDEX REGISTER Y SYSTEM REGISTERS 00CF STACK PTR 7 15 PROGRAM COUNTER PC 7 S 7 S V B D I Z 0 UNUSED 0 STACK POINTER SP 0 C STATUS REGISTER P F000 USER ROM FFFA CARRY FFFB ZERO INTERRUPT MASK DECIMAL MODE BREAK OVERFOLW SIGN FFFC RST-L FFFD RST-H FFFE IRQ-L FFFF IRQ-H IRQ VECTOR NMI-H NMI-L NMI VECTOR Figure 1. 6502 CPU Registers and Status Flags Figure 2. NT6868A Memory Map 3 NT6868A System Reserved Registers Address $00C0 $00C1 $00C2 $00C3 $00C4 $00C5 $00C6 $00C7 $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF - : no effect Register BT TCON CLRIRQX PORT0 PORT1 PORT2 PORT3 CLK DATA LED CLRWDT X X X X X Bit7 BT7 PD07 PD17 PD27 0 X X X X X Bit6 BT6 PD06 PD16 PD26 1 X X X X X Bit5 BT5 PD05 PD15 PD25 0 X X X X X Bit4 BT4 PD04 PD14 PD24 PD34 1 X X X X X Bit3 BT3 PD03 PD13 PD23 PD33 0 X X X X X Bit2 BT2 PD02 PD12 PD22 PD32 LED2 1 X X X X X Bit1 BT1 PD01 PD11 PD21 PD31 LED1 0 X X X X X Bit0 BT0 ENBT W W W RW RW RW RW RW RW W W X X X X X CLRIRQTMR PD00 PD10 PD20 PD30 CLK DATA LED0 1 X X X X X X : access not allowed 4K X 8 ROM The built-in ROM program code, executed by the 6502 CPU, has a capacity of 4K X 8 bits and is addressed from F000H to FFFFH. Power-On Reset Built-in power-on reset circuit can generate a 150ms pulse to reset the entire chip. The beginning of the 150ms pulse occurs at 60% of VDD when powered on. 128 X 8 SRAM The built-in SRAM is used for general purpose data memory and for the stack area. SRAM is addressed from 0000H to 007FH. User can allocate stack area in the SRAM by setting stack pointer register (S). Because the 6502C default stack pointer is 01FFH, it must be mapped to 007FH. Mapping from 01XX to 00XX is done internally by setting the S register to 7FH via software programming. For example : LDX TXS #$7F power VDD 60% The start of 150ms pulse t 4 NT6868A Timing Generation This block generates the system timing and control signal supplied to CPU and on-chip peripherals. There are two types of system clock sources: built-in RC oscillator or external ceramic resonator. Both of them are mask optional and generate a 4MHz system clock. They also generates 2MHz for CPU, and 1MHz for base timer. The following shows the relationship of code type number and oscillation type. Oscillator Type RC OSC Ceramic Resonator Code Number 1 3 The following table provides the relationship between external resistor and RC OSC frequency. (for reference only) External Resistor (KΩ ) 39 43 47 56 RC OSC Frequency (MHz) 4.7 4.44 4 3.68 Base Timer The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by CPU. After reset, the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any time. When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a timer interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and begin counting at 00H. The timer interval can be programmed from 1 - 256 µsec. The base timer can be enabled by writing a '0' to ' ENBT ' in the TCON (Timer Control) register. The ENBT is a level trigger. Base timer structure: 8-Bit timer 1µs BT pre-load data: Addr. $00C0 Timer Control Regisrer: $00C1 TCON ENBT BT7 BT6 BT5 BT4 BT2 BT2 BT1 BT0 TMRINT Bit BT 7 BT7 6 BT6 5 BT5 4 BT4 3 BT3 2 BT2 1 BT1 0 BT0 (W) (W) INT. Controller When BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by software. Once set by an interrupt source, it remains High unless cleared by writing '1' to the corresponding bit in CLRIRQX ($00C2H). This register is cleared to '0' on initialization by system reset. When an interrupt occurs, CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine. When BASE TIMER interrupt occurs and enters the interrupt service routine, the IRQTMR flag must be cleared by software. Interrupt Control Register: Addr. $00C2 Bit CLRIRQX 7 6 5 4 3 2 1 0 CLRIRQTMR (W) 5 NT6868A I/O Ports The NT6868A has 31 pins dedicated to input and output. These pins are grouped into 6 ports, as follows: PORT 0 (P00 - P07): Port 0 is an 8-bit bi-directional CMOS I/O port that is internally pulled High by PMOS. Each pin of port 0 can be bit programmed as an input or output pin under the software control. When programmed as output, data is latched to the port data register and output to the pin. Port 0 pins with ''1'' written to them are pulled high by the internal PMOS pull-ups, and are used as inputs in that state. These input signals can then be read. The port output is High after reset. PORT 1 ( P10 - P17 ) : Functions the same as PORT 0. PORT 2 ( P20 - P27) : Functions the same as PORT 0. PORT 3 ( P30 - P34) : Functions the same as PORT 0. CLK & DATA PORT Registers: Addr. $00C3 $00C4 $00C5 $00C6 $00C7 $00C8 Bit PORT0 PORT1 PORT2 PORT3 CLK DATA 7 PD07 PD17 PD27 6 PD06 PD16 PD26 5 PD05 PD15 PD25 4 PD04 PD14 PD24 PD34 3 PD03 PD13 PD23 PD33 2 PD02 PD12 PD22 PD32 1 PD01 PD11 PD21 PD31 0 PD00 PD10 PD20 PD30 CLK DATA (RW) (RW) (RW) (RW) (RW) (RW) : These two pins have the same structure as I/O ports, except for the 10KΩ internal pull-ups. VDD Latch WREN L Q DB D RST SD IO Weak PMOS RDENB IO Port Structure 6 NT6868A LED Port There are 3 LED direct sink pins which require no external serial resistors. The address is mapped to address $00C9. Addr. $00C9 Bit LED 7 6 5 4 3 2 LED2 1 LED1 0 LED0 (W) WREN L Q DB D RST SD LED [ 0 ] VDD WREN L Q DB D RST SD LED [ 1:2 ] LED0 Port Structure LED1, LED2 Port Structures Watch-Dog Timer NT6868A implements a watch-dog timer, which protects programs against system standstill. The clock of the watch-dog timer is derived from the on-chip RC oscillator. The watch-dog timer interval is about 0.175 of a second. The timer must be cleared within every 0.175 second during normal operation; otherwise, it will overflow and cause a system reset. The watch-dog timer is cleared and enabled after a system reset. It cannot be disabled by software. The user can clear the watch-dog timer by writing #55H to CLRWDT ($00CAH) register. For example: LDA STA Addr. $00CA Bit CLRWDT #$55 $00CA 7 0 6 1 5 0 4 1 3 0 2 1 1 0 0 1 (W) Low Voltage Reset (LVR) Circuit The NT6868A will check on the voltage level of power supply. When the voltage level of power supply is below a threshold of 3.0V (Typical), the LVRC will issue a reset output to the chip until the power voltage level is above the threshold voltage of 3.0V (Typical) again. As soon as the power voltage arises to 3.0V (Typical), the entire chip will be reset for about 150ms. RESET NT6868A can also be externally reset via RESET pin. A reset is initiated when the signal at the RESET pin is held Low for at least 10 system clock. As soon as RESET signal goes high, the NT6868A begins to be reset for about 150ms. The following shows the definition of RESET input low pulse width. V DD V DD 20%V DD Trstb 20%V DD 7 NT6868A Absolute Maximum Ratings* DC Supply Voltage . . . . . . . . . . . . . . . . . -0.3V to +7.0V Input/Output Voltage . . . . . . . .GND -0.2V to VDD + 0.2V Operating Ambient Temperature . . . . . . . .0°C to +70°C Storage Temperature . . . . . . . . . . . . . .-55°C to +125°C Operating Voltage (VDD) . . . . . . .. . . . . . . .+4.5V to 5.5V *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VDD = 5V, GND = 0V, TA = 25°C, FOSC = 4MHz, unless otherwise specified) Symbol ICC VIH VIL VOH1 VOH2 VOL1 VOL2 VOL3 ∆F/F ∆F/F ILED VLVR TPOR TRSTB RPH Parameter Power Supply Current Input High Voltage Input Low Voltage Output High Voltage (Port 0, 1, 2, 3) Output High Voltage (CLK, DATA) Output Low Voltage (PORT 0, 1, 2) Output Low Voltage (PORT 3) Output Low Voltage (CLK, DATA) Initial Frequency Variation 1 Frequency Variation 2 LED Sink Current (LED 0, 1, 2) Low Voltage Reset Threshold Power-on Reset Time RESET Input Low Pulse Width RESET Pull High Resistor Min. Typ. Max. 20 Unit mA V Conditions No load 2 0.8 2.4 2.4 0.4 0.4 0.4 +/-10 +/-1 10 14 3.0 120 2.5 220 150 180 17 V V V V V V % % mA V ms µs KΩ 10 system clocks IOH = -100µA IOH = -400µA IOL = 4mA IOL = 5mA IOL = 10mA For RC OSC option only; By Lots For ceramic resonator option only; By Lots VOL = 3.2V 8 NT6868A Application Circuit For Windows 98 Keyboard (for reference only) VDD 4.7 - 10mf P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31 VDD VDD GND Scroll Lock LED0 Num Lock LED1 Caps Lock LED2 0.1mf RESET NT6868A DATA CLK Optional KBD DATA KBD CLOCK VDD P20 P21 P22 P23 P24 P25 P26 P27 R/OSCO 47K (System clock can be decreased by increasing the resistance) R0 Pause Q W E R U I O P Scroll Lock K14 7 Home 8 S12 9 S13 S14 S15 S16 S17 Kor_L PgUp + Wake Up R1 Power R2 R3 Sleep R4 (R) Ctrl Z X C V M < , > . " ' | \(K42) R5 Wake Up K131 K132 K133 B N K56 APP ? / (R) Alt R6 (L) Ctrl ~ , F1 F2 % 5 ^ 6 + = F8 R7 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 F5 ! 1 @ 2 # 3 $ 4 & 7 * 8 ( 9 ) 0 Print Screen Tab Caps Lock F3 T Y } ] F7 { [ A S D F J K L : ; Esc (K45) Macro F4 G H F6 - (L) Alt Back Space 4 5 6 | \(K29) 1 End 2 3 PgDn (R) K107 (L) Shift WINL WINR Enter (R) Shift F11 Space 0 Ins . Del * Enter Num Lock / F12 F9 Delete Insert F10 Power Sleep Page Down End - Page Up Home Kor_R 9 NT6868A Application Circuit For Windows 2000 Standard Code 47K S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 P15 P30 P31 P00 P01 P02 P03 P04 P13 P14 P12 P10 P07 P06 P05 P11 P16 P17 P32 R_OSC Scroll Lock LED 0 Num Lock LED 1 Caps Lock LED 2 .1uF NT6868A/C VDD VDD 10uF GND GND R0 R1 R2 R3 R4 R5 R6 R7 P20 P21 P22 P23 P24 CLOCK P25 P26 P27 RESET 10 0.1uF DATA DATA CLOCK 10 NT6868A Key Matrix definition for Windows 2000 Standard Code Pause 126 Power 163 Sleep 164 64 R-Ctrl Wake Up 165 58 L-Ctrl 116 F5 S0 Q 17 16 Tab 31 A 110 Esc 46 Z (K131) 131 1 ~ ` F1 ! 2 1 @ S1 W 18 Caps Lock 30 32 S 45 (K45) 47 X (K132) 132 112 3 2 # S2 E 19 114 F3 33 D 115 F4 48 C (K133) 133 113 F2 4 3 $ S3 R 20 21 T 34 F 35 G 49 V 50 B 6 % 5 ^ 7 5 4 & S4 U 23 22 Y 37 J 36 H 52 M 51 N 6 + 8 7 * S5 I 24 28 } ] F7 118 39 38 K 117 F6 53 < , > 54 56 (K56) 13 = F8 9 8 ( S6 O 25 L App 162 119 . | 10 9 ) S7 P 26 27 { [ 40 : ; 41 " ' L-Alt 60 42 ? 55 _ 12 \ / R-Alt - 11 0 S8 Scroll Lock 125 62 Print 124 Screen S9 (K14) 14 Back Space 15 29 | \ (101) 1 122 F11 43 Enter 123 F12 120 F9 121 F10 S10 7 91 (Home) 92 ( 4 ) 93 Space 61 Num Lock 90 84 Delete 76 Power 163 (End) S11 8 96 ( ) 97 5 (Num) 98 ( 2 ) 99 0 (Ins) 95 / (Num) 89 75 Insert Sleep 164 S12 9 101 (Page Up) 102 ( 6 ) 3 103 (Page Dn) 104 . (Del) 100 * (Num) 105 (Num) Page Up 85 Page Down 86 S13 + 106 (Num) (K107) 107 108 Enter (Num) 83 Media Previous 181 WWW Search 188 WWW Stop 192 My Computer 197 Media 180 Next Media Stop 182 WWW Home 189 WWW Refresh 193 Home 79 Media Play 183 80 Media Mute 184 81 End S14 Wake Up 165 L-Shift 44 R-Shift 57 Volume + 185 S15 Volume 186 L-Win 160 WWW Forward 191 Media Select 195 WWW Mail 187 WWW Back 190 WWW Bookmark 194 S16 Kor_L 134 R-Win 161 Kor_R 135 S17 Calculator 196 S18 R0 R1 R2 R3 R4 R5 R6 R7 11 NT6868A Bonding Diagram P 1 7 P 1 6 P 1 5 P 1 4 P 1 3 P 1 2 P 1 1 P 1 0 P 0 7 P 0 6 26 25 24 23 22 21 20 19 18 17 16 15 P05 P04 P03 P02 P01 P00 RESET P34 P33 P32 P20 P21 P22 P23 P24 P25 P26 P27 LED0 LED1 27 28 29 30 31 32 33 34 35 36 37 38 39 NT6868AH Y 14 13 12 11 X 10 9 8 7 (0, 0) 1752.6µm 40 1 2 3 4 5 6 P31 L E D 2 V D D R / O S C O O S C I G N D N C D A T A C L K P 3 0 1930.4 µm *Substrate Connect to VDD or Keep Floating Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Designation GND NC DATA CLK P30 P31 P32 P33 P34 RESET P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 X -74.4 55.6 185.6 445.6 575.6 812.9 818.1 818.1 818.1 818.1 818.1 818.1 818.1 818.1 818.1 818.1 426.1 296.1 166.1 36.1 Y -712.1 -727.5 -727.5 -727.5 -727.5 -728.1 -460.6 -330.6 -200.6 -70.6 59.4 189.4 319.4 449.4 579.4 721.9 727.5 727.5 727.5 727.5 Pad No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Designation P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 LED0 LED1 LED2 VDD R/OSCO OSCI X -93.9 -223.9 -353.9 -483.9 -613.9 -756.4 -818.2 -818.2 -818.2 -818.2 -818.2 -818.2 -818.2 -818.2 -818.2 -818.2 -594.4 -464.4 -334.4 -204.4 unit: µm Y 727.5 727.5 727.5 727.5 727.5 727.5 519.3 389.3 259.3 129.3 -0.7 -130.7 -260.7 -390.7 -520.7 -666.8 -661.6 -661.6 -661.6 -661.6 12 NT6868A Ordering Information Part No. NT6868AH NT6868A Package CHIP FORM 40L DIP Code Type No. 1 3 Oscillation Type Built-in RC OSC Ceramic Resonator Function Windows 95 keyboard Package Type DIP COB Order Information NT6868A-0011 NT6868AH-0046 NT6868A-10100 NT6868AH-10088 Windows 98 keyboard DIP COB 13 NT6868A Package Information DIP 40L Outline Dimensions D 40 21 unit: inches/mm E1 1 S 20 E C A2 A A1 Base Plane Seating Plane B B1 e1 α eA L Symbol A A1 A2 B Dimensions in inches 0.210 Max. 0.010 Min. 0.155±0.010 0.018 +0.004 -0.002 0.050 +0.004 -0.002 0.010 +0.004 -0.002 2.055 Typ. (2.075 Max.) 0.600±0.010 0.550 Typ. (0.562 Max.) 0.100±0.010 0.130±0.010 0° ~ 15° 0.655±0.035 0.093 Max. Dimensions in mm 5.33 Max. 0.25 Min. 3.94±0.25 0.46 +0.10 -0.05 1.27 +0.10 -0.05 0.25 +0.10 -0.05 52.20 Typ. (52.71 Max.) 15.24±0.25 13.97 Typ. (14.27 Max.) 2.54±0.25 3.30±0.25 0° ~ 15° 16.64±0.89 2.36 Max. B1 C D E E1 e1 L α eA S Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash. 14